JP2002328964A - Logical verification system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a logical verification system which does not need all hierarchy of HDL description included in a circuit of logical verification, also does not need extensive increase of storage capacity based on a large scale circuit, and can reduce time of the logical verification. SOLUTION: In this invention, the logical verification system conducts verification by formal verification of LSI which is hierarchically designed, and is characterized by preparing an intermediate code generation part 41, which extracts a signal name in the circuit from HDL description of RTL level of the target circuit in the LSI circuit that is to be a target for the logical verification, extracts category of input/output of each signal, and also extracts an intermediate code of the logical formula of the target circuit; a beginning and ending point analysis part 42, which analyses a signal of the beginning and ending point of the logical verification from the category; and a logical verification part 44, which processes logical comparison of HDL description of RTL level to HDL description of gate level of the LSI circuit or net list generated from the description within the limits from the beginning point to the ending point.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic verification method for performing formal verification of a circuit designed using a logic description language in circuit design of an LSI (Large Scale Integrated Circuit) or the like. Here, formal verification is a technique for mathematically verifying whether or not a circuit operates normally. For example, RTL-level HDL description, gate-level HDL description, or a netlist generated therefrom are used. And the two circuits are logically compared to detect whether or not the functions of the two circuits are equivalent.

[0002]

2. Description of the Related Art Conventionally, RTL (Register Transfer Level) has been used.
l) A logic verification system that formally verifies a level HDL (hardware description language) and a gate level HDL or an RTL level HDL and a netlist verifies a start point and an end point in a circuit to be verified. External input terminal and external output terminal of the circuit that performs
External input terminal of the circuit, input terminal of FF (flip-flop) in the circuit, output terminal and external output terminal of FF in the circuit, input terminal of FF (flip-flop) and other F
The logic of this circuit is verified as one of the combinations of the output terminals of F. Here, L with a large number of gates
When designing an SI, a method based on a hierarchical design has become mainstream, and the above-described formal verification is
This process is performed for each module constituting a circuit in each layer.

[0003]

However, in the above-described conventional logic verification system, when performing logic verification using formal verification of a hierarchically designed large-scale LSI, the HDL description of all layers is described. ,
If the designer does not manually create the logic verification system, the logic verification system cannot be executed, and the logic verification is not efficient.

That is, in the conventional logic verification system, the starting point and the ending point of the logic verification are external input, external output, FF input, FF output, etc., and between the external input and external output, between the external input and FF input, In the logic verification between the FF output and the external output and between the FF output and the FF input, when performing a logic verification of a circuit described in RTL level HDL including a lower layer module (hereinafter, lower module), this circuit is used. Therefore, the HDLs of all the layers included in the circuit for performing the logic verification are indispensable.

Further, in the conventional logic verification system, when a large-scale LSI circuit is designed, the hierarchical structure becomes deeper and the number of modules to be used increases. However, there is a disadvantage that a large storage area is required for the logic verification system in order to store. That is, in the conventional logic verification system, since the starting point and the ending point of the logic verification are the external input, the external output, the FF input, and the FF output, the external input-external output, the external input-FF input, the FF output- Between external outputs,
In order to perform logic verification between the FF output and the FF input, when performing logic verification of a circuit including many lower modules, the RTL level HDL description and the gate level HDL description of these lower modules or the RT level of the lower module are performed.
All L level HDL description and netlist information,
This is because the data needs to be stored in the storage area of the logic verification system.

Further, in the conventional logic verification system, when a large-scale LSI circuit is designed, the circuit scale is increased. Therefore, the logic verification of all modules in each hierarchy is performed. However, there is a problem that the processing time becomes longer and the design efficiency is reduced. The present invention has been made under such a background, and does not require the HDL description of all the layers included in the circuit to be subjected to the logic verification, and needs to greatly increase the storage capacity as the circuit becomes larger. It is an object of the present invention to provide a logic verification system which has no problem and can reduce the logic verification time.

[0007]

A logic verification system according to the present invention is a logic verification system for performing a logic verification by formal verification of a hierarchically designed LSI circuit, wherein the LSI circuit to be subjected to the logic verification is provided. From the RTL-level HDL description of the circuit of the target circuit in the table, an intermediate code for extracting a signal name used in the target circuit, an input / output type of each signal, and an intermediate code comprising a logical expression of the target circuit A generation unit, a start / end point analysis unit for analyzing signals serving as a start point and an end point of logic verification based on the type, the RTL level HDL description, and the LSI
A logic verification unit for comparing the logic with the HDL description at the gate level of the circuit or the netlist generated from the description within the range of the start point and the end point.

The logic verification system according to the present invention is characterized in that the start and end signals include a module output signal and a module input signal of a lower module used in the target circuit. The logic verification system according to the present invention is characterized in that a symbol indicating a start point and an end point of each signal analyzed by the start / end point analysis unit is stored in the storage unit in association with each of the signal names.

A logic verification program for operating a logic verification system according to any one of claims 1 to 4, wherein the logic verification program of the present invention performs logic verification by formal verification of a hierarchically designed LSI circuit. From the RTL level HDL description of the circuit of the target circuit in the LSI circuit to be subjected to the logic verification, the signal name used in the target circuit, the input / output type of each signal, and the An intermediate code generation process for extracting an intermediate code consisting of a logical expression, a start / end point analysis process for analyzing signals serving as a start point and an end point of logic verification from the type, an HDL description at the RTL level,
A logic verification process for comparing the logic with the HDL description at the gate level of the SI circuit or the netlist generated from the description within the range of the start point and the end point.

In the logic verification system using formal verification according to the present invention, when performing logic verification on a hierarchically designed LSI circuit, a module input and a module output are taken into consideration at the start and end points of the logic verification, so that an external input- Between external outputs, between external inputs and FF inputs, between FF outputs and external outputs, between FF outputs and FF inputs, between external inputs and module inputs, between FF outputs and module inputs, and between module outputs and external outputs Between and module output-
Logic verification is performed between the FF input and between the module output and the module input, and there is a logic verification unit that does not require circuit information of a lower module.

[0011]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a configuration of a logic verification system according to an embodiment of the present invention.
In this figure, the logic verification unit 4 has a RTL level HD.
When a file 1 of an L description (a circuit description format capable of generating a logic circuit) and a file 2 (a generated circuit-level description format) described in a gate-level HDL description or a netlist are input, the file 1 A circuit described in RTL-level HDL (hereinafter, a target circuit);
The logical comparison with the circuit described in the gate level HDL description or the netlist of the file 2 is performed.

That is, the logic verification system 4 uses the RTL
This is a system for verifying the logical equivalence between the target circuit described in the HDL of the level and the circuit described in the file 2. Here, the circuit of the file 1 is the RT for logic verification.
This is described using an L (register transfer level) hardware description language, and is described in, for example, RTL level Verilog-HDL (registered trademark), VHDL, or the like.

The circuit described in the file 2 is different from the circuit described in RTL level HDL.
This is a circuit to be subjected to logical comparison.
ilog-HDL (registered trademark), VHDL (VHSIC Hardw
aare Description Language) and EDIF (Electronica)
l Design Interchange Format). The circuits described in this file 2 include:
External input, external output, FF input,
FF output, module input and module output signal, external input signal name, external output signal name, FF input signal name, FF output signal name, module input signal name, module name The output signal name is assigned.

The technology library 3 stores input / output pin information of logic gates used in the gate level HDL or netlist 2, input / output pin information of FFs, and logic information of logic gates for each logic gate. It is a library described as follows. The logic verification unit 4 includes an intermediate code generation unit 41, a start / end point analysis unit 42, a storage area 43, a logic verification processing unit 44, and a verification result output unit 45. The intermediate code storage unit 5 is a storage unit for temporarily storing the intermediate code of the target circuit described in the file 1 created by the logic verification unit 4.

Next, the intermediate code generation unit 41, the start / end point analysis unit 42, the storage area 43, the logic verification processing unit 44, and the verification result output unit 45 constituting the logic verification unit 4 will be described in order. The intermediate code generation unit 41 extracts, from the description of the target circuit in the file 1, an intermediate code in a format that can be easily processed by the start / end point analysis unit 42, that is, the signal names input to and output from the target circuit and the signals , Or the type output from the target circuit, and the extracted result is stored in the intermediate code storage unit as an intermediate code.

The start / end point analysis unit 42 extracts each signal of external input, external output, FF input, FF output, module input, and module output from the description of the target circuit in the file 1, and performs logical comparison of these signals. A distinction is made between the signal at the start point and the signal at the end point for performing the logic verification as described above, and are set in the storage area 43, respectively. The start point indicates a signal that starts logic verification when logic verification is performed, and the end point indicates a signal that ends logic verification. That is,
The starting point indicates each signal of the external input m, FF output, and module output, while the ending point indicates the external output, FF input,
Refers to each signal of the module input.

The logic verification processing unit 44 includes, for example, a BDD
By performing formal verification using (Binary Decision Diagram), a logical comparison is performed between the target circuit described in the file 1 and the circuit described in the file 2, and the equivalence is determined.
That is, the logic verification processing unit 44
Comparison between the target circuit described in the HDL at the level HDL and the circuit described in the HDL at the gate level in the file 2, or the target circuit described in the HDL at the RTL level in the file 1 and the netlist in the EDIF format For comparison with the described circuit, the logic between the start point and the end point set by the start / end point analysis unit 42 is verified by formal verification. The verification result output unit 45 outputs a result of logical comparison between the target circuit of the file 1 verified by the logic verification processing unit 44 and the lower order described in the file 2, that is, the equivalence between the target circuit and the circuit. Is displayed on a CRT (Cathode-Ray Tube) or output as a file.

Next, the operation of the logic verification system according to the above-described embodiment will be described with reference to FIGS. FIG.
5 is a flowchart illustrating an operation example of the logic verification system according to one embodiment. First, the intermediate code generation unit 41
Reads the RTL-level HDL description of the target circuit in the file 1 (step 201), extracts the logical information by syntax analysis of the read RTL-level HDL description, and processes the read-out RTL-level HDL description in a format that can be easily processed by the start / end point analysis unit 42. The intermediate code is converted into an intermediate code, and the intermediate code is stored in the intermediate code storage unit 5 (step 202).

Here, the intermediate code in a format that is easy to process is, as shown in FIG.
, A start / end point type 302 indicating a start point and an end point of each signal of the signal name 301, and a logical expression 303 of the signal. The intermediate code generation unit 41 performs syntax analysis,
In the target circuit described in the HDL at the RTL level of the file 1, the description part of the logical description in which the logical expression is described, and the input / output signal is "bus format" in the description of the port
A register description portion describing whether the data is in one of "register format" and a "module format" and a module description portion describing a connection relationship with a lower module are determined.

The intermediate code generation unit 41 extracts logical description information from the description part of the logical expression. If the signal input / output from the register description part is the “bus format”, the external input signal and the external Output signal, register format
If so, register description information as an FF input signal and an FF output signal is extracted, module description information is extracted from the module description portion as a module input signal and a module output signal, and the extracted information is used as information of an intermediate code.

Further, the intermediate code generation unit 41 converts the signals input / output from / from the target circuit into external input signal names, external output signal names, FF input signal names, FF output signal names, It is extracted as a module input signal name and a module output signal name, and is associated with the above-described logic description information, register description information, and module description information to be used as intermediate code information. The intermediate code generation unit 41 classifies the extracted signals into external input signal names, external output signal names, FF input signal names, FF output signal names, module input signal names, and module output signal names. Then, it is described in the column of the signal name 301 in the table shown in FIG.

In the storage area 43, the intermediate code generation unit 41 stores, in the column 302 of the type of the start and end points (start point and end point) of the table shown in FIG. The signal is "I" as an external input terminal,
"O" as an external output terminal and "F" as an FF input terminal
I "," FO "as the FF output terminal," MI "as the module input terminal," M "as the module output terminal
O ", a specific symbol is described corresponding to the type of signal, and the type of each signal is expressed. Then, the intermediate code generation unit 41 describes (stores) the extracted logical description as a logical expression in the logical expression column 303 as shown in FIG.

Next, Verilog-HDL (registered trademark) shown in FIG.
As an example, the target circuit described by the RTL level of
The operation of generating the intermediate code shown in FIG. 3 from the target circuit will be specifically described. The intermediate code generation unit 41 is configured as shown in FIG.
In “x = a + xb * c;” in the equation (1), the signal name “x” is defined as output, and is represented by the symbol “O”.
"A" is defined as input and expressed by the symbol "I",
“C” is defined as a register output and is represented by the symbol “FO”, and each expression is written in the column 302 of the start / end point type.

Further, the intermediate code generation unit 41 does not express the start / end point type as a signal name because “xb” is a logical expression definition. Then, the intermediate code generation unit 41
As the logical expression of the logical description in the logical expression column 303 of “a +
xb * c ". Further, the intermediate code generation unit 41
Assigns a pointer to each signal in the column 301 of each signal name so that the start / end point type of each signal of the logical expression can be detected in each column of the table of FIG. Is set to indicate the expression in the column 302 of the start / end point type corresponding to.

Similarly, the intermediate code generation unit 41 attaches a pointer to each element of the logical expression in the logical expression column 303, and assigns a pointer to each element of the logical expression in the signal name column 301 corresponding to this element. The association is performed by pointing each signal. Next, the intermediate code generation unit 41 sets the element “xb”
Is a logical expression definition by “xb = b + d;” in the expression (2) in FIG. 4, a pointer is attached to the element “xb” in the logical expression column 303, and the element “b” in the column 303 is
+ d "and associate the element" xb "with the element" b + d ". As described above, the intermediate code generation unit 4
Numeral 1 designates columns 301 and 30 shown in FIG. 3 for associating each element of equations (1), (2) and (3).
2. As shown in a column 303, each corresponding element is connected (associated) by a pointer (the arrow in FIG. 3 indicates the association by the pointer).

Next, the start / end point analysis unit 42 determines an input / output description, a register description, and a module description from the intermediate code 5 by syntax analysis. Then, the start / end point analysis unit 42
Indicates that the signals of the external input signal name (for example, the signal name “x”), the FF output signal name (for example, the signal name “c”), and the module output signal name are used as the signal of the starting point of the logic verification, and The signal of the signal name (for example, the signal name “a”), the FF input signal name, and the module input signal name are stored in the storage area 43 as the signal of the end point of the logic verification (Step 20).
3).

Next, in the logic verification of the target circuit described in the input file 1 and the circuit described in the file 2, the logic verification processing unit 44 checks the signal name of the column 301 stored in the storage area 43. Perform logic verification by formal verification within the range. Therefore, the logic verification processing unit 44 determines, for the target circuit described in the HDL at the RTL level of the file 1, the logic description and the column 303 of the intermediate code storage unit 5 of the intermediate code generated by the intermediate code generation unit 41. The circuit described using the HDL or netlist at the gate level of the file 2 using the column 301 and the column 302 is described from the technology library 3 as follows.
Using the logic description generated with reference to the pin information and the logic information of the circuit block and the range of the start and end points, a logical comparison between the target circuit of file 1 and the circuit of file 2 is performed, and the transparency obtained as the comparison result is obtained. The result of the sex determination is output to the result output unit 45. Then, the verification result output unit 45 displays the input transparency determination result as a display on a CRT, or
This is performed as output to a file (step 204).

As described above, in the logic verification system according to the embodiment, since the logic comparison in the LSI circuit can be performed within the range of the start and end points, the module output signal from the lower module and the module input signal to the lower module are constantly changed. Since it is used as a point, even if there is no circuit description of a lower module, the target circuit described in file 1
Since the logical comparison with the circuit described in the file 2 can be performed, even if the number of lower modules increases,
Unlike the related art, it is not necessary to store the description in HDL of the circuits of all the modules in each layer, so that the storage capacity does not increase significantly, and the storage capacity in logic verification can be prevented from increasing.

Further, in the logic verification system according to the embodiment, since the logic comparison in the LSI circuit can be performed within the range of the start and end points, the module output signal from the lower module and the module input signal to the lower module are used as the start and end points. Therefore, even if there is no circuit description of the lower module, the target circuit described in file 1 and the file 2
Can be logically compared with the circuit described in (1), compared to performing the logic verification of the entire LSI circuit, that is, all the layers as in the conventional case, and comparing the logical description of the lower module with the lower circuit hierarchy. Since the comparison does not need to be performed, the time for logical comparison can be reduced, and the efficiency of LSI circuit design can be improved.

Further, in the logic verification system according to one embodiment, since the logic comparison in the LSI circuit can be performed within the range of the start and end points, the module output signal from the lower module and the module input signal to the lower module are used as the start and end points. Therefore, even if there is no circuit description of the lower module, a logical comparison between the target circuit described in the file 1 and the circuit described in the file 2 can be performed. But
Logic verification can be performed, and the efficiency of LSI circuit design can be improved.

In addition, in the logic verification system according to the embodiment, since the logic comparison in the LSI circuit can be performed within the range of the start and end points, the module output signal from the lower module and the module input signal to the lower module are set as the start and end points. Since the target circuit described in the file 1 and the circuit described in the file 2 can be logically compared without using the circuit description of the lower module, the description of the lower module is input by human input. Then, since there is no need to create the LSI circuit, the efficiency of LSI circuit design can be improved.

Next, a program executed by the computer according to the embodiment of the present invention will be described. The program to be executed by the CPU of the computer system in the LSI logic verification system in FIG.
A program according to the present invention is configured.

As a recording medium for storing this program, a magneto-optical disk, an optical disk, a semiconductor memory, a magnetic recording medium, or the like can be used.
M, RAM, CD-ROM, flexible disk, memory card and the like may be used.

The recording medium is a fixed medium such as a volatile memory such as a RAM in a computer system serving as a server or a client when a program is transmitted through a network such as the Internet or a communication line such as a telephone line. The one that holds the time program is also included.

The above program may be transmitted from a computer system storing this program in a storage device or the like to another computer system via a transmission medium or by a transmission wave in the transmission medium.
The transmission medium refers to a medium having a function of transmitting information, such as a network (communication network) such as the Internet or a communication line (communication line) such as a telephone line.

The above program may be for realizing a part of the above-mentioned functions. Furthermore, what can realize the above-described function in combination with a program already recorded in the computer system, that is, a so-called difference file (difference program) may be used.

Therefore, by using this program in a system or apparatus different from the system or apparatus of FIG. 1, and executing the program by a computer of the system or apparatus, the functions and effects described in the above embodiment can be obtained. Equivalent functions and effects can be obtained, and the object of the present invention can be achieved.

As described above, one embodiment of the present invention has been described in detail with reference to the drawings. However, the specific configuration is not limited to this embodiment, and a design change or the like may be made without departing from the gist of the present invention. The present invention is also included in the present invention.

[0039]

As described above, according to the present invention,
When performing logic verification by formal verification on a hierarchically designed LSI circuit, in addition to the external input, the external output, the FF input, and the FF output,
By considering the module input and the module output, the circuit information of the lower module can be executed without the need, so that there is an effect that the formal verification can be executed even during the design of the lower module. Further, since the circuit can be executed without requiring the circuit information of the lower module, it is effective in reducing the memory amount of the logic verification system and the processing time.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a logic verification system according to an embodiment of the present invention.

FIG. 2 is a flowchart showing an operation of the logic verification system according to one embodiment of the present invention.

FIG. 3 is a conceptual diagram showing a configuration of an intermediate code in the logic verification system according to one embodiment of the present invention.

FIG. 4 is a conceptual diagram showing a description example of a target circuit at an RTL level in Verilog-HDL (registered trademark).

[Explanation of symbols]

 Reference Signs List 1 RTL level HDL 2 Gate level HDL or netlist 3 Technology library 4 Logic verification system 5 Intermediate code storage unit 41 Intermediate code generation unit 42 Start / end point analysis unit 43 Storage area 44 Logic verification processing unit 45 Verification result output unit 301 Signal name column 302 Start / end point type column 303 Logical expression column

Claims (4)

[Claims] 1. An RTL-level HDL description of a circuit of a target circuit in an LSI circuit to be subjected to logic verification in a logic verification system for performing a logic verification by formal verification of a hierarchically designed LSI circuit. A signal name used in the target circuit, an input / output type of each signal, an intermediate code generation unit for extracting an intermediate code composed of a logical expression of the target circuit, a starting point of logic verification from the type, A start / end point analysis unit for analyzing a signal serving as an end point; comparing the logic of the RTL level HDL description with the gate level HDL description of the LSI circuit or a netlist generated from the description; A logic verification system comprising: a logic verification unit that performs the verification within an end point range. 2. The logic verification system according to claim 1, wherein the signals at the start point and the end point include a module output signal and a module input signal of a lower module used in the target circuit. 3. The storage unit according to claim 1, wherein a symbol indicating a start point and an end point of each signal analyzed by the start / end point analysis unit is stored in the storage unit in correspondence with each signal name. Logic verification system. 4. A logic verification program for operating a logic verification system according to claim 1, wherein the logic verification is performed by formal verification of the hierarchically designed LSI circuit. From the RTL level HDL description of the circuit of the target circuit in the LSI circuit, an intermediate code consisting of signal names used in the target circuit, input / output types of each signal, and a logical expression of the target circuit An intermediate code generation process for extracting the HDL description, an RTL level HDL description, a gate level HDL description of the LSI circuit, or a description thereof. And a logic verification process for comparing the logic with the netlist generated from within the range of the start point and the end point. A logic verification program characterized by the following.