JP2002328880A - Image processing module and image processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent abnormality or the like from being caused in data to be processed and to reduce power consumption in an image processing module of a low priority when using a system bus. SOLUTION: A signal processing part 16 carrying out a prescribed processing to the data of one block unit with the pixel data of each area obtained by dividing a screen into a plurality of screens as one block is provided. By each DMA(direct memory access) requests of DMA request control parts 11 and 13 on an input side and on an output side, the input of the data of one block to an input processing part 16 and the output of the data from an output processing part 17 are respectively carried out. At the point of time at which a signal processing in the signal processing part is ended, in the case that the DMA request is generated from the DMA request control part 11 or 13 on the input side or on the output side, the signal processing by the signal processing part 14 is stopped.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing module for performing predetermined processing on image data output from an image pickup section using a solid-state image pickup device such as a digital still camera, and an image processing device using the same.

[0002]

2. Description of the Related Art In a digital still camera, image data picked up by a CCD, which is a solid-state image pickup device, is processed by an image processing device into a digital clamp or the like, and data generation processes such as luminance data and color difference data. JPEG compression processing and the like based on the luminance data, color difference data, and the like are performed and stored in an external memory.

FIG. 9 is a block diagram showing an example of such an image processing apparatus. The image processing apparatus 20 has a plurality of image processing modules 25 to 27 each of which performs predetermined processing on image data. Although three first to third image processing modules 25 to 27 are illustrated in the image processing apparatus 20 illustrated in FIG. 9, other than these image processing modules 25 to 27 are not particularly illustrated. However, an image processing module that performs another predetermined process is provided.

[0004] Here, a first image processing module 25 for performing a process of capturing image data captured from the CCD into the image processing apparatus, and color image data from the CCD image data captured by the first image processing module 25. A second image processing device 26 that performs signal processing for generating luminance data and color difference data based on the data of the filter array, and performs JPEG compression processing on the luminance data and color difference data generated by the second image processing module 26. The third image processing module 27 will be described.

In addition to the first to third image processing modules 25 to 27, the second image processing module 2
An image processing module that performs signal processing on the image data signal-processed by the C.6 into display data for a display such as a CRT or a liquid crystal panel, for example, JPEG data signal-processed by the third image processing module 27, etc. Communication module and the like are provided.

First to third image processing modules 25 to
27 outputs a DMA (Direct Memory Access) request signal for requesting data input / output using the system bus 29 to the DMAC (DMA controller) module 21. The DMAC module 21 includes an overtaking prohibition circuit 21a and a priority determination circuit 21b.
When the request A conflicts, a use request signal DMBREQ for the system bus 29 is output to the conflict control unit 22 and the use request signal DM for the system bus 29 from the conflict control unit 22 is output.
Priority is set based on GNT and DMGNTD.

The competition control section 22 includes a CPU & if unit 23 having a CPU and an interface section.
From the system bus 29, the contention request signal CPBREQ is input to the contention control unit 22.
For PBREQ, the management signals DMGNT and DMG
The NTD is output to the CPU & if unit 23.

In the first image processing module 25 having the highest priority, the output of a CCD provided as an imaging unit is
A / D converted and input in a digitized state are taken in the image processing device and output to the external memory 28 via the system bus 29. Input and output of data to and from the external memory 28 is performed by the external memory controller 24.
Is controlled by the

[0009] The first image processing module 25 performs an input process such as a digital clamp on input digital data from the CCD. When the data is fetched by the first image processing module 25, when the data is stored in the external memory 28 using the system bus 29, the DMA request signal DREQO-A is
Output to module 21. First image processing module 2
5 receives the DMA acknowledge signal DACKO-A from the DMAC module 21 and outputs the data that has been fetched to the system bus 29. The fetch processing data output to the system bus 29 is stored in the external memory 28 by the external memory controller 24.

[0010] The second image processing module 26 transfers the capture processing data stored in the external memory 28 to the system bus 2.
9 when reading using the DMA request signal DREQI
-B is output to the DMAC module 21. And D
DMA acknowledge signal DACKI- from MAC 21
When B is given, the fetch processing data stored in the external memory 28 is input via the system bus 29.

The second image processing module 26 carries out signal processing for generating luminance data and color difference data on the input capture processing data based on the data of the color filter array. Then, when outputting predetermined signal-processed data to the external memory 28 via the system bus 29, it outputs a DMA request signal DREQO-B to the DMAC module 21. The second image processing module 26 includes:
DMA acknowledge signal DACKO from DMAC 21
When −B is given, the data subjected to the predetermined processing is output to the system bus 29, and the data output to the system bus 29 is transmitted to the external memory controller 24 by the external memory controller 24.
It is stored in the external memory 28.

In addition to the above processing, the second image processing module 26 includes a filter processing for removing noise, a filter processing for reducing a decrease in image quality when performing enlargement or reduction processing by interpolation, and the like. These filtering processes need to capture not only the image data of the pixel to be processed, but also the image data of the pixels surrounding the pixel. For this purpose, the second image processing module 26 divides the entire screen into a plurality of rectangular small areas (hereinafter, referred to as blocks), and inputs and outputs image data in divided block units.

The third image processing module 26 outputs a DMA request signal DREQI-C to the DMAC module 21 when reading out the luminance data and the color difference data stored in the external memory 28, and outputs a DMA acknowledge signal from the DMAC module 21. By receiving the DACKI-C, the luminance and color difference data stored in the external memory 28 are input via the system bus 29.

The third image processing module 27 performs JPEG compression processing on the input luminance data and chrominance data, and outputs the generated compressed data to the system bus 29 when transmitting the DMA request signal DREQO-C to the DMAC. Output to module 21. And the DMAC module 2
By receiving the DMA acknowledge signal DACKO-C from No. 1, the compressed data is output to the system bus 29, and the compressed data output to the system bus 29 is
The external memory controller 24 controls the external memory 28
Is stored in

In the image processing apparatus having such a configuration, the first
DM for the third image processing modules 25 to 27
In order to securely store digital data output from the CCD in the external memory 28, the first image processing module 25 has the highest priority. The second image processing module 26 The third image processing module 27 is set in this order. The image processing module with a lower priority uses the DMA acknowledgment signal output from the DMAC module 21 during the period when the image processing module with a higher priority is not performing data input / output using the system bus 29. 29, the input and output of data are performed.

In particular, the first image processing module 25
Since the digital data output from the CD is sequentially transferred, it is necessary to take in the data to be transferred in sequence and perform a predetermined process on the taken-in data sequentially. Must be output to the external memory unit 29 immediately. For this, the first
In response to a DMA request from the image processing module 25,
It is necessary to minimize the waiting time until the data is output to the system bus 29, and it is necessary to surely output the data from the first image processing module 25 sequentially. Therefore, the priority of the DMA request of the first image processing module 25 is set high.

As described above, the image processing apparatus 20
In addition to the first to third image processing modules 25 to 27, for example, a display image processing module which needs to sequentially transfer display data to a display such as a liquid crystal panel is provided. This display image processing module also
Similarly to the first image processing module 25, since it is necessary to sequentially process data, the standby time from when a DMA request is issued to when display data is output to the system bus 29 is reduced, and the processing time is obtained. It is necessary to output the display data sequentially. Therefore, this image display module is also set to have a high priority for the DMA request.

FIG. 10 shows a first example used in the image processing apparatus.
It is a block diagram which shows the structure of the 3rd image processing module. Each of the first to third image processing modules has the same configuration, and includes an overall control unit 31, an input processing unit 32, a signal processing unit 33, and an output control unit 34 which are respectively controlled by the overall control unit 31. And

The overall control unit 31 includes a DMAC module 2
1, a DMAC request signal D requesting data input
REQI is output, and DM from the DMAC module 21 is output.
By receiving the A acknowledge signal DACKI, the data stored in the external memory 28 is input to the input processing unit 32 via the system bus 29. Data input to the input processing unit 32 is stored in a buffer (memory) 32.
The data stored in the buffer 32a and the data stored in the buffer 32a are transferred to the signal processing unit 33 by a signal from the overall control unit 31.

The signal processing section 33 performs a predetermined process on the transferred data. When the processing of the transferred data is completed, the data subjected to the predetermined processing is output to the output processing unit 34 according to a signal from the overall control unit 33. The output processing unit 34 stores the processing data output from the signal processing unit 33 in a buffer (memory) 34a.

In such a state, the overall control unit 31
Is connected to the DMAC module 21 by the system bus 2
9 to output a DMAC request signal DREQO requesting data output.
When the MA acknowledge signal DACKO is supplied, the output processing unit 34 outputs data on which predetermined processing has been performed to the system bus 29. The data output to the system bus 29 is stored in the external memory 28.

[0022]

In an image processing apparatus provided with such an image processing module, when the number of pixels of the CCD and the display is small, the first image processing module 25 for taking in data from the CCD, or Although the display image processing module for transferring display data to the display has a higher priority for the system bus, the number of data processing is small, the use frequency of the system bus 29 is relatively low, and Can afford. Therefore, the second image processing module 26 having a lower priority than these image processing modules
In addition, in the third image processing module 27, there is no possibility that the waiting time until the data input using the system bus 29 or the waiting time until the data output becomes long in response to the DMA request. As a result, in the image processing module, there is no danger that data may be excessively or deficient due to an increase in the standby time and the data processing time may be increased.

Recently, the number of pixels of a CCD and a display has been reduced to about 3 million, and the number of data transferred from the CCD and the number of display data transferred to the display have increased. Frequency of use of system bus 29 by module (data transfer frequency)
Is high. As a result, the time during which data is transferred by the system bus 29 becomes longer, and the second and third image processing modules 26 and 27 having lower priorities are provided.
However, there is a problem that the opportunity to use the system bus 29 is reduced.

For example, in the second image processing module 26, even when a DMA request for requesting input / output of data to / from the system bus 29 is output, the system bus 29 is used by the image processing module having a higher priority. , The input / output of data to / from the second image processing module 26 is not performed, and the apparatus enters a standby state. As a result, the second image processing module 26 stays due to a shortage of input data or the processed data is not output even though the signal processing can be performed at a high speed. Therefore, the signal processing speed may be reduced, or invalid data may be processed. Then, if such a state continues, an abnormality may occur in the processed data.

A similar problem also occurs in the third image processing module 27 that performs JPEG compression processing of data for communication of image data or storage in an external memory.

Even when the number of pixels of the CCD and the display is not large, the second, third or second image processing is performed simultaneously with the fetching of the data from the CCD, that is, while fetching the data from the CCD. Module 26
Or 27, when performing data processing,
When the data processing speed of the second or third image processing module 26 or 27 becomes higher than the data capture speed of the data transferred from the CCD, the data to be processed is originally stored in the second or third image processing module 26. Before the image data is input to the second or third image processing module, the image processing operation by the second or third image processing module 26 or 27 starts. As a result, an abnormality may occur in the data processed by the second or third image processing module 26 or 27.

In order to prevent the occurrence of such an abnormality,
Usually, the contention control unit (arbiter) 22 of the image processing apparatus
In response to a DMA request from the second or third image processing module 26 or 27, the second or third image processing module 26 or 27 performs control so that use permission of the system bus 29 is not given.
Of the image processing module 26 or 27 is stopped in a data input standby state. in this way,
Second or third image processing module 26 or 27
Is stopped in the data input standby state, the second or third image processing module 26 or 2 is controlled by the CPU & if 23 in order to reduce power consumption.
7 is stopped.

However, as described above, the CPU & if
When the supply of the clock to the second or third image processing module 26 or 27 is stopped by the control of 23,
When the processing by the second or third image processing module 26 or 27 is started, the control signal from the CPU CPU & if 23 is transmitted via the frequently used system bus 29 to the second or third image processing module 26 or 2.
Therefore, it takes a long time until the second or third image processing module 26 or 27 can be processed.

Further, in this case, after the processing by the second or third image processing module 26 or 27 is resumed, the second or third image processing module 26 or 27 generates a DMA request and Since it takes a long time before the second image processing module 29 can be used, it takes a very long time before the actual processing is performed by the second or third image processing module 26 or 27. Further, as described above, it takes a long time until the actual processing is performed, so that the power consumption also increases.

An object of the present invention is to solve such a problem, and an object of the present invention is to prevent an abnormality or the like from occurring in data to be processed in an image processing module having a low priority when using a system bus. It is an object of the present invention to provide an image processing apparatus capable of preventing the power consumption and reducing power consumption.

[0031]

An image processing module according to the present invention executes predetermined processing on data in units of one block, with pixel data of each area obtained by dividing a screen into a plurality of blocks as one block. A signal processing unit; input-side DMA request control means for generating a DMA (Direct Memory Access) request for inputting data of one block to be processed via a system bus; Output side DMA request control means for generating a DMA request for requesting data output, an input processing unit for receiving one block of data via a system bus and transferring the input data to a signal processing unit;
An output processing unit to which data processed by the signal processing unit is transferred and output to the system bus, wherein when the signal processing in the signal processing unit is completed, the input-side DMA request control means Alternatively, when a DMA request is issued from the output side DMA request control means, the signal processing by the signal processing unit is stopped.

A clock control unit for controlling the supply of a clock signal to the signal processing unit is provided. When the signal processing in the signal processing unit is stopped, the supply of the clock signal from the clock control unit is stopped. The signal processing unit is brought into an operation stop state.

A clock control unit for controlling the supply of the clock signal to the signal processing unit is provided. When the signal processing in the signal processing unit is stopped, the supply of the clock signal from the clock control unit is stopped. .

The output processing section outputs a plurality of blocks collectively.

The image processing apparatus of the present invention generates a DMA request for requesting data input / output via a system bus,
By permitting use of the system bus, data input / output to / from the system bus is performed, a plurality of image modules for performing signal processing on the input data, and a DMA request from each image processing module.
A DMAC module for determining which image processing module is permitted to use the system bus, wherein at least one of the image processing modules is the image processing module according to claim 1. .

Data subjected to signal processing in the image module is image data output from the solid-state imaging device.

[0037]

Embodiments of the present invention will be described below with reference to the drawings.

The image processing apparatus according to the present invention is different from the image processing apparatus shown in FIG.
The configurations are the same except that only the configurations of 6 and 27 are different. The configurations other than the second and third image processing modules 26 and 27 are described in detail by using the reference numerals shown in FIG. Is omitted.

FIG. 1 is a block diagram showing the configuration of the image processing module of the present invention used as the second and third image processing modules in the image processing apparatus of the present invention. This image processing module performs data processing in units of blocks, and inputs and outputs data to and from the system bus 29 in units of blocks.

The image processing module includes a system bus 29
Processing unit 1 to which data in block units is input from
5, the block unit data input to the input processing unit 15 is transferred, the signal processing unit 16 for performing predetermined processing, and the block unit data processed by the signal processing unit 16 are transferred. , An output processing unit 17 for outputting to the system bus 29, and an overall control unit 18 for controlling the signal processing unit 16 and the like.

The overall control unit 18 receives an input-side DMA request control unit 11 for generating a DMA request for requesting data input via the system bus 29 and a DMA request for requesting data output via the system bus 29. Generated output D
It has an MA request control unit 13 and a signal processing control unit 12 that controls the signal control unit 16. The signal processing control unit 12 is provided with a block processing end detection unit 12a for detecting that data is processed in block units by the signal processing unit 16 and the processing is completed.
Is provided with a block number counting unit 12b for counting the number of blocks processed in.

The block processing end detection section 12a has a preset time required for processing the data in block units in the signal processing section 16, and the input processing section 15 sends the data in block units to the signal processing section 16 from the input processing section 15. When a predetermined time elapses after the transfer, it is detected that the signal processing unit 16 has processed the data in block units.

The input side DMA request control section 11 of the overall control section 18 outputs a DMA request signal (DMA
REQI) is generated, output to the DMAC module 21, and output to the signal processing control unit 12 of the overall control unit 18. Further, the DMA acknowledge signal DACKI from the DMAC module 21 is input to the input-side DMA request control unit 11.
The MA acknowledge signal DAKI is also input to the input processing unit 15.

The output side DMA request control section 13 generates a DMA request signal (DMAREQO) for requesting data output, outputs the generated DMA request signal to the DMAC module 21, and outputs the signal to the signal processing control section 12 of the overall control section 18. I do.
Further, the DMA acknowledge signal DACKO from the DMAC module 21 is input to the output side DMA request control unit 13, and the DMA acknowledge signal DACKO is also input to the input processing unit 15.

The input processing unit 15 includes the DMAC module 2
When the DMA acknowledge signal DACKI from 1 is input, data is input in block units from the system bus 29 and stored in the buffer (memory) 15a. Then, the data stored in the buffer 15a is transferred to the signal processing unit 16.

The signal processing unit 16 performs predetermined processing on the transferred data in block units, and then outputs the processed data to the output processing unit 17. Output processing unit 1
Reference numeral 7 stores the processed data output from the signal processing unit 16 in a buffer (memory) 17a, and outputs the processed data to the system bus 29 by receiving the DMA acknowledge signal DACKO from the DMAC module 21.

The overall control section 18 is provided with a clock control section 14 for supplying a clock signal to the signal processing section 16 to make the signal control section 16 operable. The clock control unit 14 is controlled by the signal processing control unit 12, and when the input processing unit 15 and the output processing unit 17 input and output data in block units, the processing is prioritized. In order to cause the signal processing unit 14 to stop supplying the clock signal to the signal processing unit 14, the operation of the signal processing unit 14 is stopped.

A case will be described below in which the image processing module having such a configuration performs a filter process for compressing an image by interpolation rather than by thinning. This filtering process interpolates not only data such as the luminance of the pixel to be processed, but also data obtained by multiplying the data of the surrounding pixels by a predetermined coefficient so that the image quality is not significantly degraded by the compression process. I do. Therefore, it is necessary to take in data including not only pixels to be processed but also peripheral pixels. For this purpose, data of all pixels in a rectangular small area (block) obtained by dividing the entire screen into a plurality of blocks is input to the image processing module in block units, and the signal processing unit 16 also inputs the data in block units. After the image data is processed, data in block units is output.

Here, 19 in the horizontal direction on the screen
A 19 × 19 pixel constituted by pixels (horizontal lines) and 19 pixels in the vertical direction (vertical lines) is subjected to compression conversion to compress the number of pixels into 8 × 8 pixels, which are 8 pixels in the horizontal direction and 8 pixels in the vertical direction. The case will be described. In this case, the signal processing unit processes the output 1-pixel data, with 19 × 19 pixels as the processing target pixels. For this purpose, a 19 ×
The signal processing is performed while sequentially changing the 19 pixels to be processed so as to obtain data corresponding to the output 8 × 8 pixels. Therefore, in the signal processing unit 16, 8
× 8 = 64 signal processes are performed.

In order to execute predetermined signal processing in the signal processing section 16, 32 (horizontal line) × 19 (vertical line) pixels are assigned to one screen as shown in FIG.
Divided as a block, 3
The data of 2 × 19 pixels is the D from the image processing module.
MA requests are sequentially input to the image processing modules via the system bus 29. In this case, the data of one block I1 located at the uppermost position on the leftmost side of the screen is first transferred to the image processing module, and then,
Block I adjacent to the right side of the block I1 in the horizontal direction
2 is transferred to the image processing module. Hereinafter, the data of the block adjacent to the right side in the horizontal direction is sequentially transferred to the image processing module.

In each block, 32 pixels on the uppermost horizontal line are transferred in order from left to right, and when the transfer of the data of the uppermost 32 pixels is completed, the block is adjacent to the lower side of the horizontal line. Data of 32 pixels on the horizontal line are sequentially transferred from left to right. Similarly, the data is sequentially transferred over the 19 lines in the vertical direction, thereby completing the data transfer of all the pixels in one block.

When the transfer of all data in one row of blocks arranged in the horizontal direction is completed, the data of each block along the horizontal direction adjacent to the lower side of the row is sequentially transferred from the left to the image processing module. Is done.

In this case, pixel data of 11 horizontal lines arranged vertically below the uppermost block to which the data has been transferred are read in duplicate. That is,
In the second line block from the upper side, data of 19 lines of pixels is transferred vertically from the ninth horizontal line located 8 lines below the pixels of the uppermost horizontal line. Thereafter, similarly, in a pair of blocks arranged in the vertical direction, pixel data of 11 lines arranged in the vertical direction is transferred in an overlapping manner, and the data of 11 lines transferred in an overlapping manner is transmitted. Is used to maintain continuity during image processing.

As described above, the input processing unit 15 of the image processing module receives the data of one block unit of 32 × 19 pixels in order, and outputs the data to the buffer 15 of the input processing unit 15.
In a, data of 32 × 19 pixels per block is stored. Thereafter, data of 32 × 19 pixels per block stored in the buffer 15 a of the input processing unit 15 is transferred to the signal processing unit 16.

The buffer 1 in the input processing unit 15
The capacity of 5a is determined in consideration of the processing speed, the frequency of use of the system bus 29, the area of the LSI chip, etc., but data (32 × 19 ×) transferred by three DMA requests.
It suffices if there is enough capacity to store data corresponding to three pixels). Normally, since data corresponding to two blocks (32 × 19 × 2 pixels) can be stored, it can function as a buffer capable of continuously outputting data in block units.

The signal processing section 16 performs pixel number reduction processing including interpolation processing and the like from 32 × 19 pixel data, obtains one pixel data from 19 × 19 pixel data, and obtains 32 × 19 pixel data. Is compressed into data of 8 × 8 pixels. Then, the obtained data of 8 × 8 pixels is 1
It is in block units.

The data of one block of 8 × 8 pixels obtained by the signal processing unit 16 is transferred to the output processing unit 17.

The output processing unit 17 converts the data of 8 × 8 pixels transferred from one block into four blocks as one unit.
The data is stored in the buffer 17a in a state of being arranged in the horizontal direction. In this case, as shown in FIG. 3, in the buffer 17a of the output processing unit 17, data of 32 pixels corresponding to 4 blocks are sequentially stored from left to right in one horizontal line direction. When the data is stored in the horizontal direction, data of 32 pixels in the second horizontal line located one step below in the vertical direction is stored. Hereinafter, similarly,
Pixel data is stored along eight lines in the vertical direction, and 32 (8 × 4) × 8 pixels are stored as one unit.

In this manner, data of 8 × 8 pixels in one block are sequentially stored in the buffer 17a of the output processing unit 17 with four blocks as one unit.

FIG. 4 shows the relationship between the data size (19 × 19 pixels) processed by the signal processing unit 16 and the data size (8 × 8 pixels) obtained by the image compression processing. In the signal processing unit 16, the data of 19 × 19 pixels is subjected to compression processing to obtain data of 8 × 8 pixels, which are sequentially output to the output processing unit 14. The buffer 17a of the output processing unit 17 stores data of 8 × 8 pixels as one block and four blocks as one unit.

Since the image compression processing by interpolation is an existing technology, it will not be specifically described here, but will be described about data input / output control by the DMA request in the image processing module, control of the signal processing section 14, and the like. I do.

FIG. 5 is a flowchart showing a processing procedure when data is input to the input processing unit 14 in the image processing module, and FIG. 6 is a flowchart showing a subroutine in the input side DMA request control unit 11.

At the beginning of the image processing, the clock control unit 14 of the overall control unit 18 stops supplying the clock signal to the signal processing unit 16.
Is in an operation stopped state in which processing is not performed.
(See step S11 in FIG. 5, the same applies hereinafter).

When the image processing is started in such a state, the buffer (memory) 15a of the input processing unit 15 stores
Since no data has been input, in order to input data to the input processing unit 14, the input-side DMA request control unit 11 performs a subroutine A shown in FIG.

The input-side DMA request control unit 11 in the overall control unit 18 generates a data input request signal DREQI (see step S31 in FIG. 6, the same applies hereinafter) as shown in subroutine A in FIG. Input request signal D
The REQI is output to the DMAC module 21. Then, the DMAC module 21 sends a DMA request for recognizing the use of the system bus 29 to the image processing module.
The acknowledgment signal DACKI is input-side DMA request control unit 1
When given to the input processing unit 15 and the input processing unit 15, data of 32 × 19 pixels per block is transferred from the external memory 28 to the buffer (memory) 15 a of the input processing unit 15 under the control of the DMAC module 21.

As shown in step S31 of FIG. 6, when DREQI is generated from the input side DMA request control unit 11,
In the buffer 15a of the input processing unit 15, one block 32 ×
Until the data of 19 pixels is stored, the DMA request signal D
REQI is continuously generated (step S32). Then, when one block of data is transferred to the buffer 15a of the input processing unit 15, the generation of the DMA request signal DREQI in the input-side DMA request control unit 11 ends (step S33).

At the beginning of the signal processing, the input side DMA
First DMA request signal D issued from request controller 11
Even if data of one block of 32 × 19 pixels transferred from the external memory via the system bus 19 is stored in the buffer 15a of the input processing unit 15 by the REQI, the buffer 15a has a margin (space). FIG. 6
Is continuously performed, and data of 32 × 19 pixels in the next block are also stored in the buffer 15a continuously.

While the data is being input to the buffer 15a of the input processing unit 15, the supply of the clock signal from the clock control unit 14 of the overall control unit 18 to the signal processing unit 16 is continuously stopped. Therefore, the signal processing unit 16 continues the operation stop state.

Signal processing controller 1 in overall controller 18
2, the signal processing unit 16 extracts 19 × 19 pixels from the input data of 32 × 19 pixels in one block and compresses the data to make 32 × 19 pixels 8 × 8 pixels. A block processing end detection unit 12a having a preset time is provided, and the block processing end detection unit 12a starts measuring time when storage of one block of data is started. Then, when a preset time elapses (step S12), the input-side DMA request control unit 11 determines that the input of one block of data to the buffer of the input processing unit 15 has ended. It is checked whether the DMA request signal DREQI has been generated (step S13).

If the DMA request signal DREQI has been generated in step S13, it is determined that all data has not been completely input to the buffer 15a of the input processing unit 15, and the buffer 15a of the input processing unit 15 is determined. The input of data to is continued.

On the other hand, the DMA request signal DREQI
Is completed, the clock control unit 14 of the overall control unit 18 supplies the clock signal to the signal processing unit 16 to make the signal processing unit 16 operable.
Then, from the input processing unit 15 to the signal processing unit 16, 32 ×
One block of data of 19 pixels is transferred (step S14).

In such a state, the signal processing unit 16
Performs signal processing of 32 × 19 pixel data input from the input processing unit 15. The signal processing unit 16 sequentially selects eight pieces of 19 × 19 pixel data from the input 32 × 19 pixel data, compresses the selected 19 × 19 pixel data, and performs The pixel data is set (step S15).

In this way, when the data processing of the first block is completed, it is confirmed that the processing of the data of two blocks is not completed continuously (step S1).
6) The data of 32 × 19 pixels in the second block input to the buffer 15a of the input processing unit 15 is transferred to the signal processing unit 16, and the data is compressed. Then, the data of 8 × 8 pixels obtained by the processing of the signal processing unit 16 is transferred as one block to the buffer 17a of the output processing unit 17 (Step S1).
5).

At the beginning of the signal processing, there is no data processed by the signal processing unit 16.
The buffer 17a of the output processing unit 17 has an external memory 28
, There is no data to output, and thus the signal processing unit 16 can continuously process two blocks of data.

In this way, the signal processing unit 16
When the data processing of the block is performed, the input processing unit 15
The buffer 15a of the input processing unit 15 checks whether there is a margin (space) for storing data of 32 × 19 pixels per block (step S19).
If there is a margin for storing one block of data, the subroutine A shown in FIG. 6 is executed, and one block of data is stored in the buffer 15a of the input processing unit 15 (step S17).

Thereafter, it is checked whether or not the DMA request signal DREQI has been generated from the input side DMA request control section 11 (step S18). If the DMA request signal DREQI has been generated from the input side DMA request control section 11, it is determined. ,
From the clock control unit 14 of the overall control unit 18 to the signal processing unit 1
6, the supply of the clock to the signal processing unit 16 is stopped.
Is set to a state in which signal processing is not performed (step S
19).

DMA from input side DMA request control unit 11
When the request signal DREQI is generated, the DMAC
It is determined that the device is waiting for an acknowledge signal from the module 21, and all data of 32 × 15 pixels in one block is transferred to the buffer 15 a of the input processing unit 15.
Until the generation of the DMA request signal DREQI ends, the generation of the clock from the clock control unit 16 is stopped, and the operation of the signal processing unit 16 is stopped.

In response to the acknowledge signal from the DMAC module 21, 1 is stored in the buffer 15 a of the input processing unit 15.
When the generation of the DMA request signal DREQI ends due to the input of the data of the block, it is checked whether the DMA request signal DREQO has been generated from the output side DMA request control unit 13 (step S20). Output side DM
When the DMA request signal DREQO has been generated from the A request control unit 13, it waits until the generation of the DMA request signal DREQO is completed, and confirms that the DMA request signal DREQO has not been generated. The clock control unit 14 of the overall control unit 18 supplies the clock signal to the signal processing unit 16 so that the signal processing unit 16 can perform signal processing. Then, one block of data of 32 × 19 pixels is transferred from the input processing unit 15 to the signal processing unit 16 (step S21).

Thereafter, as described above, the signal processing section 16 compresses the data of 32 × 19 pixels input from the input processing section 15 and outputs the processed data of 8 × 8 pixels to the output processing section 17. (Step S22).

As described above, the signal processing unit 16
When the processing of the pixel data of the block is completed, it is confirmed whether or not the data processing of all the blocks on the screen has been completed (step S23). S2
Step 2 is repeated.

FIG. 7 is a flowchart for explaining the operation when the processing data is output from the output processing unit 17. When the processing by the output processing unit 17 is started, the supply of the clock signal to the signal processing unit 16 is stopped, and the signal processing unit 16 is in an operation stopped state in which the processing is not performed. Also, a block number counting unit 1
2b is reset, and the count number is set to 0 (see step S40 in FIG. 7, the same applies hereinafter).

In the output processing unit 17, since the DMA request signal DREQO is not generated from the output side DMA request control unit 13, the signal processing unit 16 is in a signal processing permission state for one block of data. (Step S41 in FIG. 7), it is confirmed that the DMA request signal DREQI has not been generated from the input side DMA request control unit 11 (Step S42), and the data processing by the signal processing unit 16 is performed (Step S42). S43). The data processing by the signal processing unit 16 is the same as the signal processing in step S15 in the flowchart of FIG. 5. When the data processing is completed, the number of processing blocks of the block number counting unit provided in the signal processing control unit 12 is reduced. , +1. The data of one block of 8 × 8 pixels obtained by the signal processing unit 16 is stored in a buffer 17 of the output processing unit 17.
output to a.

When a DMA request signal DREQI is generated from the input side DMA request control unit 11, one block of data is input to the buffer 15a of the input processing unit 15, so that the signal processing unit 16 The clock signal is not supplied from the clock control unit 14, the operation is stopped, and the processing is not performed.
After one block of data input to 5a is completed,
When the clock signal is supplied to the signal processing unit 16, the signal processing unit is brought into a process executable state, and predetermined signal processing is performed.

As described above, the signal processing unit 16
When the processing of the pixel data of the block is completed, the block number counting unit 12b provided in the signal processing control unit 18 checks whether the number of blocks subjected to the signal processing by the signal processing unit 16 is four. (Step S44). If the signal processing unit 16 has not processed data of four blocks in succession, steps S41 to S43 are repeated.

On the other hand, in the signal processing unit 16,
When four blocks of data are processed in succession, the output side DMA request control unit 13 outputs the DMA request signal D
REQO is issued to request the DMAC module 21 to use the system bus 29. When inputting data to the input processing unit 14, the input-side DMA request control unit 11
Then, a subroutine A shown in FIG. 6 is performed. The output-side DMA request control unit 1 in the overall control unit 18 in this case.
In 3, the subroutine B shown in FIG. 8 is executed. The output side DMA request control unit 13 firstly outputs the data input request signal D
REQO is generated (see step S51 in FIG. 8, the same applies hereinafter), and the data input request signal DREQO is
Output to C module 21. Then, a DMA acknowledgment signal DA for recognizing the use of the system bus 29 for the image processing module from the DMAC module 21.
When CKO is given to the output-side DMA request control unit 13 and the output processing unit 17, four blocks of pixel data (8 × 4 ×) stored in the buffer (memory) 17 a of the output processing unit 17 are controlled by the DMAC module 21. 8 pixel data) is transferred to the external memory 28 via the system bus 29 at a time.

If the data of four blocks has not been processed successively in the signal processing section 16, the processing of steps S41 to S43 is performed.

When the control is performed by the output side DMA request control unit 13, the output side DMA request control unit 13
It is checked whether the A request signal DREQO has been generated (step S45). If the DMA request signal DREQO has been generated from the output side DMA request control unit 13, the clock processing unit 14 of the overall control unit 18 performs signal processing. Part 16
Is stopped, and the signal processing unit 16
Is set to a state in which signal processing is not performed (step S
46).

DMA from output side DMA request control unit 13
When the request signal DREQO is generated, the DMAC
It is determined that it is in a state of waiting for the acknowledge signal DACKO from the module 21, and the data of four blocks (8 × 4 × 8 pixels) stored in the buffer 17 a of the output processing unit 17 are collectively transferred to the system bus 29. Is output to the external memory 28 via the.

The data of the four blocks (8 × 4 × 8 pixels) stored in the buffer 17a of the output processing unit 17 are output to the external memory 28 via the system bus 29, so that the output side DMA request control unit When the generation of the DMA request signal DREQO from the H. 13 stops, it is checked whether or not the data processing of all the blocks on the screen has been completed (step S47). If the data processing of all the blocks has not been completed, step S41 is performed. Step S46 is repeated. If the data processing for all blocks has been completed, the control ends.

[0090]

As described above, the image processing module and the image processing apparatus of the present invention stop the signal processing by the signal processing unit when the DMA request is generated, and input / output data. Therefore, there is no possibility that the data may be excessive or insufficient at the time of signal processing by the signal processing unit, and there is no possibility that an abnormality or the like occurs in the processed data.

Further, the image processing module is provided with a clock control unit for supplying a clock signal to the signal processing unit, and when the signal processing is stopped, the operation of the signal processing unit is stopped. Power can be significantly reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of an image processing module according to the present invention.

FIG. 2 is an explanatory diagram of an input procedure of image data to be processed in the image processing module.

FIG. 3 is an explanatory diagram of an output procedure of image data to be processed in the image processing module.

FIG. 4 is an explanatory diagram of processing contents of image data in the image processing module.

FIG. 5 is a flowchart for explaining processing contents on a data input side in the image processing module.

FIG. 6 is a flowchart showing a subroutine in the processing.

FIG. 7 is a flowchart for explaining processing contents on a data output side in the image processing module.

FIG. 8 is a flowchart showing a subroutine in the processing.

FIG. 9 is a block diagram illustrating an example of a configuration of an image processing apparatus.

FIG. 10 is a block diagram illustrating a configuration of an image processing module used in the image processing apparatus.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 Input side DMA request control part 12 Signal processing control part 12a Block processing completion detection part 12b Block number counting part 13 Output side DMA request control part 14 Clock control part 15 Input processing part 15a Buffer 16 Signal processing part 17 Output processing part 17a Buffer DESCRIPTION OF SYMBOLS 21 DMAC module 22 Competition control part 23 CPU & if 24 External memory controller 25-27 Image processing module 28 External memory 29 System bus

Claims (5)

[Claims] 1. A signal processing unit for performing predetermined processing on data in units of one block, with pixel data of each area obtained by dividing a screen into a plurality of blocks, and processing via a system bus. Input side DMA request control means for generating a DMA (Direct Memory Access) request for inputting data of one block to be output, and an output for generating a DMA request for requesting output of data of a block processed via a system bus Side DMA request control means, one block of data input via the system bus, an input processing unit for transferring the input data to the signal processing unit, and data processed by the signal processing unit. And an output processing unit for outputting to the system bus. When the signal processing in the signal processing unit is completed,
An image processing module, wherein the signal processing by the signal processing unit is stopped when a DMA request is generated from the input side DMA request control unit or the output side DMA request control unit. 2. A clock control unit for controlling supply of a clock signal to the signal processing unit, wherein when the signal processing in the signal processing unit is stopped, the supply of the clock signal from the clock control unit is stopped. The image processing module according to claim 1, wherein the signal processing unit is stopped to operate. 3. The image processing module according to claim 1, wherein the output processing unit outputs a plurality of blocks collectively. 4. A DMA request for requesting data input / output via a system bus is issued, and when the use of the system bus is permitted, data input / output to / from the system bus is performed and the input data is A plurality of image modules for signal processing, and a DMAC module for determining which image processing module is permitted to use the system bus in response to a DMA request from each image processing module, An image processing apparatus, wherein at least one of the processing modules is the image processing module according to claim 1. 5. The image processing apparatus according to claim 4, wherein the data subjected to signal processing in the image module is image data output from a solid-state imaging device.