JP2002324097A - Design system and method for cmos operational amplifier - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a design system for CMOS operational amplifier capable of achieving automatically design of a circuit-component-level from a desired amplifier function. SOLUTION: In the system acquiring a design constant of a CMOS operational amplifier equivalent in AC to a circuit composed of each output node of cascade connected 2 stages amplifying-circuit is connected via a phase compensation capacitance, a means to input a DC gain a0 of operational amplifier, a unity gain frequency fT, a phase allowance ϕ, and an S/N α as characteristic parameters necessary to calculate and a calculation means to acquire design constants of each constituent component of the amplifier based on a predetermined algorism and optimize the constants based on the predetermined evaluation factors are comprised.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a design system and method for an operational amplifier, particularly an operational amplifier comprising a CMOS (complementary MOS transistor).
The present invention relates to a technique that is useful when applied to the design of a digitally embedded LSI (integrated circuit).

[0002]

2. Description of the Related Art In recent years, in order to realize a plurality of functions with a single-chip LSI, the necessity of an LSI in which an analog circuit and a digital circuit are mixed on the same chip has increased.
Significant developments have been seen in SI.

Conventionally, in the field of digital LSI, I
Logic circuits (also called macrocells) provided by device manufacturers, such as P-core modules and RAM modules, that have already been logically designed, and designs up to, for example, functional levels and logical levels are automatically expanded to gate-level and mask-pattern layout levels. By using a design support program or the like called a design tool, it is possible to relatively easily perform LSI design.

[0004]

However, in the field of analog / digital mixed LSIs, analog circuits satisfying desired performance are required at the element level because the degree of freedom in designing analog circuits is significantly greater than that of digital circuits. There is no convenient design tool that automatically expands to this point, and analog circuit design is a major barrier for designers of mixed analog / digital LSIs. In particular, these are remarkable in the design of an operational amplifier used for most analog circuits.

As a conventional design method of an analog circuit represented by an operational amplifier, for example, a numerical analysis and a simulation at a circuit element level are repeated while changing parameters of the circuit element to satisfy a desired performance. Most of the methods required a lot of experience and advanced design know-how.

At present, a communication L for performing wired and wireless transmissions
In control circuits for SI, home electric appliances, automobiles, etc., the demand for analog / digital hybrid LSIs has greatly increased, while analog circuit designers are significantly short of digital circuit designers. In the situation. Therefore, development of a design tool that facilitates the design of an analog circuit is desired.

An object of the present invention is to provide a CMOS operational amplifier design system for automatically designing a circuit element level based on required amplifier performance, and a softway including the design algorithm.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0009]

The outline of a typical invention among the inventions disclosed in the present application is as follows.

That is, a CMOS operational amplifier design system for obtaining a design constant of a CMOS operational amplifier which is equivalent to an AC operational amplifier with a circuit formed by connecting each output node of a cascade-connected two-stage amplifier circuit via a phase compensation capacitor. Then, as the characteristic parameters required for calculation, DC gain a ₀ of the operational amplifier, unity gain frequency fT, phase margin φ, S
Means for inputting the N ratio α, and power supply voltage VDD, N channel MOS and P
Threshold voltage Vth (n), Vth (p) of channel MOS, voltage −
Current gain ratio β ₀ (n), β ₀ (p), channel modulation parameters λ (n), λ (p), flicker noise coefficient k (n), k (p), unit gate capacitance Cox, unit diffusion capacitance Cd Means for inputting a unit gate-source capacitance Cgs and a unit gate-drain capacitance Cgd; means for setting an evaluation function representing a predetermined physical quantity (for example, occupied area or power consumption) of the CMOS operational amplifier; Parameters, device parameters,
And an algorithm derived from the following conditions 1 to 6,
And calculating means for obtaining a design constant of each component of the CMOS operational amplifier based on an algorithm for optimizing the design constant based on the evaluation function.

1. Phase compensation capacitance C _C = (C ₁・ C ₂・ tan (φ)
/ 2) ^(1/2) , C ₁ : output load capacitance of first stage amplifier circuit, C ₂ : output load capacitance of second stage amplifier circuit 2. The sensitivity of the phase compensation capacitor C _C to the total current I _total is the minimum, ∂I _total (C _C ) / ∂ (C _C ) = 0. Relation between the current Ids ₃ uni I tee gain frequency fT and the first-stage amplifier _{circuit, Ids 3 = πC C · fT} · VE, VE: the effective bias voltage 4. The gain a ₁ of the first stage amplifier and the gain of the second stage amplifier
a ₂ are _{equal, a 1 = a 2 = (} a 0) (1/2) 5. Conditional expression of the current ratio n of the current gm ₃ flowing through the first stage amplifier circuit and the current gm ₈ flowing through the second stage amplifier circuit, n = gm ₈ / gm ₃ = [(C ₁ C ₂ + C ₂ C _C + C _C C ₁ ) / C _C ² ] · tan (φ) Effective bias voltage VE ≤ 2 / ((a ₀ ) ^(1/2)・ λ (n //
p)), λ (n // p): λ (n // p) = λ (n / p) + λ (p / n), λ (n / p): channel modulation of n-channel MOS in the saturation region Parameter, λ (p / n): p-channel MOS channel modulation parameter in the saturation region

According to the operation algorithm of such means, the DC gain, the SN ratio, the unity gain frequency, and the phase margin, which are the specifications of the operational amplifier, are satisfied.
It is possible to automatically derive a design constant that optimizes the characteristics of the evaluation function (for example, power consumption and occupied area of the operational amplifier). Therefore, for example, a digital / analog mixed LSI
Can be improved in each stage.

Since the design algorithm automatically inputs the amplifier characteristics required for the LSI system and satisfies the characteristics, the design and simulation are performed based on the amplifier characteristics when performing the LSI system design and system simulation. Can be easily performed.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows an example of a design flow of an analog / digital mixed LSI to which a design tool (hereinafter, referred to as amplifier software IP) according to the present invention is applied.

The design flow of an analog / digital mixed LSI is not uniform due to its design concept.
1. High-level descriptions called macro models, behavior models, and function models (for example, “VHDL-AMS: IEEE Sta
ndard VHDL 1067.1 "," Verilog-AM
S "), 2. 2. Transfer function expansion of system by high-order description (including heuristic simplification description) Specific circuit description,
4. It is hierarchized into four design steps S1 to S4 by layout development (also called layout synthesis). The design verification is performed in such a manner as to reverse the flow of the design.

That is, as shown in the design flow of FIG. 1, the system designer specifies a system specification R1, an LSI specification R2 necessary for the system specification R1, a digital circuit logical specification R3 satisfying the system specification R1, and an analog circuit specification R4. I will decide. On the digital circuit side, the logic specification R3 is described in a high-level language, and logic synthesis S5 is performed using the digital circuit library 10 and a logic synthesis tool. Then, a specific circuit-level netlist NL1 is created by the hierarchical model design.

On the analog circuit side, after describing the analog specifications in a high-level language, the analog circuit library 11
Is used to perform a circuit synthesis S6 that expands to an analog circuit architecture level. In parallel with this, the size of the constituent MOS of the operational amplifier and the capacitance value of the phase compensation capacitance that are synthesized at the architecture level by the amplifier software IP12 according to the present invention are determined by the operational amplifier performance determined by the analog specification R4 and the device vendor. The calculation is performed based on the presented parameter R5 of the element. As a result, an element-level netlist NL2 including information such as the size of each element is obtained on the analog circuit side.

The layout of the mask pattern is developed from the analog and digital netlists NL1 and NL2.

After the layout has been developed, the individual blocks are extracted from the layout model so as to reverse the flow of the hierarchical design, and analog additional information such as the parasitic capacitance of the MOS and the actual information are added. An analog / digital mixed circuit simulation S7 is performed by designating a parameter variation range in consideration of a semiconductor manufacturing process and a use environment to verify whether the LSI specification is satisfied.

The parameters for which the fluctuation range is specified in the circuit simulation include parameters relating to the usage environment on the customer side, such as a power supply voltage range and an operating temperature range, and various device parameters based on semiconductor manufacturing variations.

When the operation check is completed, the parameters obtained by the amplifier software IP are preferably registered in a library of an analog circuit. The registered parameters include, for example, the transfer function constant of the operational amplifier, the amplifier circuit diagram, each design constant of the operational amplifier, the bias voltage and the allowable variation range.

Next, the amplifier software IP according to the present invention
The design procedure of the CMOS operational amplifier using the above will be described. FIG. 2 is a configuration diagram of a basic two-stage CMOS operational amplifier to be designed with the amplifier software IP, and FIG. 3 is a circuit diagram of an AC equivalent circuit of the CMOS operational amplifier.

In the amplifier software IP of this embodiment, FIG.
An operational amplifier having the circuit configuration shown in FIG. That is, the differential amplification stage including the MOS transistors M1 to M5 and the output stage including the MOS transistors M7 and M8 are cascaded, and the phase compensation capacitance Cc is provided between the output node of the differential amplification stage and the output node of the output stage. It is a two-stage CMOS operational amplifier connected.
Then, by inputting a predetermined characteristic parameter required by a system designer and a predetermined device parameter provided by a semiconductor vendor, and further selecting a predetermined evaluation function for optimizing a design constant of the amplifier, The above CMO
MOS transistors M1 to M5, M of S operational amplifier
7, the gate length and gate width of M8, and the capacitance value of the phase compensation capacitance Cc are automatically calculated.

Such amplifier software IP is, for example,
It is configured by causing a workstation or a personal computer to execute software having a design algorithm described later.

[0025] The system designer specifies the amplifier software IP
The predetermined characteristic parameter input from a keyboard or the like of a computer equipped with is a DC gain a ₀ of an operational amplifier.
(dB), unity gain frequency fT (MHz), phase margin φ (de
gree), input signal amplitude Vin (V), SN ratio α (dB), signal frequency band B (kHz), and output load capacitance Cout (pF).

In the LSI design flow shown in FIG. 1, these characteristic parameters are generally determined by a system designer in the course of proceeding with circuit synthesis from analog specifications, but when these parameters are unknown. In, parameters are determined by joint work of a system designer and a circuit designer. At this time, it is also preferable to determine the use environment parameters required for the circuit operation verification of the circuit simulation, such as the operating temperature and the variation width of the power supply voltage. Furthermore, if there is a system specification to be targeted (for example, power consumption), it is better to clarify them.

The device parameters provided by the semiconductor vendor include power supply voltage VDD, threshold voltages Vth (n) and Vth (p) of N-channel MOS and P-channel MOS, voltage-current gain ratio β ₀ (n), β ₀ (p), channel modulation parameter λ
(n), λ (p), flicker noise coefficients k (n), k (p), unit gate capacitance Cox, unit diffusion capacitance Cd, unit gate-source capacitance Cgs, and unit gate-drain capacitance Cgd.

The predetermined evaluation function is, for example, a CMOS
This is a function for evaluating the minimum chip occupied area of the operational amplifier, the minimum power consumption, and the like. One of several registered evaluation functions is selected.

Further, the circuit designer must use the minimum MO used in the operational amplifier to match the device model (eg, MOS noise model) used in the operational amplifier design.
The gate length of S is designated and registered in the amplifier software IP.

When the above-described parameter input and selection of the evaluation function are performed by the user, the amplifier software IP uses the design algorithm consisting of the following steps 1 to 9 to make each MOS transistor M1 constituting the operational amplifier of FIG. Calculate and output the gate size of .about.M5, M7, M8 and the capacitance value of the phase compensation capacitance.

Step 1: The gate length of the registered minimum MOS is set to _L1fix . Step 2: The maximum effective bias voltage VEmax is determined as follows. VEmax = 2 / ((a ₀ ) ^(1/2)・ λ (n // p)) where λ (n // p) = λ (n / p) + λ (p / n) λ (n / p) and λ (p / n) are the n-channel MO in the saturation region.
These are channel length modulation parameters of S and p channel MOS.

Step 3: The effective bias voltage before correction is
VE (m). Here, m is an integer index number that is incremented by one each time this step 3 is repeated. The initial effective bias voltage is VE (0) = VEmax.

Step 4: Check whether the input signal amplitude Vin satisfies the following condition. Vin ² > 10 ^{(α / 10)}・ 16kT / (3 ・ β ₀ (n / p) ・ η ・ VE)

Step 5: Output Capacities of Differential Stage and Output Stage
C ₁ (k), and C ₂ (k). Here, k is the index number that is incremented by one each time this step 5 is repeated. The initial output capacitance is C ₁ (0), C ₂ (0) = Cout.

Then, in step S5, the next 1
結果 3. 1. Differential stage current to achieve unity gain frequency fT
Ids ₃ (k), a relational expression of the ratio η (k) (= W ₃ / L ₃ ) between the gate width W ₃ and the gate length L ₃ of the MOS transistor M3. Ids ₃ (k) = πC _C (k) · fT · VE, η (k) = W ₃ / L ₃ = Ids ₃ / [(1/2) · β ₀ (n / p) · VE ² · (1 +
λ (n / p) Vds ₃ )] From the SN ratio α, the MOS transistors M1 to M in the differential stage
An expression in which the gate length and gate width of No. 5 are expressed using Ids ₃ (k), η (k), and current distribution ratio n (k). These equations are
Is obtained by calculation based on the noise model. (Detailed in the theoretical explanation) Equation for expressing the phase compensation capacitance C _C (k) and the current distribution ratio n (k) using the phase compensation capacitance C _C (k) before correction and the phase margin φ. C _C (k) = (C ₁ (k) ・ C ₂ (k) ・ tan (φ) / 2) ^(1/2) , n (k) = [(C ₁ (k) C ₂ (k) + C ₂ (k) C _C (k) + C _C (k) C ₁ (k)) / (C _C
(k) ² )] ・ tan (φ)

Step 6: From the MOS size formula, all the MOS transistors M are divided into the following cases 1 to 3.
Gate lengths L1 to L5, L7, L of 1 to M5, M6, M7
8 and gate widths W1 to W5, W7, W8. First,
In any of the cases 1 to 3, the following expression holds. L _3fix = [(Kf (B _r ) / η) / (Vin ²・ 10 ^{(-α / 10)} -Kth (B) /
η)] ^(1/2) , W _3fix = η ・ L _3fix

1. Input MOS is N-channel type and β
Here the case of r (n / p)> 1 , βr (n / p) is the ratio of the beta ₀ and P-channel MOSbeta ₀ of N-channel MOS. L1 = L7 = L8 = _L1fix , L2 = L3 = _L3fix , L4 = L5 = (1 / βr (n / p)) · _L3fix , W1 = 2 ( _L1fix / _L3fix ) · _W3fix , W2 = W3 = W _3fix , W4 = W5 = W _3fix , W7 = n ・ (L _1fix / L _3fix ) ・ W _3fix , W8 = n ・ (L _1fix / L _3fix ) ・ βr (n / p) ・ W _3fix

2. Input MOS is P-channel type and β
If r (n / p) <1, L1 = L7 = L8 = _L1fix , L2 = L3 = _L3fix , L4 = L5 = _L3fix , W1 = 2 ( _L1fix / _L3fix ) · _W3fix , W2 = W3 = W _3fix , W4 = W5 = βr (n / p) ・ W _3fix , W7 = n ・ (L _1fix / L _3fix ) ・ W _3fix , W8 = n ・ (L _1fix / L _3fix ) ・ βr (n / p ) ・ W _3fix

3. The driving MOS M2 and M3 have negative noise
L1 = L7 = L8 = L when the noise is equal to the load MOS M4, M5 noise_1fix, L2 = L3 = L_3fix, L4 = L5 = [(K (p / n) / K (n / p)) / βr (n / p)]^(1/2)・ L_3fix, W1 = 2 (L_1fix / L_3fix) ・ W_3fix, W2 = W3 = W_3fix, W4 = W5 = [(K (p / n) / K (n / p)) · βr (n / p)]^(1/2)・
W_3fix, W7 = n ・ (L_1fix/ L_3fix) ・ W_3fix, W8 = n ・ (L_1fix/ L_3fix) ・ Βr (n / p) ・ W_3fix  Here, K (p / n) is a P-channel MOS or N-channel
This represents the flicker noise coefficient of the MOS.

Step 7: All MOS transistors M
From the sizes of 1 to M5, M7 and M8,
Output capacity C₁(k + 1), C_TwoFind (k + 1). Furthermore, phase margin
Phase compensation capacitance C corrected from φ_C(k + 1) and current distribution ratio n
(k + 1) is calculated as follows. C_C(k + 1) = (tan (Φ) ・ C₁(k + 1) ・ C_Two(k + 1) / 2)^(1/2), N (k + 1) = [(C₁(k + 1) C_Two(k + 1) + C_Two(k + 1) C_C(k + 1) + C_C(k + 1)
C₁(k + 1)) / (C_C(k + 1) ^Two )] × tan (φ)

Step 8: Corrected output capacitance C ₁ (k +
1), C ₂ (k + 1) is the output capacitance before correction C _j (k) (j = 1 to 2, k = 0
~ N), then check if C _j (k + 1)-C
_{If j} (k) = 0, the design up to this point is completed, and the process proceeds to the next step 9. Otherwise, return to step 4 with C _j (k + 1) as the newly defined output capacity, and repeat the procedure from step 4.

[0042] Step 9: The selected evaluation function, for example, by using an evaluation function P _{# 038} representing the power consumption of the entire operational _{amplifier, P amp (VE (m)} ) is equal to _{P amp (VE (m) -ΔVE} ) Check whether or not. Here, ΔVE is an arbitrary minute amount. If they are equal, it is determined that the power consumption is the minimum, and the design is completed. Otherwise, the newly defined effective bias is set to VE (m + 1) = VE (m) -ΔVE, and the process returns to step 3 and the procedure from step 3 is repeated.

According to the above steps 1 to 9, the amplifier software IP according to the present invention uses the design constant optimized to satisfy the input operational amplifier characteristics and to minimize the selected evaluation function. Lead out.

Since all the design constants must satisfy the following conditions 1 and 2, it is checked whether these conditions are satisfied. 1.0 ≤ VE ≤ VE _max = 2 / ((a ₀ ) ^(1/2)・ λ (n // p)) ≤
(1/4) VDD 2. Discriminant D of current quadratic equation (see theoretical explanation below)
Must be positive.

That is, (P _amp / VDD) ² > 8n · gm ₃ ² / (λ (p // n) ² · a ₀ ) ⇔n · gm ₃ ² <(P _amp / VDD) ² · (λ ( p // n) ²・ a ₀ ) / 8 As an evaluation function, the occupied area of the operational amplifier F (m) =
If the calculation in step 9 is performed using the evaluation function representing the MOS area + the phase compensation capacitance C _C area, the optimization that minimizes the occupied area can be performed.

In this design algorithm, the gate length L _1fix is used as a free design parameter.
_Applying the iterative algorithm above over a range of _{1fix allows} the CMOS operational amplifier to be optimized (minimized) with respect to power consumption.

Further, since the algorithm for obtaining a solution based on the AC analysis is used, the basic idea of this design algorithm can be applied to all amplifiers represented by the equivalent circuit shown in FIG. Thus, for example, FIG.
(B) of the two-stage inverter type shown in FIG. In this case, step 6 and step 7
May be rewritten into a formula corresponding to an inverter type amplifier.

Next, an example in which an amplifier design constant is actually obtained using the amplifier software IP will be described. FIG. 5 is a table showing amplifier design constants obtained by the amplifier software IP.

In this example, the targetness initially set
Functions, process parameters and evaluation functions are as follows:
It is. 1. Target performance: DC gain a₀ = 60 dB, unityge
In frequency fT = 10 MHz, output load capacitance Cout = 0.5 pF,
Phase margin φ = 60 degrees, input signal amplitude Vin = 0.5 V, S
NR = 100 dB, signal bandwidth B = 4 kHz 2. Process parameters: Power supply voltage VDD = 3 V, then
Threshold voltage Vth (n) = 0.3V, Vth (p) = 0.26V,
Current gain ratio β₀(n) = 170μA / V^Two, Β₀(p) = 60.8 μA / V^Two,
Output conductance λ (n) = 0.04 V^-1, Λ (p) = 0.06 V
^-1, Flicker noise coefficient k (n) = k (p) = 3.7 / 10^{-twenty four} F
V^Two, Unit gate capacitance C_ox = 4.32 fF / μm^Two  3. Evaluation function: Occupied area of operational amplifier

Based on these setting conditions, the above amplifier software
The following parameters and design constants are calculated using IP.
The number is obtained. 1. Fixed minimum gate length: L_1fix = 1.0 μm 2. Effective bias voltage: VE_max = 0.64 V3. Minimum gate area: Sg_Three ≒ 143 μm^Two  4. P-channel input type and N-channel shown in the chart of FIG.
Design constants for two types of operational amplifiers.

As a result of performing an analog simulation with the BSIM3 model of the 0.35 μm CMOS process on the operational amplifier constituted by the above design constants, the target performance previously set is obtained.

{Theoretical Description} Next, according to the above algorithm, the design constants of the basic operational amplifier having a two-stage configuration including the differential stage and the output stage are set to the DC gain, which is the specification of the operational amplifier,
It can be derived from characteristic parameters such as S / N ratio, unity gain frequency, and phase margin, and some specified design conditions. Furthermore, it is optimized for the evaluation function selected by taking the theoretical design limit Explain what you can do theoretically.

[Basic Theorem of Operational Amplifier Design] MOS model In order to design a CMOS operational amplifier, M
Use a better approximation of the current-voltage characteristic that matches the OS: [See Document 1: PAUL R, GRAY and ROBERT G.
MEYER, “Analysis and Design of Analog Integrate
d Circuits Third Edition, ”John Wiley & Sons, In
. c 1993] Ids = (1/2 ) · β 0 · (W / L) · (Vgs - Vth) 2 · (1 + λVds) (1) Here, the small signal current gain beta ₀ is the following equation, beta ₀ = μ ₀ · ε _ox / t _ox , β ₀ (p) ≒ (1/2) · β ₀ (n). Here, μ ₀ is the mobility of electrons or holes, ε _ox is the dielectric constant of the gate oxide film, t _ox is the thickness of the gate oxide film, Vgs is the bias voltage, and Vth is the threshold voltage.

The effective bias voltage VE is obtained from the MOS bias voltage. VE = Vgs-Vth (2) Here, Vgs is the gate-source voltage of the MOS, and Vth is the threshold voltage of the P-channel and N-channel MOS. Therefore, the drain-source current Id can be expressed as follows. Ids = (1/2) ・ β ₀・ (W / L) ・ VE ²・ (1 + λVds) (3)

Normally, the characteristics of the operational amplifier are expressed as follows using the mutual conductance gm of the small signal and the small signal output conductance gds. [See Reference 2: PAUL R, GRAY and ROBERT G. MEYER, “MOS Opera
national Amplifier Design-A Tutorial Overview, ”
IEEE Journal of Solid-State, Vol.SC-17, No. 6 D
ec 1982] gm = ∂Ids / ∂Vgs = β ₀・ (W / L) ・ (Vgs-Vth) ・ (1 + λVds) = β ₀・ (W / L) ・ VE ・ (1 + λVds) = 2Ids / VE (4) gds = ∂Ids / ∂Vds = (1/2) β ₀・ (W / L) ・ VE ²・ λ = (1/2) ・ gm ・ VE ・ λ = λIds (5) If λVds If << 1, Ids is often approximated as Ids = (1/2) ・ β ₀・ (W / L) ・ VE ² (6) gm = ∂Ids / ∂Vgs = β ₀・ (W / L) ・ VE (7) Therefore, Ids = (1 / 2) gmVE (8)

B. Operational Amplifier Characteristics The transfer function of the operational amplifier of FIG. 2 is expressed as follows.
[See Document 1] H (s) = a ₀ / [(s / ω ₁ +1) (s / ω ₂ +1) (s / ω ₃ +1)] (9) where ω ₁ , ω ₂ , ω ₃ is the angular frequency of the pole, s is the angular frequency of the imaginary. The design formula is derived by comparing the coefficient of equation (9) with the count of the equivalent circuit using the equivalent circuit of the operational amplifier. [See Document 2] dc gain a ₀ : a ₀ = gm ₃ gm ₈ R ₁ R ₂ (10) The angular frequency ω ₂ of the _second pole is ω ₂ = gm ₈ C _C / (C ₁ C ₂ + C ₂ C _C + C _C C ₁ ) ≒ gm ₈ / C ₂ (12) The angular frequency ω ₃ of the _third pole is represented by ω ₃ = 1 / (R _z C ₁ ) (13). Here, gm ₃ and gm ₈ are MOS M
3, and the conductance of the MOS M8, C _1, C ₂ and C _C are differential output stage, the output stage, and a phase compensation stage, a respective capacitance.

The main characteristics of the operational amplifier are shown as follows. [References 1,2] unity gain frequency _{fT: fT = a 0 ω 1} / (2π) = gm 3 / (2πC C) (15) slew rate SR: SR = 2πfsmax · Vin = Ids 1 / C C = gm ₃ VE / C _C = 2π · fT · VE (16) where fsmax is the maximum signal frequency, Vin is the input signal amplitude, and Ids ₁ is the source current of the differential stage.

Phase margin φ: tan (φ) = ω ₂ / (2πfT) = f ₂ / fT = (gm ₈ / C ₂ ) / (gm ₃ / C _C ) (17) From the condition of the minimum offset voltage of the system , These 5
It can be assumed that it is equal to the current density of two MOS Mi (i = 1, 4, 5, 7, 8). [See Literatures 1 and 2] (W ₄ / L ₄ ) / (W ₈ / L ₈ ) = (W ₅ / L ₅ ) / (W ₈ / L ₈ ) = (1/2) (W ₁ / L ₁ ) / (W ₇ / L ₇ ) = γ (18) where Wi and Li are the gate width and gate length of the MOS transistor Mi.

The following three steps are required to determine design conditions and design conditions. That is, DC analysis, mixed analysis using a quadratic equation of current, and small signal analysis.

[DC Analysis] Current Flow of Operational Amplifier To determine the current flow of the CMOS operational amplifier shown in FIG. 2, first, DC analysis is used. Branch current Ids
_i is a MOS Mi (i = 1, 2, 3, 4, 5, 7,
8). Since the gate input impedance of the MOS is infinite, no current flows between the differential stage and the output stage (see FIG. 2). The differential stage is symmetric on the positive phase side and the negative phase side. Therefore Kirchhoff's current law gives the following current equation: Differential stage: Ids ₁ = Ids ₂ + Ids ₃ , Ids ₂ = Ids ₄ , Ids ₃ = Ids ₅ , Ids ₂ = Ids ₃ (19) Output stage: Ids ₇ = Ids ₈ (20)

Assume that the current densities of all MOS channels are equal. Under this condition, all MOS
Obtains a model that forms a current flowing through a resistive network and a constant resistive surface. This model gives design conditions for a source-drain voltage and an effective bias voltage in the following CMOS operational amplifier. Then, the voltage equation can be written by the operational amplifier as follows. _{Vds 1 + Vds 2 + Vds 4} = Vds 1 + Vds 3 + Vds 5 = Vds 7 + V
ds ₈ = VDD, Vds ₄ = Vds ₅ = VE ₄ = VE ₅ = VE ₈ , VE ₁ = VE ₇

As described above, VE ₅ can be derived as follows using Ids ₁ = 2 · Ids ₅ and VE ₁ using the above voltage equation. VE ₅ = (βr (n / p) (W ₁ / L ₁ ) / (2 (W ₅ / L ₅ )) ^(1/2) VE ₁ (21) where βr (n / p) is N It is defined by the ratio of β _{0 of the} channel MOS and β ₀ of the P channel MOS as follows: An operational amplifier having an N channel input MOS, and βr (n)
= β _0n / β _0p ≒ 2 An operational amplifier having a P-channel input MOS, and βr (p)
= β _0p / β _0n ≒ 1/2 Using the minimum offset condition of the system, and transforming equation (21), VE ₅ = (βr (n / p) (W ₇ / L ₇ ) / (W ₈ / L ₈ )) ^(1/2)・ VE ₁ (22) If (βr (n / p) (W ₇ / L ₇ ) / (W ₈ / L ₈ )) ^(1/2) = 1, then β ₀ (n / p) (W ₇ / L ₇ ) = β ₀ (p / n) (W ₈ / L ₈ ) (23), and under the condition of Ids ₇ = Ids ₈ , β ₀ (n / p) (W ₇ / L ₇ )
= β ₀ (p / n) (W ₈ / L ₈ ). That is, gm ₇ = gm ₈ and VE ₅ = VE ₈ = VE ₁ . Hence, V
Assume E ₁ = VE ₄ = VE ₅ = VE ₇ = VE ₈ .

[0063] the rest of the problem, the effective bias voltage VE ₂ and VE ₃
Is the decision. In the system, the input voltage of the differential stage can be assumed to be AC ground. Therefore, MOS
The gate voltage Vg of Mj (j = 2, 3) is almost VD
D / 2. This condition is Vds ₁ + Vgs ₃ = (1/2)
Request VDD. Further, the MOS M1 must operate in the pinch-off region.

Therefore, the following design conditions are obtained. If VE ₃ = VE ₁ and VE ₁ = Vgs ₁ ≤ Vds ₁ , then VE ₁ ≤ (1/4) VDD (25) According to this conclusion, it can be assumed that VE ₁ = VE ₂ = VE ₃ . After designing a CMOS operational amplifier, the operation of the CMOS operational amplifier must be checked through the use of an analog simulator.

In order to obtain the design conditions, a current ratio n between half of the current of the differential stage and the current of the output stage is introduced. _{Ids 8 = n · Ids 3 (} 26) Thus, by using the equation (26) the equivalent of the effective bias voltage, as follows, can be derived a relationship of the mutual conductance gm ₃ and gm ₈ of small signal. gm ₈ = n · gm ₃ (27) The total current I _total of the CMOS operational amplifier is expressed by the following equation. I _total = Ids ₁ + Ids ₇ = Ids ₁ + Ids ₈ = (n + 2) Ids ₃ (28)

From the target performance of the unity gain frequency, Id
s ₃ , gm ₃ , η (= W3 / L3) are determined as follows. gm ₃ = 2πC _C・ fT, Ids ₃ = πC _C・ fT ・ VE ・ (1 + λ
(n / p) Vds _{3) Therefore, η = W 3 / L 3} = 2πC C · fT / [β 0 (n / p) · VE · (1 + λ (n / p) Vds 3)] (29 ) Ratio η is unity gain frequency fT, phase compensation capacity
C _C , effective bias voltage VE, source / drain bias voltage V _ds3 , and power supply voltage VDD, β ₀ (n / p), λ (n / p)
Can be defined using process parameters including

Therefore, it can be assumed that all effective bias voltages are equal under the design condition (25). All gate ratios W / L can be expressed using n, η, βr (n / p) as follows, and they are derived from the current equations (19), ( Two
0) and (18). (See Appendix _{A) W 1 / L 1 = 2W} 3 / L 3 = 2η, W 2 / L 2 = W 3 / L 3 = η, W 5 / L 5 = W 4 / L 4 = βr (n / p ) ・ W ₃ / L ₃ = βr (n / p) ・ η, W ₇ / L ₇ = n ・ η, W ₈ / L ₈ = βr (n / p) ・ W ₇ / L ₇ = n ・ βr ( n / p) · η (30) where βr (n / p) is β ₀ of NMOS and β
It is a ratio of ₀ . Therefore, the current ratio n is equal to the reciprocal of the ratio of the minimum offset condition of the system. n = 1 / γ (31)

B. Noise analysis, size design method for all gates obtained from noise conditions To simplify the design process, the algorithm is CM
A few parameters are used to determine all gate widths and lengths of OS op amps. Noise conditions and all gate widths and gate lengths are determined by the gate length L of the MOS M3.
3 and the gate width W3.

Assume the equivalent input noise of the operational amplifier as follows. [See Document 1] v _inN ² = v _inN (T) ² + v _inN (1 / f) ² = 4kT (2/3) (1 / gm ₃ ) [1 + (gm ₅ / gm ₃ ) ^{(1 / 2)] · B + [Kf} / (C ox · W 3 · L 3)] · ln (B r) (32) where, v _inN (T) is the thermal noise, v _inN (1 / f) is the flicker noise, k is the Boltzmann constant, T is the operating temperature, gm is the minimum transconductance of the input signal, B is the input signal bandwidth, the band ratio is the ratio between the minimum and maximum frequencies of the B _r Haga input signal, C _{o x} the capacity of the gate oxide film, Kf is equivalent flicker noise coefficients.

Kf = 2 · K (n / p) · [1+ (K (p / n) · μ (p / n) · L ₃ ² ) / (K (n / p) · μ (n / p ^{_{) · L 5 2)] (}} 33) where, K (p / n) If the input MOS is a P-channel, or a flicker noise coefficients for the n-channel.

Since Ids ₅ = Ids ₃ and VE ₅ = VE ₃ , gm
₅ = gm ₃ and gm ₃ = β ₀ (n / p) · (W ₃ / L ₃ ) · VE.
Therefore, equation (32) can be transformed as follows. v _inN ² = [{16kT / (3 · β ₀ (n / p) · VE)} · B] · (L ₃ / W ₃ ) + [(Kf / C _ox ) · ln (B _r )] / ( W ₃・ L ₃ ) = Kth (B) ・ (L ₃ / W ₃ ) + Kf (B _r ) / (W ₃・ L ₃ ) = Kth (B) / η + Kf (B _r ) / (η ・ ^{_{L 3 2) = [Kth (}} B) · Kf (B r)] (1/2) · (L 3 / L eq + L eq / L 3) (34) where, Kth (B) = [16kT / (3 · β ₀ (n / p) · VE)] · B, Kf (B _r ) = (Kf / C _ox ) · ln (B _r ), L _eq = [Kf (B _r ) / Kth (B) ] ^(1/2) (35)

By using the condition of the SN ratio, the SN ratio
The gate length L3 can be derived from αdB as follows.
Wear. Ten^{(α / 10)} ≤ Vin^Two/ [Kth (B) / η + Kf (B_r) / (η ・ L_Three ^Two)] ⇒ L_Three ≧ [(Kf (B_r) / η) / (Vin^Two·Ten^{(-α / 10)} -Kth (B) / η)]^(1/2) = L_3fix  W_3fix = η ・ L_3fix (36) where L_ThreeIs a positive value, the denominator in equation (36) is not positive
must not. Hence Vin^Two > 10^{(α / 10)}・ Kth (B) / η = 10^{(α / 10)}・ 16kT / (3 ・ β₀(n / p) ・ η ・ VE) (37) If L_3fixIs the required process measurement or
Applicable MOS gate length L_minIf smaller than
L_3fixTo L_minReplace with

Therefore, all the gate lengths and gate widths are obtained by the following equations (30) to (36). 1. The N-channel input type, βr (n / p)> 1 _{since, L 1 = L 7 = L} 8 = L 1fix, L 2 = L 3 = L 3fix, L 4 = L 5 = (1 / βr (n / p)) ・ L _3fix , W ₁ = 2 (L _1fix / L _3fix ) ・ W _3fix , W ₂ = W ₃ = W _3fix , W ₄ = W ₅ = W _3fix , W ₇ = n ・ (L _1fix / L _3fix ) ・ W _3fix , W ₈ = n ・ (L _1fix / L _3fix ) ・ βr (n / p) ・ W _3fix (38)

2. For P-channel input type, βr (n / p)
<So _{1, L 1 = L 7 =} L 8 = L 1fix, L 2 = L 3 = L 3fix, L 4 = L 5 = L 3fix, W 1 = 2 (L 1fix / L 3fix) · W 3fix, W ₂ = W ₃ = W _3fix , W ₄ = W ₅ = βr (n / p) · W _3fix , W ₇ = n · (L _1fix / L _3fix ) · W _3fix , W ₈ = n · (L _1fix / L _3fix ) ・ βr (n / p) ・ W _3fix (39)

3. If the noises of the driving MOSs M2 and M3 and the noises of the load MOSs M4 and M5 are to be designed to be equal, all gate lengths and gate widths are calculated using equations (30) and (36) as follows. be able to. L ₁ = L ₇ = L ₈ = L _1fix , L ₂ = L ₃ = L _3fix , L ₄ = L ₅ = [(K (p / n) / K (n / p)) / βr (n / p) ] ^(1/2)・ L _3fix , W ₁ = 2 (L _1fix / L _3fix ) ・ W _3fix , W ₂ = W ₃ = W _3fix , W ₄ = W ₅ = [(K (p / n) / K (n / p)) ・ βr (n / p)] ^(1/2)・ W _3fix , W ₇ = n ・ (L _1fix / L _3fix ) ・ W _3fix , W ₈ = n ・ (L _1fix / L _3fix ) ・_Βr (n / p) ・ W _3fix (40)

When the main noise is thermal noise, the equivalent input noise to the operational amplifier can be approximated as follows: v _inN ² = v _inN (T) ² = Kth (B) · (L ₃ / W ₃ ) = Kth (B) / η (41) By using the condition of the SN ratio, the gate ratio η satisfying the SN ratio αdB can be derived as follows. 10 ^{(α / 10)} = Vin ² η / Kth (B) ⇒ η = Kth (B) ・ 10 ^{(α / 10)}・ Vin ^(-2) (42) Since η is defined by equation (29), Assuming that equation (42) is equal to (29), Kth (B) · 10 ^{(α / 10)} · Vin ^(-2) = 2πC _C · fT / [β ₀ (n / p) · VE · (1 + λ ( n / p) Vds ₃ )] (43) Therefore, a phase compensation capacitance C _C can be obtained. C _C = [(16 kT / 3) · B · 10 ^{(α / 10)} · Vin ^(-2) ] / (2πfT) (44)

In the design algorithm of the CMOS operational amplifier, the phase compensation capacitance C _C is C _C = (C 1 · C 2 · tan (φ) / 2)
^(1/2) (see equation (53)). When the main noise is thermal noise, the relative MOS size ratio can be defined simply using equation (30). Therefore, it is necessary to change the noise model in equation (34). Alternatively, other design conditions are required.

Next, the design conditions for selecting a noise model of a two-stage amplification CMOS operational amplifier will be examined. When flicker noise becomes main noise, L ₃ / L _eq in equation (34) is L _eq /
Compared with the L ₃ is when the well can be ignored. If thermal noise is the main noise is when L _{e q} / L ₃ of formula (34) can be sufficiently neglected compared to L ₃ / L _eq. Therefore, design conditions for selecting a noise model can be derived from the bandwidth and band ratio of the input signal as follows. (See Appendix B)

1. If L _eq / L ₃ >> L ₃ / L _eq , then ln (B _r ) / (L ₃・ W ₃ ) ≦ 10 ^{(-α / 10)}・ Vin ² / (Kf / C _ox ) (45) At this time, flicker noise becomes main noise. 2. If _{L eq / L 3 ≒ L 3} / L eq, [ln (B r) · L 3 2] / B = [16kT / (3 · β 0 (n / p) · VE)] / (Kf / C _ox ) (46) At this time, flicker noise and thermal noise are almost equal. 3. If L _eq / L ₃ << L ₃ / L _eq , B ・ (L ₃ / W ₃ ) ≤ 10 ^{(-α / 10)}・ Vin ² / [16kT / (3 ・ β ₀ (n / p)・ VE)] (47) At this time, the thermal noise becomes the main noise.

Since the gate length L _1fix is fixed, the MOS M3
And current ratio n, all gate widths Wi and gate lengths L
i is the noise condition and the noise model equations (38), (3
9), and derived from (40). However, the phase compensation capacitance C _C
This formula is not enough to design a CMOS operational amplifier because is not defined.

C. Characteristics of the minimum sensitivity CMOS operational amplifier of the phase compensation capacitance C _C to the total current is used to determine the condition of the phase compensation capacitance C _C. By giving power consumption P _amp ,
The total current I _total (VE, C _C ) can be expressed as follows. Official Ids and unity gain frequency (8), (15) leads to current Ids ₁ of the differential stage. Ids ₁ = 2Ids ₃ = 2 ・ (1/2) gm ₃・ VE = 2πC _C・ fT ・ VE (50) The current Ids _{8 of the} output stage is obtained from the equation (12) of the second pole ω2 as follows: Desired. Ids ₇ = Ids ₈ = (1/2) gm ₈・ VE = πf ₂ [(C ₁ C ₂ + C ₂ C _C + C _C C ₁ ) / C _C ] ・ VE (51) Total current I _total (VE , C _C ) is therefore I _total (VE, C _C ) = Ids ₁ + Ids ₈ = πVE · fT · [2 C _C + tan (φ) (C ₁ C ₂ + C ₂ C _C + C _C C ₁ ) / C _C ] (52) where tan (φ) = f2 / fT (17)

The power consumption P _{amp of the} operational amplifier is proportional to the total current I _total (VE, C _C ) of the differential stage and the output stage. Differential stage current is proportional to the phase compensation capacitor C _C, the current of the output stage is inversely proportional to the phase compensation capacitance C _C. Op amp total current I _total (V
E, C _C ) is a downward convex function of the phase compensation capacitance C _C. Therefore, the minimum compensation phase compensation capacitance C _C for I _total (VE, C _C ) is as follows. When ∂I _total (VE, C _C ) / ∂ (C _C ) = 0, C _C ² = (1/2) tan (φ) · C ₁ C ₂ (53) From this result, the phase margin φ, The phase compensation capacitance can be obtained by using the output capacitance C ₁ of the differential stage and the output capacitance C ₂ of the output stage.
C _C is required.

[Integration of Typical Design Conditions (Secondary Equation of Current and Discriminant D Condition)] In the above description, all the gate widths and gates satisfying the noise condition and the minimum sensitivity condition of the phase compensation capacitance C _C are described. The design method leading to the length was derived. Since the effective bias voltage VE and the current distribution ratio are not defined, not all design parameters can be determined yet. Therefore, to find the effective bias voltage VE, a quadratic equation of the current must be introduced.

If the quadratic equation of Ids has solutions of Ids ₁ and Ids ₈ , the quadratic equation of Ids is as follows. (Ids-Ids ₁ ) ・ (Ids-Ids ₈ ) = Ids ^2- (Ids ₁ + Ids ₈ ) ・ Ids + Ids ₁・ Ids ₈ = 0 (54) Total current I _total is current of differential stage and output stage Can be defined by the power consumption P _amp . _{I total = Ids 1 + Ids 8} = P amp / VDD (55)

The product of the current of the differential stage and the current of the output stage is
DC gain a₀Obtained from DC gain is a₀ = gm_Threegm
₈R₁R_Two It is defined as (10). R₁And R_TwoIs the differential stage
And the output resistance of the output stage. MOS as current source
The parallel conductance of the active load MOS is
R₁And R_TwoIs included. 1 / R₁ = λ (n / p) Ids_Three + λ (p / n) Ids_Four, 1 / R2 = λ (n / p) I
ds₇ + λ (p / n) Ids₈  Where λ (n / p) and λ (p / n) are in the pinch-off region.
Channel modulation paths for N-channel and P-channel MOS
Parameters.

Therefore, 1 / R ₁ and 1 / R ₂ can be modified as follows by the current equation. 1 / R ₁ = (λ (n / p) + λ (p / n)) Ids ₃ = λ (n // p) Ids ₃ = (1/2) λ (n // p) Ids ₁ , 1 / R ₂ = (λ (n / p) + λ (p / n)) Ids ₈ = nλ (n // p) Ids ₃ = λ (n // p) Ids ₈ (56) where λ (n / p) + λ (p / n) = λ (n // p) (57)

From the equation of current, gm ₈ is calculated as gm ₈ = n · gm ₃
(27). By substituting (27) to (56) into the DC gain equation (10), the product of the current of the differential stage and the current of the output stage can be obtained. a ₀ = n gm ₃ ² R ₁ R ₂ = n ・ gm ₃ ² / [(1/2) λ (p // n) ² Ids ₁・ Ids ₈ ] ⇒ Ids ₁・ Ids ₈ = 2n ・ gm ₃ ² / (λ (p // n) ²・ a ₀ ) (58)

By substituting equations (55) and (58) into (54), the quadratic equation of Ids is as follows. Ids ^2- (P _amp / VDD) ・ Ids + 2n ・ gm ₃ ² / (λ (p // n) ²・ a ₀ ) = 0 (59) The quadratic equation of Ids is a quadratic equation for a CMOS operational amplifier. is there. The discriminant D is as follows: D = (P _amp / VDD) ² −8n · gm ₃ ² / (λ (p // n) ² · a ₀ ) (60) Since Ids ₁ and Ids ₈ are positive, The discriminant D must be positive. Therefore, the current distribution n and gm
It is possible to derive ₃ of the relationship in the following manner. (P _amp / VDD) ² > 8n ・ gm ₃ ² / (λ (p // n) ²・ a ₀ ) ⇔ n ・ gm ₃ ² <(P _amp / VDD) ²・ (λ (p // n) ²・ a ₀ ) / 8 (61)

Equation (26) defines the current ratio n of Ids ₈ and Ids ₃ . Therefore, the quadratic equation of the current is as follows. Ids ² − (n + 2) Ids3 · Ids + 2nIds ₃ ² = 0 (62) By comparing the coefficient of Equation (62) with the coefficient of Equation (59), the following relational expression is obtained. (n + 2) Ids ₃ = P _amp / VDD, (63) 2n ・ Ids ₃ ² = 2n ・ gm ₃ ² / (λ (n // p) ²・ a ₀ ) (64) In particular, equation (64) Derives the effective voltage. Ids ₃ = gm ₃ / (λ (n // p) ・ (a ₀ ) ^(1/2) ) ⇒ (1/2) gm ₃・ VE =
gm ₃ / (λ (n // p) · (a ₀ ) ^(1/2) ) Therefore, the following relationship is obtained. VE ≤ VE _max = 2 / ((a ₀ ) ^(1/2)・ λ (n // p)) ≤ (1/4) VDD (65)

[0090] The effective bias voltage VE is less than Vemax, and the target DC gain must be determined to be a _0. This effective bias voltage VE adjusts the gain of each stage so that the gain of the differential stage is equal to the gain of the output stage.
(a ₀ ) ^(1/2) .

Finally, using the remaining design problems, the current ratio n
If the current ratio n is found, the design algorithm of the CMOS operational amplifier can be optimized by the evaluation function using the characteristics to be achieved.

[Small Signal Analysis (Relationship Between Current Distribution Ratio and Phase Margin)] Using the unity gain frequency and the phase margin, the current ratio n is calculated as follows from the first and second poles (poles) in the frequency characteristic. Can be determined.

The first pole is defined as follows. ω ₁ = gm ₃ / (a ₀ C _C ) (11) The second pole is defined as follows. ω ₂ = gm ₈ C _C / (C ₁ C ₂ + C ₂ C _C + C _C C ₁ ) (12) By dividing equation (12) by equation (11), the current ratio n is as follows. n = gm ₈ / gm ₃ = [(C ₁ C ₂ + C ₂ C _C + C _C C ₁ ) / C _C ² ] · [ω ₂ / (a ₀ ω ₁ )] (66) Therefore, the phase margin Equation (17) gives: n = gm ₈ / gm ₃ = [(C ₁ C ₂ + C ₂ C _C + C _C C ₁ ) / C _C ² ] tan (φ) (67)

The initial current ratio depends on the initial output capacitance C ₁ and
It can be found from the C _2, and it is shown by Cout as follows. n = 2 · [1 + (2tan (φ)) ^(1/2) ] (68) where Cout is the output load capacity of the second stage, and C _C =
(tan (φ) / 2) The relationship of ^(1/2) · Cout is satisfied.

Accordingly, the design algorithm of the CMOS operational amplifier can be an iterative algorithm of the phase compensation capacitance that is optimized to achieve a predetermined performance with respect to power consumption.

[Theoretical Design Limit of Characteristics in Structure of CMOS Operational Amplifier] The effective bias voltage VE is expressed by the following equations (25) to (6).
Since given in 5), the range of the effective bias voltage can be assumed as follows. 0 ≤ VE ≤ VE _max = 2 / ((a ₀ ) ^(1/2)・ λ (n // p)) ≤ (1/4) VDD (69) Used to derive the theoretical limit of gain a ₀ . 10 ^{(α / 10)}・ 16kT / (3 ・ β ₀ (n / p) ・ η ・ VE _max ) <Vin ² (70) [2 / (λ (p // n) ・ VE _max )] ² ≦ a ₀ (71)

Bias voltage at unity gain frequency fT
By applying the range of VE, the unity gain frequency fT can be expressed as follows using the CMOS operational amplifier power consumption _Pamp and Expression (15). (Ids ₃ / VE _max ) / (π ・ C _C ) <fT (72) where Ids ₃ = (1 / (n + 2)) ・ (P _amp / VDD)

If there is no power consumption condition, a CMOS operational amplifier that satisfies the phase margin φ according to the formula (17) is possible. That is, a CMOS operational amplifier can be considered under the condition that the phase compensation capacitance is simply the gate-source capacitance C _{gs8 of the} MOS M8. In such a case, the unity gain frequency fT becomes the maximum unity gain frequency in the target phase margin. The phase compensation capacitance C _C , the capacitance C _{1 of} the differential stage, and the capacitance C ₂ of the output stage are cascaded with a plurality of operational amplifiers having a gain of 1 (see FIG. 4).
Is expressed as follows. The phase compensation capacitance C _C is C _C = C _gd8 (73)

[0099] The output capacitance C ₁ of the differential stage, there are two cases. C ₁ (M ₂ ) = C _d2 + (C _g4 + C _d4 + C _gs4 ) + (C _g5 + C _gs5 ) (74) or C ₁ (M ₃ ) = C _d3 + (C _d5 + C ' _gd5 ) + (C _g8 + C _gs8 ) ≒ C _d3 + (C _d5 + C _gd5 ) + (C _g8 + C _gs8 ) (75) The output capacitance C ₂ of the output stage is C ₂ = (C _d7 + C _gd7 ) + C _d8 + 2C _g3 (76)

Here, C₁(M_Two) Is the output capacitance of MOS M2
Quantity, C₁(M_Three) Is the output capacitance of MOS M3, C_djIs MOS
Mj drain capacitance, C_gjIs the gate capacitance of the MOS Mj,
C_gsjIs the gate-source capacitance of MOS Mj, C_gdjIs M
The gate-drain capacitance of OS Mj and C ′_gd5
Is defined as follows. C ’_gd5 = C_gd5・ [C_d2 + (C_g4 + C_d4 + C_gs4) + (C_g5 + C_gs5)] / {C_gd5 + [C_d2 + (C_g4 + C_d4 + C_gs4) + (C_g5 + C_gs5)]} ≒ C_gs5 (77) These capacitances C₁(M2), C₁(M3), and C_TwoIs as follows
Can be approximated. C_C/ W_Three = n ・ (L_1fix/ L_3fix) ・ Βr (n / p) ・ C_gd (78) C₁(M_Two) / W_Three= (1 + β'r (n / p)^(1/2)) ・ C_d + 2β'r (n / p)^(1/2)・ C_gd + 2C_g0・ L_{3fi x}  ≒ 2C_g0・ L_3fix (79) Here, β′r (n / p) is β in the case of the P-channel input type.
r (p), 1 / βr (n) for N-channel input type.

C ₁ (M ₃ ) / W ₃ = (1 + β′r (n / p) ^(1/2) ) · C _d + [β′r (n / p) + n · (L _1fix / L _3fix ) ・ βr (n / p)] ・ C _gd + n ・ (L _1fix / L _3fix ) ・ βr (n / p) ・ C _g0・ L _1fix ≒ n ・ (L _1fix / L _3fix ) ・ βr ( n / p) ・ C _g0・ L _1fix (80) C ₂ / W ₃ = n ・ (L _1fix / L _3fix ) ・ (1 + βr (n / p)) ・ C _d + n ・ (L _1fix / L _3fix ) ・ βr (n / p) ・ C _gd + 2C _g0・ L _3fix ≒ 2C _g0・ L _3fix (81) where C _d is unit drain capacitance (F / m), C _gd is unit gate-source capacitance (F / m), and C _g0 is unit Gate capacitance (F /
_m ^2), L 3fix the gate length of the differential stage, L _1fix is the gate length of the output stage.

Therefore, the ratios of the capacitances can be compared. C _C / C ₂ ≒ (n / 2) · (L _1fix / L _3fix ) · (1 / L _3fix ) · βr (n / p)・ (C _gd / C _g0 ) (82) C ₁ (M ₂ ) / C ₂ ≒ 1 (83) C ₁ (M ₃ ) / C ₂ ≒ C ₁ (M ₃ ) / C ₁ (M ₂ ) ≒ ( (n / 2) ・ (L _1fix / L _3fix ) ²・ βr (n / p) (84) _Compare the sum of the capacitance ratios for the P-channel input type with those for the N-channel input type. In the case of the input type, βr (n)> βr (p) than in the case of the N-channel input type
So it gets smaller. Therefore, in the limit where the phase compensation capacitance becomes 0, the P-channel input type operational amplifier is superior to the N-channel input type in high-speed performance.

Next, the phase compensation capacitance C_CIn the limit where
Then, the current distribution ratio n is found. C₁ (M_Two), Tan (φ) = nC_C ^Two/ (C₁C_Two + C_TwoC_C + C_CC₁) = n ・ [n ・ (L_1fix/ L_3fix) ・ Βr (n / p) ・ C_gd]^Two  / {L_3fix・ C_g0・ [2L_1fix・ C_g0 + (2 + n ・ (L_1fix/ L_3fix)^Two・ Βr (n / p)) ・ C_gd]} (8 5) C₁ (M_Three), Tan (φ) = nC_C ^Two/ (C₁C_Two + C_TwoC_C + C_CC₁) ≒ n ・ [n ・ (L_1fix/ L_3fix) ・ Βr (n / p) ・ C_gd]^Two  / {4L_3fix・ C_g0・ [L_3fix・ C_g0 + n ・ (L_1fix/ L_3fix) ・ Βr (n / p) ・ C_gd]} (86)

Since the cubic equation has at least one real solution, the cubic equations (85) and (86) for the current ratio n
Can be obtained. n = β ₀ (n / p) ・ (W ₃ / L _3fix ) ・ VE / [2πfT ・ (L _1fix / L _3fix ) ・ βr (n / p) ・ C _gd・ W ₃ ] (87) ) Gives the limit of the unity gain frequency fT in the basic CMOS operational amplifier structure. (See Appendix C)

[Appendix A: Formulation of Total Gate Size Based on Gate Ratio of MOS M3] It can be assumed that all effective bias voltages are equal under the design condition (25). Therefore,
All gate ratios W / L are n, η, and βr (n / p)
Can be indicated by These parameters can be derived from the current equations (19) and (20) and the equation (18) of the minimum offset condition as follows.

W ₁ / L ₁ = 2W ₃ / L ₃ = 2η, W ₂ / L ₂ = W ₃ / L ₃ = η, W ₅ / L ₅ = W ₄ / L ₄ = βr (n / p) · W ₃ / L ₃ = βr (n / p) ・ η, W ₇ / L ₇ = n ・ η, W ₈ / L ₈ = βr (n / p) ・ W ₇ / L ₇ = n ・ βr (n / p) · η (30) Here, βr (n / p) is the ratio of β ₀ of the N-channel MOS to β ₀ of the P-channel MOS. n = 1 / γ (31)

Next, a proof is given. In the CMOS operational amplifier shown in FIG. 2, the Kirchhoff current law gives the following relationship. In the differential stage, Ids ₁ = Ids ₂ + Ids ₃ , Ids ₂ = Ids ₄ , Ids ₃ =
_{Ids 5, Ids 2 = Ids 3} (19) output _{stage, Ids 7 = Ids 8 (20} ) Since it can be assumed that _{Ids 8 = n Ids 3 (26} ), the total current I _total, I _total = Ids ₁ + Ids ₇ = Ids ₁
+ Ids ₈ = (n + 2) Ids ₃ (28)

Further, the current equation is changed using Ids (1).
Shape. Ids_i = (1/2) ・ β₀(n / p) ・ (W_i/ L_i) ・ VE_i ^Two・ (1 + λVds_i) = (1/2) ・ β₀(n / p) ・ (W_i/ L_i) ・ VE_i ^Two   Here, assuming that i = 1, 2, 3, 4, 5, 7, 8₁ = VE_Two = VE_Three = VE_Four = VE_Five = VE₇ = VE₈ = Ids for the VE differential stage_Two = Ids_Four ⇒ β₀(n / p) ・ (W_Two/ L_Two) = β₀(p / n) ・ (W_Four/ L
_Four), Ids_Three = Ids_Five ⇒ β₀(n / p) ・ (W_Three/ L_Three) = β₀(p / n) ・ (W_Five/
L_Five), Ids_Two = Ids_Three ⇒ W_Two/ L_Two = W_Three/ L_Three = η, Ids_Two + Ids_Three = 2Ids_Three ⇒ W₁/ L₁ = (W_Two/ L_Two) + (W_Three/ L_Three) In the output stage, Ids₇ = Ids₈ ⇒ β₀(n / p) ・ (W₇/ L₇) = β₀(p / n) ・ (W₈/ L
₈), Ids₈ = n Ids_Three ⇒ β₀(p / n) ・ (W₈/ L₈) = nβ₀(n / p) ・ (W_Three/ L
_Three) = n ・ β₀(n / p) · η Therefore, W₁/ L₁ = 2W_Three/ L_Three = 2η, W_Two/ L_Two = W_Three/ L_Three = η, W_Five/ L_Five = W_Four/ L_Four = βr (n / p) ・ W_Three/ L_Three = βr (n / p) · η, W₇/ L₇ = n · η, W₈/ L₈ = βr (n / p) ・ W₇/ L₇ = n ・ βr (n / p) ・ η (30)

When the minimum offset condition of the system is applied to the equation (30), the following equation is obtained. (W ₄ / L ₄ ) / (W ₈ / L ₈ ) = (W ₅ / L ₅ ) / (W ₈ / L ₈ ) = [βr (n / p) · η] /
[n ・ βr (n / p) ・ η] = 1 / n = γ and (1/2) (W ₁ / L ₁ ) / (W ₇ / L ₇ ) = (1/2) (2η) / ( n ・ η) = 1 / n
= γ, so n = 1 / γ (31)

[Appendix B: Design Conditions of Noise Model] The criterion for selecting a noise model is derived from the maximum frequency and the minimum frequency of the signal bandwidth. 1. If L _eq / L ₃ >> L ₃ / L _eq , then ln (B _r ) / (L ₃ · W ₃ ) ≤ 10 ^{(-α / 10)} · Vin ² / (Kf / C _ox ) (45) At this time, flicker noise becomes main noise. 2. If L _eq / L ₃ ≒ L ₃ / L _eq , then [ln (B _r ) · L ₃ ² ] / B = [16kT / (3 · β ₀ (n / p) · VE)] / (Kf / C _ox ) (46) At this time, the flicker noise and the thermal noise are almost equal. 3. If L _eq / L ₃ << L ₃ / L _eq , B ・ (L ₃ / W ₃ ) ≤ 10 ^{(-α / 10)}・ Vin ² / [16kT / (3 ・ β ₀ (n / p)・ VE)] (47) At this time, the thermal noise becomes the main noise.

Next, a proof is given. 1. In the case of L _eq / L ₃ >> L ₃ / L _eq The equivalent input noise can be expressed as follows. v _inN ² ≒ [Kth (B) ・ Kf (B _r )] ^(1/2)・ (L _eq / L ₃ ) ・ (1 / W ₃ ) = Kf (B _r ) / (L ₃・ W ₃ ) (B-1) Therefore, Vin ² / V _inN ² ≧ 10 ^{(α / 10)} ⇒ Vin ² / [Kf (B _r ) / (L ₃・ W ₃ )] ≧ 10 ^{(α / 10)} (B− 2) Therefore, ln (B _r ) / (L ₃・ W ₃ ) ≤ 10 ^{(-α / 10)}・ Vin ² / (Kf / C _ox ) (45) At this time, flicker noise becomes main noise .

[0112] 2. L ₃ / L _eq >> L _eq / L ₃ The equivalent input noise can be expressed as follows. v _inN ² ≒ [Kth (B) ・ Kf (B _r )] ^(1/2)・ (L ₃ / L _eq ) ・ (1 / W ₃ ) = Kth (B) ・ (L ₃ / W ₃ ) ( B-3) Therefore, Vin ² / V _inN ² ≧ 10 ^{(α / 10)} ⇒ Vin ² / [Kth (B) ・ (L ₃ / W ₃ )] ≧ 10 ^{(α / 10)} (B-4) Therefore, B · (L ₃ / W ₃ ) ≦ 10 ^{(-α / 10)} · Vin ² / [16kT / (3 · β ₀ (n / p) · VE)] (47)・ It becomes noise.

3. When L ₃ / L _eq = L _eq / L ₃ The definition formula of L _eq is shown below. L _eq = [Kf (B _r ) / Kth (B)] ^(1/2) (35) Therefore, L ₃ ² = L _eq ² ⇒ L ₃ ² = ([16kT / (3 ・ β ₀ (n / p) · VE)] · B} / [(Kf / C _ox ) · ln (B _r )] [ln (B _r ) · L ₃ ² ] / B = [16kT / (3 · β ₀ (n / p ) · VE)] / (Kf / C _ox ) (46) At this time, the flicker noise and the thermal noise are almost equal.

[Appendix C: Limit of Unity Gain Frequency] The following equation (87) determines the limit of the unity gain frequency fT in a two-stage CMOS operational amplifier architecture. n = β ₀ (n / p) ・ (W ₃ / L _3fix ) ・ VE / [2π ・ fT ・ (L _1fix / L _3fix ) ・ βr (n / p) ・ C _gd・ W ₃ ] (87) Proof I do.

The CMOS operational amplifier has a phase compensation capacitance C _C ,
And the relationship between the unity gain frequency fT is as follows. gm ₃ = 2πC _C · fT (27) If fT approaches an infinite frequency, gm ₃ is finite, so C _C must approach zero. Phase compensation capacity
When C _C approaches zero, the phase compensation capacitance C _C approaches C _gs8 .

[0116] _{C C = n · (L 1fix} / L 3fix) · βr (n / p) · C gd · W 3 (78) wherein the gm ₃ (7) and (78), the equation (27) By substituting, equation (87) is obtained as follows. β ₀ (n / p) ・ (W ₃ / L _3fix ) ・ VE = 2π ・ n ・ (L _1fix / L _3fix ) ・ βr (n
/ p) ・ C _gd・ W ₃・ fT Therefore n = β ₀ (n / p) ・ (W ₃ / L _3fix ) ・ VE / [2π ・ fT ・ (L _1fix / L _3fix ) ・ βr (n / p) ・ C _gd・ W ₃ ] (87)

Therefore, the maximum unity gain frequency fTmax is expressed by a modification of the following equation (87). fT _max = β ₀ (n / p) ・ (W ₃ / L _3fix ) ・ VE / [2π ・ n ・ (L _1fix / L _3fix ) ・ βr (n / p) ・ C _gd・ W ₃ ] (C- 1)

As described above, according to the amplifier software IP of this embodiment, while inputting a predetermined amplifier characteristic,
By selecting an evaluation function that is a condition for optimizing the amplifier, the size of each component element and the capacitance value of the phase compensation capacitance of the CMOS operational amplifier satisfying these conditions are automatically obtained.

Therefore, for example, in the design of a digital / analog mixed LSI, it is possible to easily design an analog circuit which has conventionally been a barrier, especially an operational amplifier which is a main component in the analog circuit. As a result, the design efficiency of the digital / analog mixed LSI can be improved in each stage.

[0120] The LS and the maker jointly work together
ASIC (Application Specific) that designs and manufactures I
In the field of IC), by providing the amplifier software IP to the customer side, it is also possible to construct an environment similar to a gate array design in a digital circuit in an analog circuit. As a result, CMOS can be used during initial design of the integrated circuit.
It becomes possible to design the operational amplifier on the customer side or to optimize the analog circuit on the customer side.

Further, since the design algorithm uses the amplifier characteristics required for the LSI system (for example, characteristic parameters for which a transfer function can be defined) as setting parameters, the LSI
When performing the system design and the system simulation, the design and simulation can be simplified by the amplifier characteristics.

Also, the amplifier software IP as described above is
For example, by linking with an analog application circuit design tool such as a filter design tool, it can be easily extended as a semiconductor-level design tool for analog application circuits. For example, a useful tool for designing a filter at a semiconductor level can be provided in cooperation with a design tool for a switched capacitor filter.

Although the invention made by the inventor has been specifically described based on the embodiments, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the gist of the invention. Needless to say.

For example, in the embodiment, it has been described that the predetermined characteristic parameters representing the performance of the amplifier and the device parameters of the MOS are input parameters. However, the device parameters may be set to desired values before use. Some of the characteristic parameters of the amplifier can be used in a state where they are set to desired values in advance.

The design algorithm according to the present invention
It is not limited to the operational amplifiers shown in FIGS.
The present invention can be similarly applied to any type of CMOS operational amplifier as long as the amplifier corresponds to the AC equivalent circuit shown in FIG. When changing the type of the CMOS operational amplifier, the formula of the MOS size used in steps 6 and 7 of the design algorithm may be rewritten into an expression corresponding to the type.

In the above description, a design system for a digital / analog mixed LSI, which is an application field in which the invention made by the present inventor was used as a background, has been described. However, the present invention is not limited to this. It can be widely used for a design system of a semiconductor integrated circuit on which an analog circuit is mounted.

[0127]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, according to the present invention, by inputting a predetermined amplifier characteristic and selecting an evaluation function which is a condition for optimizing the amplifier, each component size and phase compensation capacitance of the CMOS operational amplifier satisfying these conditions are selected. Is automatically obtained, for example, there is an effect that the design efficiency of a digital / analog mixed LSI can be improved in each stage.

Since the design algorithm uses the amplifier characteristics required for the LSI system as setting parameters,
When performing system design and system simulation of an LSI, there is an effect that the design and simulation can be simplified by the amplifier characteristics.

[Brief description of the drawings]

FIG. 1 is a flowchart showing a design procedure of a digital / analog mixed LSI in which a CMOS operational amplifier design system according to the present invention is used.

FIG. 2 is a CMO to be designed by the design system of the embodiment.
FIG. 3 is a circuit configuration diagram and an AC equivalent circuit diagram of the S operational amplifier.

FIG. 3 is an example of another circuit configuration diagram of a CMOS operational amplifier that can be a design target.

FIG. 4 is a diagram showing a cascaded operational amplifier with a gain of 1 and an equivalent circuit.

FIG. 5 is a table showing amplifier design constants obtained by the design system of the embodiment.

[Explanation of symbols]

12 Amplifier software IP M1 to M5 MOSFETs M7 and M8 constituting a differential stage MOSFET Cc constituting an output stage Phase compensation capacitance of C _C

Continued on the front page F-term (reference) 5B046 AA08 BA03 DA05 5F064 BB01 BB21 BB24 CC12 DD04 DD09 EE45 HH06 HH09 HH10 HH12 5J066 AA01 AA47 CA00 FA12 HA09 HA17 HA25 HA29 KA05 MA22 ND01 ND14 ND22 A01 TA01 TA01 TA01 TA01 TA01 TA01 TA01 HA25 HA29 KA05 MA22 TA01 TA07

Claims (5)

[Claims] A circuit in which output nodes of two stages of cascaded amplifier circuits are connected via a phase compensation capacitor and A
C for finding the design constant of a CMOS operational amplifier equivalent to C
This is a design system for MOS operational amplifiers.
Gain a ₀ , unity gain frequency fT, phase margin φ,
Means for inputting an SN ratio α; calculating means for calculating design constants of each component of the CMOS operational amplifier based on the characteristic parameters and an algorithm derived from the following conditions 1 to 5: Phase compensation capacitance C _C = (C ₁ · C ₂ · tan (φ) / 2) ^(1/2) C ₁ : Output load capacitance of the first stage amplifier circuit C ₂ : Output load capacitance of the second stage amplifier circuit 2. 2. The sensitivity of the phase compensation capacitor C _C to the total current I _total is the minimum ∂I _total (C _C ) / ∂ (C _C ) = 0. _3. Relational expression between the unity gain frequency fT and the current Ids ₃ of the first-stage amplifier circuit Ids ₃ = πC _C · fT · VE VE: Effective bias voltage The gain a ₁ of the first stage amplifier and the gain of the second stage amplifier
a ₂ are equal _{a 1 = a 2 = (a} 0) (1/2) 5. Conditional expression n = gm ₈ / gm ₃ = [(C ₁ C ₂ + C ₂ C _C + C _{C] for} the current ratio n of the current gm ₃ flowing through the first stage amplifier circuit and the current gm ₈ flowing through the second stage amplifier circuit C ₁ ) / C _C ² ] · tan (φ). 2. The arithmetic unit further includes the following six conditions: Effective bias voltage VE ≦ 2 / ((a ₀ ) ^(1/2) · λ (n // p)) λ (n // p): λ (n // p) = λ (n / p) + λ (p / n) λ (n / p): Channel modulation parameter of n-channel MOS in the saturation region λ (p / n): Channel modulation parameter of p-channel MOS in the saturation region The CMOS operational amplifier design system according to claim 1, wherein: 3. The method according to claim 2, further comprising: setting an evaluation function representing a predetermined physical quantity related to the CMOS operational amplifier; wherein the calculation means includes an algorithm for optimizing the design constant based on the evaluation function. 3. The design system for a CMOS operational amplifier according to 1 or 2. 4. Device parameters required for the calculation include a power supply voltage VDD, an N-channel MOS and a P-channel M
OS threshold voltages Vth (n), Vth (p), voltage-current gain ratios β ₀ (n), β ₀ (p), channel modulation parameters λ (n), λ
(p), flicker noise coefficient k (n), k (p), unit gate capacitance Cox, unit diffusion capacitance Cd, unit gate-source capacitance C
gs, a unit gate-drain capacitance Cgd, and an input unit, wherein the operation unit is further configured to perform an operation based on the device parameter. CMOS operational amplifier design system. 5. A circuit in which output nodes of two cascade-connected amplifier circuits are connected via a phase compensation capacitor, and
This is a method for designing a CMOS operational amplifier that obtains a design constant of a CMOS operational amplifier equivalent to C by using a computer, wherein a DC parameter of the operational amplifier is used as a characteristic parameter required for calculation.
Gain a ₀ , unity gain frequency fT, phase margin φ,
A routine for inputting the SN ratio α, and a power supply voltage VD
D, threshold voltages Vth (n) and Vth (p) of N-channel MOS and P-channel MOS, and voltage-current gain ratio β ₀ (n), β
₀ (p), channel modulation parameters λ (n), λ (p), flicker noise coefficient k (n), k (p), unit gate capacitance Cox, unit diffusion capacitance Cd, unit gate-source capacitance Cgs, unit A routine for inputting a gate-drain capacitance Cgd, a routine for setting an evaluation function representing a predetermined physical quantity related to a CMOS operational amplifier, an algorithm derived from the above characteristic parameters, device parameters, and the following conditions 1 to 6: And an operation routine for obtaining a design constant of each component of the CMOS operational amplifier based on an algorithm for optimizing the design constant based on the evaluation function; Phase compensation capacitance C _C = (C ₁ · C ₂ · tan (φ) / 2) ^(1/2) C ₁ : Output load capacitance of the first stage amplifier circuit C ₂ : Output load capacitance of the second stage amplifier circuit 2. 2. The sensitivity of the phase compensation capacitor C _C to the total current I _total is the minimum ∂I _total (C _C ) / ∂ (C _C ) = 0. _3. Relational expression between the unity gain frequency fT and the current Ids ₃ of the first-stage amplifier circuit Ids ₃ = πC _C · fT · VE VE: Effective bias voltage The gain a ₁ of the first stage amplifier and the gain of the second stage amplifier
a ₂ are equal _{a 1 = a 2 = (a} 0) (1/2) 5. Conditional expression n = gm ₈ / gm ₃ = [(C ₁ C ₂ + C ₂ C _C + C _{C) for} the current ratio n of the current gm ₃ flowing through the first stage amplifier circuit and the current gm ₈ flowing through the second stage amplifier circuit C ₁ ) / C _C ² ] · tan (φ) 6. Effective bias voltage VE ≦ 2 / ((a ₀ ) ^(1/2) · λ (n // p)) λ (n // p): λ (n // p) = λ (n / p) + λ (p / n) λ (n / p): channel modulation parameter of n-channel MOS in the saturation region λ (p / n): channel modulation parameter of p-channel MOS in the saturation region Design method.