JP2002319300A - Semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To easily detect cut off state of a fuse, even after a device has been sealed in a mold as a circuit for compensating an internal potential of a semiconductor memory, and to vary an internal potential, independently of a cut off state of the fuse. SOLUTION: In a semiconductor memory, having an internal potential compensating circuit 2 for outputting the prescribed internal potential by voltage- dividing resistors Ri,..., R1, R2,..., Ri-1 in which reference internal potentials are connected in series and the prescribed internal potential is adjusted by switch transistors Tri,..., Tri-1 to be on/off driven using the prescribed fuse circuit 30 of a selector 13 and connected in parallel with each resistor Ri,..., Ri-1, the device has a test circuit 1 in which on-off of the switch transistors Tri,..., Tri-1 is controlled arbitrarily by external addresses A0-Am-1, and the prescribed internal potential is compensated for.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device having an internal potential correction circuit used in a DRAM or the like.

[0002]

2. Description of the Related Art At present, SDRA as a semiconductor memory device is used.
For M, use of an internal potential obtained by stepping down a power supply potential is mainly used due to a problem of a withstand voltage due to low power consumption and miniaturization of a process. However, the internal potential causes a deviation from a design value due to a variation in a manufacturing process. The difference from this design value is corrected using a predetermined correction circuit.

Further, in recent years, due to an increase in the number of DRAMs mounted on a system and a high-speed operation, noises and the like that cannot be realized by a measuring device such as a tester have been generated, which has hindered a DRAM-specific sensing operation. As a method for solving this, it is considered effective to change the internal potential on a tester. However, it is difficult to reproduce a defect using a current correction circuit using a fuse.

As an internal potential correction circuit of a conventional semiconductor memory device, there is a circuit as shown in FIGS.
This is a circuit that generates an internal level by dividing a reference power supply by resistance. This circuit is disclosed in, for example, Japanese Patent Application Laid-Open No. 7-144141. In FIG. 12A, the reference power source is
Of a circuit in which the resistors R21 to R24 of the resistors R21 to R26 connected in series and the fuses F11 to F14 connected in parallel are connected,
The fuses F11 to F14 are appropriately disconnected to obtain an output in which the internal potential has been corrected. In FIG. 14B, the resistors R21 to R24 of the resistors R21 to R26 connected in series are connected to the reference power source.
In this case, an aluminum master slice (hereinafter referred to as M / S) is prepared. The internal potential is corrected by cutting these fuses F1 to F4 or switching their M / S.

[0005]

However, in the prior art, in order to correct the internal potential, it is necessary to open the mold, cut the fuse, or change the M / S. Further, since the fuse cannot be restored once it has been blown, it is impossible to change the internal potential many times. In addition, the change of the M / S involves a mask change, and in any case, it takes much time to perform the evaluation. Further, in this method, since the internal potential cannot be changed on the tester, there is a problem that it is very difficult to make a device having no operation margin to be defective in a screening process by the tester.

A main object of the present invention is to provide a circuit for correcting an internal potential, which can easily cut a fuse even after a device is sealed in a mold, and furthermore, irrespective of a cut state of a fuse. It is an object of the present invention to provide a semiconductor memory device having a test circuit capable of changing the threshold voltage.

[0007]

According to the present invention, there is provided a switch having an internal potential correction circuit for dividing a reference internal potential and outputting a predetermined internal potential, and which is turned on and off using a predetermined fuse circuit. In a semiconductor memory device in which the predetermined internal potential is adjusted by a transistor, a test circuit for correcting the predetermined internal potential by turning on / off the switch transistor arbitrarily by an external address is provided.

In the present invention, the reference internal potential is divided by a resistor connected in series, a switch transistor is connected in parallel to each of the resistors, and can be driven on and off by a predetermined fuse circuit. May have a selector for switching between a drive signal of a switch transistor specified by an external address and a drive signal of a switch transistor specified by using a predetermined fuse circuit, and the test circuit may further include an external address and an external command. To set the test mode, the switching timing of the selector can be designated according to the test mode, and each output of the selector is output to the outside by the output switching circuit, so that the driving state of the switch transistor can be monitored. In addition, the test circuit Can be specified dress is made by the address pins or I / O pins.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of one embodiment of the present invention. As shown in FIG. 1, the semiconductor memory device of the present embodiment includes a test circuit 1, an internal potential correction circuit 2, and an output switching circuit 3, and the test circuit 1 of the present embodiment includes a test circuit 1. A mode setting circuit (TC) 11, a register 12 for storing an address for resistance selection, a selector 13 with a built-in fuse, and transistors TRi and TRi-1 for controlling on / off of the resistance are provided. In this test circuit 1, the number of address pins is n, the number of addresses is m, and i = m + 2.

In the test circuit 1, the test mode setting circuit 11 makes an entry to a test mode for changing the internal potential in accordance with an address code at the time of inputting a mode register set command (hereinafter referred to as MRS) conforming to JEDEC, and an address latch. A signal (hereinafter referred to as AL) and a test mode entry signal (hereinafter referred to as TE) are generated. The test mode entry signal TE is at the power supply potential (hereinafter, high level) in the test mode, and is normally at the GND potential (hereinafter, low level). Further, the address latch signal AL is input to the register 12, and holds the address input from the outside.

Further, as shown in the circuit diagrams of FIGS. 2 and 3, the selector 13 outputs the output of the selector 13 by the test mode entry signal TE to the signal from the fuse unit 30 and the address signal (RA0 to RAm-1) from the register. ) To switch on and off the resistors Ri and Ri −1 to vary the resistance and change its internal potential. This test circuit 1 has a resistance R
It is possible to control on / off of i, Ri-1. Further, the operation of outputting the fuse cutting information to the outside is performed by inputting the mode register set command MRS and the address code (FRA) for reading the fuse number without setting the test mode entry signal TE to the high level.

In the circuit of the selector 13 shown in FIG.
A fuse unit 30 including a fuse F1 and a resistor R11 connected in series is provided between C and the ground GND, and a test mode signal TE and a switch transistor TR11 having a gate input of a signal obtained by inverting this signal by an inverter 31 are provided.
12, the connection point between the fuse F1 and the resistor R11 is input, and the switch transistors TR13 and TR14 are used as gate inputs of signals opposite to the switch transistors TR11 and TR12.
, Inputs from the register 12 (RA0 to RAm-1), and outputs of these transistors TR11 to TR14 are connected to the transistor TRi-1.

The circuit of the selector 13 shown in FIG.
The connection of the fuse portion 30 between the fuse F1 and the resistor R11 of FIG.
2 includes a fuse portion 30a on the ground side, and the inverter 32 and the other switch transistors TR15 to TR18 in the other circuits are the same as the inverter 31 and the transistors TR11 to TR14 in FIG.

Referring to FIG. 1, during normal operation of the SDRAM (when TE is at a low level), the output from the fuse portion is transmitted to the internal potential correction circuit 2 as it is, and the internal potential is corrected by the cut state of the fuse.

With respect to the internal potential correction by this fuse,
The details provided in the present embodiment are described in a test mode setting circuit 11 as shown in FIG. 4 and a fuse selection address storage register (hereinafter referred to as a register) 1 as shown in FIG.
2, a selector (hereinafter referred to as a selector) 13 for selecting an output from the register 12 and the fuse section, an internal potential correction circuit 2 controlled by an output of the selector 13, and an output switching circuit 3 as shown in FIG.

The test mode setting circuit 11 shown in FIG.
8, m = 6, external command and clock CLK
A flip-flop (hereinafter referred to as FF) 20 for outputting an MDRS, an AND gate 21 for addresses A8 and A7, an AND gate 22 for receiving the output of the AND gate 21 and the output of the FF 20, and an inverter 23 An AND gate 24 for inputting the inverted signal and the output of the AND gate 21; a data input for the address A6; a clock input for the output of the AND gate 22;
25, an output of the AND gate 24 as a data input, an output of the FF 20 as a clock input, and an FF 26 for outputting an FR. And an AND gate 29 which receives a signal and outputs AL.

The test mode setting circuit 11 generates TE, AL and a fuse number read signal (FR) in response to an external input. The register 12 holds an externally input address through the AL and transmits the signal to the selector 13. The selector 13 selects and outputs a signal from the register 12 and a signal from the fuse unit by TE. This output is transmitted to the internal potential correction circuit 2 and the output switching circuit 3.

As shown in FIG. 1, the internal potential correction circuit 2
MOS transistor TRi, NMOS transistor TR
By turning on / off i-1, series resistances Ri and Ri-1 connected in parallel with these are turned on / off to correct the internal potential. By preparing a plurality of combinations of the resistors Ri, Ri-1 and the transistors TRi, TRi-1 of the internal potential correction circuit 2, the voltage can be finely set.

As shown in the circuit of FIG. 5, the register 12 has an FF 41 which inputs addresses A1 to Am-1 as data, inputs AL as a clock input, and outputs addresses RA0 to RAm-1 to the selector 13. , 42 ... 43
Consists of The output switching circuit 3 in FIG. 6 selects the normal outputs VO0 to VOm-1 and the outputs SA0 to SAm-1 from the selector 50 based on the read signal FR, and outputs the fuse cutting information to the outside via the output circuit.

The operation of this embodiment will be described below. First, the operation of the TC of FIG. 1 will be described with reference to the timing charts of FIGS. This circuit is JEDEC from outside
By inputting the compliant MRS and the address code within the range that each vendor can freely set, TE and A are output as output.
L and FR signals are generated.

At the timing shown in FIG. 7, an external clock CLK and an external command are input, and the fuse number read signal FR first rises by the mode register set signal MRS of the command, and the FR falls at the next clock. Rise and AL also occur. The address Am-n includes a fuse read address code FRA and a test mode entry address code TRA, and the addresses A0 to Am-1 include a fuse selection address FA. To RAm-1 and outputs SA0 to SAm-1 of the selector 13 are obtained.
The output FU is obtained from the fuse unit 30 of FIG.

FIG. 8 is a timing chart corresponding to the circuit of FIG. 4 and shows a case where n = 8 and m = 6.
This signal is at a high level during the rising edge of the clock when MRS is input.

The test mode entry signal TE is at a low level during normal use of the device, but attains a high level when an MRS and an address code for changing an internal potential (hereinafter referred to as a test mode). Once at a high level, the command exits the test mode. Hold the level until you enter. In the present embodiment, when FR goes high, TE
Is set to a low level. AL is at a high level once for a certain period of time at the same time that TE is output at a high level, and is at a low level during other periods. FR becomes high level by the address code at the time of inputting the mode register set command similarly to TE, and becomes low level when MRS is next input.

On the other hand, the register 12 operates according to the timing chart of FIG. 7 and takes in the external addresses A0 to Am-1 only when AL is at a high level, and holds this data when AL is at a low level. Data is continuously output as address signals RA0 to RAm-1. That is,
The external address code (A0 to
When (Am-1) is input, the values of the external addresses A0 to Am-1 are continuously output from the register 12.

The operation of the selector 13 is performed according to the timing charts of FIGS. The potential of TE selects the output of the selector 13 between the potential of the fuse unit and the inputs RA0 to RAm-1 from the register. When TE is at a high level, the potential of RA0 to RAm-1 is output.
When TE is at the low level, the potential from the fuse unit 30 is output.

The operation of this fuse section is as follows. In the case of an NMOS transistor selector, as shown in FIG. 2, the power supply VCC and GND are connected via a fuse and a resistor. Outputs a high level. In the case of the selector for the PMOS transistor, as shown in FIG. 3, the operation is opposite to that of the selector for the NMOS. Next, outputs SA0 to SAm from the selector 13
The on / off of the transistors TRi, TRi-1 connected in parallel with the resistors Ri, Ri-1 is controlled by -1, and the internal potential is changed as shown in FIG. For example, when m = 2, when SA0 is at the low level and SA1 is at the high level, the internal potential is determined by the resistors R1 and R2 and the reference internal potential (Vr), and the internal potential (Vref) represented by the following equation (1). Becomes

Vref = R2 · Vr / (R1 + R2) (1) Further, if SA0 is at a high level, the transistor TRi is turned off and a current flows through the resistor Ri. Becomes

Vref = R2 · Vr / (R1 + R2 + Ri) (2) In addition, by inputting an address code for setting MRS and FR to a high level in the test mode setting circuit 11, FR
Is set to a high level, the output switching circuit 3 switches the normal I / O potential to the potentials SA0 to SAm-1, and outputs the potential to the outside via the output circuit. This FR is at a high level until the next MRS is input. At this time, if the potential of TE is at the low level, the output potential from the fuse section is output as it is. That is, the fuse cutting state can be known.

According to the circuit of the present embodiment, the cutting information of the fuse can be easily known even after the mold is sealed, and the internal potential of the device can be easily changed regardless of the cutting state of the fuse. can get.

FIGS. 11 and 12 are circuit diagrams showing specific examples of the embodiment of FIG. 1 and tables showing the relationship between addresses, resistance values and output voltages.
i, Ri-1 and therefore four transistors TR
3 shows a case where there is TR6. That is, in correspondence with the four addresses A0 to A3, from the outputs of the register 12 and the selector 13 according to the combination of ON and OFF, as shown in FIG.
To 16), and the voltage dividing resistance ratio Vref / Vr is calculated as shown in the chart, and the internal voltage Vref with respect to the reference internal voltage Vr is calculated.

In FIG. 12, for example, at the address "1001" of No. 10, the transistors TR3 and TR6 are turned on and the transistors TR4 and TR5 are turned off, so that Vref = (R2 + R5) .Vr / (R1 + R2 + R4).
+ R5), and the resistance R1 = 25 kΩ and R2 = 100 k
Ω, R3 = R6 = 100 kΩ, R4 = 5 kΩ, R5 = 2
When 0 kΩ and Vr = 2.5 V (1), an internal voltage Vref = 2.0 V is obtained.

In FIG. 12, the reference internal voltage Vr is
In the case of 2.5 V (1), this reference internal voltage Vr is
(2) when the voltage changes to 2.4 V. When the reference internal voltage Vr requires 2.0 V, when the reference internal voltage Vr is 2.5 V (1), No10 (or 1)
6), the address is “1001” (or 1111). If the reference internal voltage Vr becomes 2.4 V (2), the address “110” of No. 14 or No. 15
0 "(1101). Note that these resistance values and voltages can be arbitrarily combined according to the design conditions.

As another embodiment of the present invention, an I / O pin is used instead of an address pin, or a fuse portion is M / O.
S, and the selector 13
Circuits such as those shown in FIGS. That is, a logic circuit is used in place of the switching transistor shown in FIGS.
Using a NAND gate 51, an AND gate 52 and an OR gate 53 in place of the transistor TR
Instead of 15-18, AND gates 54, 55 and O
This uses an R gate 56. This circuit is also shown in Figs.
Obviously, it behaves the same as.

[0034]

As described above, according to the present invention,
By using a tester even after being enclosed in the mold,
Since the internal potential can be changed, it is possible to remove a defective product on the system, which was conventionally difficult to be distinguished as a defective product on a tester, in a sorting process by the tester. Furthermore, knowing the fuse blown state
The reference internal potential is determined, and it is possible to evaluate the optimal combination of fuse blows, including changes in characteristics due to mold encapsulation, and reflect the evaluation results in the fuse blow process in the previous process to improve device characteristics The effect is obtained. In this evaluation, since the internal reference potential is known, the combination of the resistance and the internal potential can be specified, and the internal potential can be changed only by a tester without cutting the fuse or changing the mask. There is an effect that the internal potential dependent evaluation can be performed.

[Brief description of the drawings]

FIG. 1 is a block diagram of a semiconductor memory device for explaining a first embodiment of the present invention.

FIG. 2 is a circuit diagram of a part of a selector 13 of FIG.

FIG. 3 is a circuit diagram of another portion of the selector 13 of FIG.

FIG. 4 is a circuit diagram of the test mode setting circuit of FIG. 1;

FIG. 5 is a circuit diagram of a register 12 of FIG. 1;

FIG. 6 is a circuit diagram of a portion of the output switching circuit 3 of FIG. 1;

FIG. 7 is a waveform chart for explaining the operation of the test circuit 1 of FIG. 1;

FIG. 8 is a waveform chart for explaining the operation of the test mode setting circuit 11 of FIG. 1;

FIG. 9 is a waveform chart for explaining the operation of the selector 13 in FIG. 1;

FIG. 10 is a waveform chart for explaining the operation of the internal voltage correction circuit 4 of FIG. 1;

FIG. 11 is a circuit diagram showing a specific example of FIG. 1;

FIG. 12 is a diagram illustrating a relationship among an address, a resistance value, and an output voltage in FIG. 11;

FIGS. 13A and 13B are circuit diagrams of a semiconductor memory device according to a second embodiment of the present invention.

14A and 14B are circuit diagrams of a conventional semiconductor memory device.

[Explanation of symbols]

1 Test Circuit 2 Internal Potential Correction Circuit 3 Output Switching Circuit 11 Test Mode Setting Circuit 12 Register 13, 50 Selector 20, 25, 26, 41-43 Flip-Flop 20, 22, 24, 29, 52, 54, 55 AND
Gate 23, 28, 31, 32 Inverter 27 Delay element 30, 30a Fuse part 51 NAND gate 53, 56 OR gate F1, F2, F11 to F14 Fuse R1 to R6, R11, R12, R21 to R26, Ri,
Ri-1 resistors SW1 to SW4, switches TR1 to TR6, TR11 to TR18, TRi, TRi
-1 transistor

Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat II (Reference) H01L 27/04 G01R 31/28 B WF Term (Reference) 2G132 AA08 AB00 AD05 AG08 AK15 AL14 5F038 AV02 BB05 BB07 DT02 DT03 DT15 EZ20 5L106 AA01 DD12 EE08 5M024 AA20 AA40 AA93 BB29 BB30 BB40 DD40 FF20 FF30 HH01 HH10 MM04 MM05 PP01 PP02 PP03 PP07 PP10

Claims (7)

[Claims] An internal potential correction circuit for dividing a reference internal potential and outputting a predetermined internal potential, wherein the predetermined internal potential is adjusted by a switch transistor that is turned on and off using a predetermined fuse circuit. A semiconductor memory device, comprising: a test circuit for arbitrarily controlling ON / OFF of the switch transistor by an external address and correcting the predetermined internal potential. 2. The semiconductor memory device according to claim 1, wherein the reference internal potential is divided by a resistor connected in series, a switch transistor is connected in parallel to each of the resistors, and is turned on / off by a predetermined fuse circuit. 3. The semiconductor according to claim 1, wherein the test circuit has a selector for switching between a drive signal of the switch transistor specified by the external address and a drive signal of the switch transistor specified by using a predetermined fuse circuit. Storage device. 4. The semiconductor memory device according to claim 3, wherein a test mode of the test circuit is set by an external address and an external command, and a switching timing of a selector is designated according to the test mode. 5. The semiconductor memory device according to claim 3, wherein each output of the selector is output to the outside by an output switching circuit so that a driving state of the switch transistor can be monitored. 6. The semiconductor memory device according to claim 3, wherein the selector switched according to the test mode comprises a switching circuit composed of a transfer gate or a switching circuit combining logic circuits. 7. The test circuit according to claim 1, wherein an address of the test circuit is specified by an address pin or an I / O pin.
7. The semiconductor memory device according to 3, 4, 5, or 6.