JP2002319290A - FLASH EEprom MEMORY SYSTEM AND UTILIZATION METHOD THEREFOR - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an EEprom array, having large storage capacity and service life and moreover technology for increasing the number of times of programmings and erasures which the EEprom can withstand. SOLUTION: A semiconductor substrate 11 has a source region 13 and a drain 15, and a channel region 17 is arranged between the source 13 and the drain 15. A floating gate 19 is arranged on a channel region L1 region, this is separated by a gate oxide 21. A control gate 23 is formed on a region L2 , and this is separated by a gate oxide 25. The control gate 23 also is electrically separated from a floating gate 19 by a oxide layer 27.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention generally relates to electrically programmable read only memory (Eprom) semiconductors and electrically erasable and programmable read only memory (EEpro).
m), and more specifically, the technology that utilizes it.

[0002]

2. Description of the Related Art An electrically programmable read-only memory (Eprom) has a field-effect transistor structure and is provided between a source and a drain region insulated from a channel of a semiconductor substrate region. A conductive gate (no connection) is used. The control gate is provided above the floating gate and is insulated therefrom. The threshold voltage characteristics of the transistor are controlled by the amount of charge trapped on the floating gate. That is, to allow conduction between its source and drain regions, the voltage that must be applied to its control gate before the transistor is turned on, ie, its voltage is its threshold voltage, its minimum voltage Threshold voltage). A transistor can be programmed in one of two states by accelerating electrons to the floating gate through a thin dielectric gate in the channel region of the substrate.

[0003] The state of a transistor in a memory cell can be read by applying operating voltages to the source, drain and control gate of the transistor, and the current flowing between the source and drain when the control gate voltage is selected is detected. By doing so, it is possible to know whether the device is programmed on or off. To address a particular cell in a two-dimensional array of Eprom cells for reading, a source and drain voltage is applied between the source and drain lines of the column containing the cell to be addressed. And applying a control voltage to the control gate of the matrix containing the cell to be addressed.

Examples of such memory cells include triple polysilicon, channel-separated, electrically erasable and programmable read-only memory (Eprom). This is called a spirit channel device because the floating and control gates extend over adjacent portions of the channel. Thus, the transistor structure acts as two transistors in series, one having a variable threshold channel responsive to the charge level on the floating gate, the other being unaffected by the charge on the floating gate, Rather, it works in response to the voltage applied to its control gate, similar to a normal field effect transistor.

[0005] Such a memory cell is called triple polysilicon. This is because it has a triple conductive layer of polysilicon material. An erase gate is included in addition to the floating and control gates. The erase gate passes close to the floating gate surface of each memory cell transistor,
They are insulated from them by a thin tunnel dielectric (having a tunnel effect). Charge is removed from the floating gate of the cell to the erase gate when the appropriate voltage is applied to all transistors. When the entire array of cells or a particular group of cells are erased at the same time (ie, by flash), the cells of such Eprom are referred to as flash Eprom arrays.

EEprom has come to be known for its finite useful life. The number of times such devices can be programmed and erased before performance degrades is finite. Its characteristics are dependent on the particular structure, but its programmability decreases after more than 10,000 use cycles. After such a device has been used for more than 100,000 use cycles, it can no longer be programmed or properly erased. This is believed to be the result of the charge being transferred or removed to the floating gate for programming or erasing being trapped in the dielectric.

[0007]

SUMMARY OF THE INVENTION It is an object of the present invention to provide an EEprom array with increased storage capacity and lifetime. Another object is to provide a technique for increasing the number of times of programming and erasing that one EEprom can withstand. Still another object of the present invention is to provide
It is to provide a technique for increasing the amount of information stored in an Eprom or an array of EEProm of a given size. Still another object of the present invention is to provide an EEprom semiconductor chip that can be used as a solid-state memory that can replace a magnetic disk storage device.

[0008]

Various objects can be achieved from various aspects of the invention. Here, if briefly described in general terms, each Eprom or EEpr
The om memory cell can store one or more data by dividing its programmed charge into three or more ranges. Each cell can thereby be programmed to one of these ranges. For example, if four ranges are used, two bits of data are stored in one cell.
If eight ranges are specified, three bits are stored.

[0009] An information program and a sensing technique which allow a realistic configuration capable of storing such multi-stages are provided. In addition, an algorithm for erasing information is provided that effectively removes the electrical stress applied to the erasing tunnel dielectric, thereby providing more endurance to the program and erase cycles, and , The life of the memory can be increased.

A flash EEprom memory system and method of use according to the present invention includes: (1) an array of electrically modifiable memory cells is divided into blocks of cells, which address individual cells within said blocks. Means for reading and changing the state of said memory cell, said memory cells individually having a field effect transistor with a floating gate, and having a threshold voltage level, said level being provided when said floating gate has no net voltage. For an array of memory cells, the level being variable by a net amount of charge held on the floating gate, in a method of operating the array: a plurality of effective thresholds greater than two Establishing a voltage level, said level being greater than two individual Corresponding to a plurality of detectable states of a cell, and setting an effective threshold level of at least one addressed cell in the block to one of the plurality of levels; Increasing the amount of charge on the addressed at least one floating gate until the effective threshold voltage of the at least one addressed cell is substantially equal to one of the plurality of the effective threshold voltages. Changing the state of the at least one addressed cell to one of the plurality of states, and wherein a cell in an individual one of the blocks of the cell comprises one of the plurality of states. Accumulating a count equal to the total number of times set to one of the following. (2) In the method according to (1), the step of accumulating a count of an individual block of the block is configured to store the count in the individual block of the block. (3) The method of (1), wherein at least one auxiliary memory cell block is provided, and in response to the count of each one of the blocks exceeding a set number. , Additionally replacing the auxiliary block in place of the individual one of the blocks. (4) The method according to (1), wherein a plurality of auxiliary memory cells are provided, and the at least one addressed memory cell is responsive to the at least one addressed memory cell being defective. Instead of replacing at least one of the auxiliary cells. (5) In the method according to any one of (1) to (4), the step of establishing a plurality of effective threshold voltage levels includes the step of establishing at least four such threshold voltage levels. It is comprised including. (6) In a system separated by a plurality of well-defined blocks of cells with electrically changeable memory cells, and having means for addressing individual cells in said blocks to read and change their state, Each cell includes a field effect transistor having a floating gate, each cell having one threshold voltage level which is a predetermined level if there is no net charge on the floating gate, Variable in accordance with the net charge held on the gate and operating the memory system, comprising: (a) a threshold voltage level of a plurality of effective memory cells of more than two memory cells, the level being 2 Levels corresponding to the states of a plurality of individually detectable memory cells exceeding Establishing a memory cell threshold voltage level; providing an auxiliary cell in place of any defective cells in the block of memory cells; and floating the memory cell in at least one of the block of cells. Changing the amount of charge on the gate simultaneously in the direction of the effective base threshold voltage level to preset the effective threshold voltage; and at least one of the at least one cell in the block of at least one cell. Changing the amount of charge on the floating gate of one memory cell to shift its effective threshold voltage in a desired one of the plurality of effective threshold voltage levels, thereby removing at least one memory cell. A changing step of setting to one of a plurality of detectable states and a desired effective threshold voltage level Generating the address of any cell in the block of cells that is not changed, and wherein the setting step includes replacing the at least one arbitrary memory cell whose address so generated with the auxiliary cell. It is composed of (7) The method according to (6), further comprising the step of separately accumulating a total count of the preset number of blocks of each cell. (8) In the method according to (6), the presetting step includes changing an amount of charge on a floating gate of a memory cell in the at least one block of the cells. N
Continue until the effective threshold level of the memory cells other than the memory cell reaches the effective base threshold level, wherein:
The step of generating an address comprises generating an Nth address of the cell. (9) In the method according to any one of (6) to (8), the step of establishing a plurality of effective threshold voltage levels comprises the step of establishing at least four such threshold voltage levels. It is comprised including. (10) An array of electrically modifiable memory cells, said array being divided into blocks of cells, having means for addressing individual cells within said block and reading out and changing their state, wherein said memory cells are Individually comprising a field effect transistor having a floating gate, having a threshold voltage level, said level being a predetermined level in the absence of a net charge on said floating gate, but a net level held by said floating gate Variably depending on the amount of charge of the array and operating the array: establishing more than two effective threshold voltage levels corresponding to more than two detectable states of individual cells; Reducing the effective threshold voltage level of each of the plurality of cells addressed to one of the blocks to one of the plurality of levels Resetting the amount of charge on the floating gate of each of the plurality of cells until the effective threshold voltage of the cells is substantially equal to one of the plurality of effective threshold voltage levels. Changing the state of one of the plurality of addressed cells of the plurality of states to be individually set; and changing at least one block of the cell other than the one block of the block. By replacing the one of the auxiliary blocks with the auxiliary block of the cell, the cells in the auxiliary block of the cell are addressed to set their effective threshold voltage level to one of the plurality of levels. And possible replacement steps. (11) The method of (10), further comprising the step of monitoring blocks of individual cells, and responsive to detecting that one of the blocks of cells has reached endurance limits, And starting a cell replacement step. (12) In an electrically modifiable memory cell array, said cells are divided into distinct blocks of cells and have means for addressing individual cells within said blocks to read and change their state, The memory cell has individual field effect transistors with floating gates, and the cell has a threshold voltage level;
The level is a predetermined level when there is no net charge on the floating gate, but is variable in response to the net charge held by the floating gate, and in a method of operating the array: Establishing a plurality of effective threshold voltage levels greater than two, wherein the levels correspond to a plurality of detectable states of more than two individual cells; and an effective threshold voltage of each of a plurality of memory cells in one of the blocks. Changing a threshold level to an amount of charge on each floating gate of the cell until the effective threshold voltage is substantially equal to one of the plurality of effective threshold voltage levels. Setting the states of the plurality of cells individually to be one of a plurality of seasonal states; and
Reading the status of said plurality of memory cells with the aid of an error correction scheme. (13) an array of electrically modifiable memory cells, said cells being divided into blocks of cells and having means for addressing individual cells within said blocks to read and change their state; The memory cell individually includes a field effect transistor having a floating gate, and the cell has a threshold voltage level, the level having a predetermined threshold voltage level if the floating gate has no net charge. Wherein the method of operating the array is variable in response to a net charge held by the floating gate: establishing a plurality of effective threshold voltage levels greater than two, wherein the levels are greater than two individual threshold voltages; Corresponding to a plurality of detectable programmed states of cells of at least one of said blocks. Changing the amount of charge on the floating gate of the addressed cell until it is substantially equal to one of the effective threshold voltage levels of the addressed cell; Setting the effective threshold voltage level, thereby setting the state of the aorexed cell to one of the plurality of programmed states: activating the addressed cell. Applying a constant voltage to the addressed cell for a predetermined period of time sufficient to move a threshold voltage from a starting level to one of the plurality of threshold voltage levels; An electrical parameter of the addressed cell is determined by determining an effective threshold voltage of the addressed cell by the plurality of threshold voltage levels. Reading to determine if one of the plurality of threshold voltages has been reached, and that the effective threshold voltage of the addressed cell has been set to one of the plurality of threshold voltage levels. And a step of repeating the reading step until it is detected by the reading step. (14) In the method according to (13), the voltage applying step may be configured such that the effective threshold voltage of the addressed cell is equal to the effective voltage of the plurality of effective threshold voltages and the predetermined time. Threshold voltage level adjacent two
And making the change even less than half between the two. (15) The method according to (13), wherein the reading step electrically interrogates the addressed cell, and sets a result level of an electric parameter of the addressed cell to a plurality of reference levels of two or more. At the same time. (16) In the method of (13), before setting an effective threshold level of at least one addressed cell of one of the blocks, an effective threshold of cells in the at least one block. Resetting the value voltage level to a preset level, wherein at the reset: a cell in the at least one block has the effective threshold voltage of a cell in the at least one block at the preset level. Applying a given voltage for a predetermined period of time sufficient to move the electrical parameters of the cells in the at least one block to the at least one
Reading to determine if the effective threshold voltage of the individual cells in one block has reached the preset level, and applying a voltage to the cells in the at least one block Is repeated until it is detected that the effective threshold voltage of the cells in the at least one block has been reset to the preset level. (17) The method according to (16), wherein the preset level is substantially equal to one of the plurality of effective threshold voltage levels corresponding to a plurality of detectable programmed states of an individual cell. It is configured. (18) The method according to (16), wherein the at least one effective threshold voltage level is reset while resetting the effective threshold voltage level.
The voltage applied to the cells in one block is configured to rise when the steps of applying and reading the voltage are repeated. (19) In the method according to (16), the step of reading the electrical parameter of a cell in the at least one block comprises: electrically interrogating a cell in the at least one block; And comparing the resulting level of the individual electrical parameters of the cells within the plurality of reference levels simultaneously. (20) The method according to any one of the above (13) to (19), wherein, among the plurality of effective threshold levels,
At least two are configured to be due to a net positive charge on the floating gate of the individual cell. (21) In the method according to any one of (13) to (19), the given threshold level of the individual cells is set to at least 3 volts. (22) The method according to any one of (13) to (19), wherein the applying and reading the voltage while the effective threshold voltage level of the at least one addressed cell is set. The repetition of the steps comprises: setting a preset maximum number of repetitions of the voltage application and reading steps without setting the effective threshold voltage level of the addressed set to one of the plurality of threshold voltage levels. Is configured to be terminated after it occurs. (23) In the method according to any one of (13) to (19), the repetition of the voltage application and the reading step is performed while resetting an effective threshold voltage level of a cell in the at least one block. Terminating after resetting the preset maximum number of voltage application and reading steps while resetting without resetting some of the effective threshold voltage levels of individual cells within the at least one block. It is configured to be. (24) The method according to any one of (13) to (19), wherein the at least one addressed cell is replaced with an auxiliary good cell in the array in response to the defect. It is configured to additionally include steps. (25) The method according to any one of (13) to (19), wherein a block of at least one auxiliary cell in the array is responsive to the at least one cell becoming defective. It is configured to additionally include a replacing step. (26) The method according to any one of (13) to (19), further comprising accumulating a count of the total number of times that at least one block of cells has been reset. .

An embodiment of the fault management error correction code of the flash EEprom memory system according to the present invention comprises the following steps: A method of operating an integrated circuit memory system that is addressable for reading includes the following steps: providing a plurality of distinct blocks of memory cells, wherein the cells of the individual blocks are taken together. Being erasable, performing an erase operation on memory cells in at least one block, and not erasing cells in the at least one block after the erase operation has been performed. To determine if any are present, and if so, Determining the number of non-erased cells and comparing the number of non-erased cells with an allowable number, wherein the allowable number is substantially the maximum number of cells, and if the data of the cells is bad. A comparing step that can be corrected by an error correction scheme, and if the number of non-erased cells in a block is less than an allowed number, the memory of at least one erased block is replaced with new data. Re-programming, and replacing the non-erased cells with another auxiliary memory if the number of non-erased cells in one block is greater than the allowed number;
It is composed of (A2) In the method according to (A1), the replacing step determines an address position of a non-erasable cell in at least one block, stores the address position, and identifies an auxiliary good cell. It is configured to include a replacing step. (A3) The method according to (A1), further comprising the step of setting a flag when at least the number of cells that are not erased in a certain block exceeds another number that is considerably larger than the allowed number. (A4) In the method according to (A1), the erase operation is performed as follows: at least addressing a block, initiating an erase cycle of a memory cell therein, and during the erase cycle. Determining the state of the memory cells within at least one block, and when it is determined that all memory cells of at least one block are to be erased or when a predetermined condition is reached , At least 1
Ending the erase cycle before all cells of one block are erased. (A5) The method according to (A4), wherein the predetermined condition is that all memory cells in one block have been erased leaving a predetermined number or a smaller number. It is configured to include conditions. (A6) An integrated circuit memory system includes an array of non-volatile floating gate memory cells, the individual cells of which are addressable for programming and reading, in a method of operating the memory system: Provide multiple distinct blocks of
Therein the cells of the individual blocks can be erased together to form a ground state, where 1
Memory cells in the one or more erased blocks provide a subsequently reprogrammed block; addressing one of the plurality of blocks, initiating an erase cycle of the memory cells there; Determining the state of the memory cells in at least a block during a cycle, and when it is determined that at least all memory cells in a block should be erased, or at least all of a block Terminating the erase cycle when a predefined condition is reached before the cells of the block are erased; and if the erase cycle is terminated before at least all cells of a block are erased, At least the number of unerased memory cells in a block is the allowed number, Determining whether the error correction plan when the data is incorrect is smaller or larger than the maximum number of cells that can be corrected; and Reprogramming the memory cells in the at least one erased block with new data;
Substituting other auxiliary memory cells for non-erased memory cells when at least the number of non-erased cells in a block is greater than the allowed number. (A7) In the method according to (A5), the replacing step includes a step of determining an address position of a cell which is not erased in at least one block. (A8) In the method according to (A5), the predetermined condition of the erase cycle is to reach a condition, which condition is an allowable number of memory cells in at least one block or less. Except for the case, all the memory cells in the at least one block are erased. (A9) The method according to (A5), wherein the erase cycle includes a step of applying a plurality of erase pulses to the memory cells in at least one block in a state determined between the erase pulses. Have been. (A10) In the method according to (A9), the predetermined condition of the erase cycle includes a step of reaching a given number of erase pulses during the erase cycle. (A11) The method according to (A9), wherein the plurality of erase pulses increase in amplitude during the erase cycle, and the predetermined condition is such that the amplitude of the erase pulse reaches a predetermined maximum level. And the step of reaching.

An embodiment of the erasing algorithm of a flash EEprom memory system according to the present invention comprises the steps of: (B1) Targeting a block of addressed cells in an electrically erasable and programmable read-only memory row and column array. Wherein each cell has a field-effect transistor having a threshold voltage, and the voltage can be changed by controlling the charge level at its floating gate. The method includes the following steps:
Applying a controlled voltage appropriate for the cells of the block of addressed cells toward the target erase charge level for a time sufficient to change their individual charge levels; Reading the level of charge on the floating gates of at least a plurality of cells in the block of cells generated; determining if one of a plurality of conditions has occurred in relation to some of the plurality of cells; Until it is determined whether at least some of the plurality of cells have experienced one of the conditions.
Repeating the above steps as necessary, followed by reading the floating gate and charge levels of the cells of the block of addressed cells, and then, during the block of addressed cells, Determining the number of cells N that do not reach the required erase charge level, and then comparing the number of cells N with an acceptable number X of non-erased cells. I have. (B2) In the method according to (B1), at least some of the plurality of cells comprise substantially less than all cells in the block of addressed cells. (B3) The method according to (B1), wherein it is determined that one of a plurality of conditions has occurred in relation to the plurality of cells, and then an erase pulse is applied to the block of addressed cells. The method further comprises the step of applying. (B4) In the method according to (B1), in response to the fact that the number of cells N has not reached the erase level exceeding an allowable number X in the comparison step, E) generating an address location of a cell that has not reached the erase level if the number of cells that have not reached the erase level is less than or equal to a second cell number that is higher than the acceptable number; (b) generating a patience limit flag if the number of cells N that have not reached the erased level exceeds the second number of cells. (B5) In the method according to (B1), the plurality of conditions include a condition that the number of cells N that have not reached the erase target voltage level of the addressed block of cells is equal to or less than an allowable number. It is composed of (B6) A method for erasing memory states from a block of addressed cells of an array of electrically erasable and programmable read only memory (EEPROM) cells, wherein said cells program cells with their states. ,
A natural threshold voltage that has means for addressing the cells for reading and erasing, each of which can control and change the level of charge on the floating gate to obtain an effective threshold voltage And wherein the natural threshold voltage is that corresponding to that when the level of its floating gate charge is equal to zero, comprising the following steps: towards the erase voltage level Pulse the addressed cells for a predetermined period and voltage sufficient to change their individual threshold voltage, but not enough voltage to fully reach the erase threshold level And then reading the current through a selected number of cells to ensure their effective threshold voltage; and Repeating the applying and reading steps a plurality of times, terminating said applying and reading steps after any one of the following conditions has occurred: and the effect of each of the selected number of blocks of the addressed cell. The threshold voltage has reached an erased threshold level; the pulsing step has reached a preset maximum number; or the predetermined maximum voltage for the pulse is Has a recent pulsing step been reached; the remaining number of non-erased cells of the selected number of cells N is equal to or less than the number of unerased cells that can be accepted. (B7) In the method according to (B6), the predetermined voltage is increased by a certain increment from that of the previous pulse applying step. (B8) In the method according to (B6), after it is first detected that one of the plurality of conditions has occurred,
And applying an erase pulse to the addressed cell. (B9) In the method according to (B6), the selected number of cells is clearly less than the total number of addressed cells.

A flash EEprom memory system according to the present invention comprises: (a) a flash electrically erasable and programmable read having a memory state defined by a real charge on a floating gate electrode capable of modulating transistor channel conduction; In only memory cells,
Different distinct memory states are provided by means for introducing one of two or more given amounts of charge into the floating gate for indeterminate storage until removed by electron erasure. The amount given corresponds to the distinct storage state. (A) The floating gate modulates conduction of some of the channels of the transistor. (C) an array of electrically erasable and programmable read-only memory cells having means for reading and erasing individual cells for programming, and for erasing their state, addressing means, each cell being a field effect transistor The transistor has a natural threshold voltage, which can be changed by applying a level of charge to the floating gate to select a valid one threshold voltage. Wherein said natural threshold voltage corresponds to a state of zero floating gate charge and is a method for programming a memory state of a cell in an addressed array, comprising: a plurality of effective threshold voltages; In the step of determining the voltage, the plurality of levels are greater than two, which is the number of more than two detectable individual cells. Erasing a cell by lowering its threshold voltage to a base level, the base level being the state of a plurality of detectable cells, the state increasing the charge of the floating gate, corresponding to the state Programming the cell to its plurality of states, wherein the effective threshold voltage is less than the lowest of the plurality of effective threshold voltages. This is done by adding a negative charge to the floating gate until it is substantially equal. (D) the method of (c), comprising establishing a plurality of valid threshold voltages, and establishing at least four such voltage levels, wherein the cell comprises at least two bits of information; Can be accumulated. (E) the method of (d), wherein the threshold voltage level is established; and at least two of a voltage lower than the natural threshold voltage of the cell transistor.
And selecting one of the two voltages. (F) programming the cell to one of the plurality of threshold voltage levels, sending a pulse to the cell with a short programming pulse, and applying the programming pulse; After that, alternately read the current flowing there,
It continues until the level of the current is at the desired one of the plurality of effective threshold voltages, the short program pulse having a threshold voltage that is half the difference between the two threshold voltages. Are short enough to change the program pulse. (G) In the method according to (c), the step of erasing the cell includes pulsing the cell with an erasing pulse;
Read the current flowing through it and continue until it reaches the desired base threshold voltage, the magnitude and duration of each erase pulse being such that the first erase pulse is insufficient to completely erase the cell. Yes, and the subsequent erase pulse is raised by a defined amount until the cell is completely erased. (G) The method according to (g), further comprising adding a counter to one after the cell is completely erased to the base threshold level, and monitoring the number of times the cell has been erased. It is a thing. (G) In the method described in (g), the step of erasing the cell includes the step of stopping the generation of the erasing pulse when the number of erasing pulses exceeds a predetermined number of pulses. (K) read and program individual cells,
An array of electrically erasable and programmable read-only memory cells having means for addressing to erase that state, each cell having a field effect transistor,
The transistor has a natural threshold voltage,
The threshold voltage can be changed by applying a level of charge to the floating gate to select a valid one threshold voltage, and the natural threshold voltage is such that the floating gate charge is zero. Wherein the first and second memory states correspond to first and second valid threshold levels, respectively, and address the addressed cells of the array with the first or second memory cells. A method for programming to the state 2 includes the following steps. The addressed cell is pulsed for a predetermined time and voltage to change the charge on its floating gate and change its threshold voltage, the threshold voltage being the first and second threshold voltages. Effective threshold voltage 1
/ 2 is not enough to change / 2 and then read the current through the cell to determine if the self-threshold voltage has reached the new desired first or second state. And the pulse generation is repeated, and the addressed cell has the desired first
Or until the second memory state is reached, at which point the programming of the addressed cell of that cell is complete. (C) Addressing the cell for programming, reading and erasing its state. An array of a plurality of such electrically erasable and programmable read-only memory cells having means for controlling the level of charge on the floating gate to obtain an effective threshold voltage. A cell of an addressed array for such an array having a field effect transistor having a variable natural threshold voltage, said natural threshold voltage corresponding to a zero charge on the floating gate. A method for erasing a group of memory states, wherein said addressed cells are stored for a predetermined time. Pulsing the cells with a voltage that can change the threshold voltage, but not completely erase the cells, and then reduce the current flowing through the addressed cells to their changed threshold levels And the step of reading the pulse are repeated a plurality of times, and the repetition step of increasing the voltage by a fixed amount from the last pulse step each time the pulse step is repeated. (B) The memory erasing method according to (b), further including an additional step of storing a count equal to the total number of times the cell has been erased. (S) In the memory erasing method according to (S), each of the repeated steps of the pulse application and the reading is terminated when any of the following conditions first occurs. The respective thresholds have reached the erased state, that a predetermined number of erase pulses have been applied, that the maximum voltage of the predetermined erase pulse has been reached, or that the addressed cell has When the number of non-erasable items falls below a predetermined acceptable number of erasures. (E) electrically erasable and programmable read-only memory cells, each cell including a channel-separated field effect transistor, wherein the transistor is a source and drain region separated by a channel region in a semiconductor substrate; A transistor having a floating gate insulated from and located on a channel region adjacent to the drain, a control gate provided on and insulated from the floating gate, and another portion of the channel adjacent to the source Wherein the transistor has a first portion with a natural threshold voltage that can controllably change the level of charge on the floating gate to obtain an effective threshold voltage, wherein the natural threshold voltage is applied to the transistor. Value voltage is floating Corresponding to the case where the charge of the gate is equal to 0, wherein the conductance of the first transistor portion is determined by the voltage of the control gate and the level of the charge of the floating gate,
And the transistor has a second portion in series with the first portion, which has a conductivity determined by the charge on the control gate and erases the storage state of the cells in the array. , A system for programming and reading includes means for connecting one or a group of memory cells selected for addressing said array, and means for connecting said array for erasing. And moving the effective threshold voltage of the addressed cell or group of cells to a base level by moving the charge on the floating gate of each cell in a positive direction, wherein the floating of the addressed cell Programming means connected to the array to apply a negative charge to the gate;
This is done substantially until one of the above effective threshold voltages is reached, whereby each cell of the array is programmed to a state corresponding to one of the two or more states and the current flowing through the addressed cell Read means connected to the array and means for detecting individual currents corresponding to a number corresponding to a valid threshold voltage level, thereby providing an address. Determine the state of the measured current level of the measured cell. (G) In the erasing, programming, and reading system of the memory array according to (g), the array of memory cells has a common connection between control gates of a row of memory cells, and the program means includes a common connection between cells of the row. Means for applying said first tall voltage to a connection;
Means for applying said second high voltage to the drains of memory cells included in said rows that do not reach a particular effective voltage level to be programmed which is desired for them. A read-only memory system that can be electrically erased and programmed, comprising: a semiconductor substrate including an array of a plurality of storage cells in rows and columns, each cell including a transistor, the transistor comprising: It has a source region and a drain region including the following, and a channel region provided therebetween. Having a floating gate, the charge of which affects the level of conduction between the source and the drain; and the control gate, whose voltage affects the level of conduction between the source and drain, a column means is applied to the source and drain of the cell. Connectable to an addressed column of the storage cell transistors to control a voltage. Column means connectable to the addressed row of the cell transistors and control the voltage at the control gate of the cell; program means responsive to the address of a particular cell, a voltage applied to the cells addressed to the row means and the column means. To reduce the conductance of the addressed cell transistor by increasing the charge on its floating gate by applying a voltage to the source and drain connections of the addressed column. State by detecting the level of current flowing between the drain and source of the addressed cell by increasing the voltage level of the control gate of the addressed row by applying a voltage to the column means as well. Erasing means connected to the storage cells of the array Removing the charge from the floating gate of a plurality of storage cell transistors includes the following improvements in the system: the reading means includes means for distinguishing between two current ranges of the addressed cell, whereby each cell The program means having corresponding two or more states has means corresponding to the reading means, and supplies a program voltage to the cells addressed to the row means and the column means, and flows to the addressed cells. The charge on the floating gate is increased until the read current is in one of two current ranges. (H) The improved memory system according to (g) includes means for counting and storing the number of times the plurality of storage transistor cells have been erased. (X) In the improved memory system according to (x), the reading means additionally has at least one sense amplifier, the sense amplifier being connectable to the drain of the addressed cell, whereby The above reference levels are provided by the operational sense amplifier, thereby providing more than one programmable conductance level to each addressed cell. (E) In the improved memory system of (ta), the erasing means has improved means selected for the row means and the column means, and provides an erasing voltage and a short erasing pulse, and then a cell current. The initial erase voltage is selected to be insufficient to a level that can completely erase the cell, and the pulse amount is gradually increased from the pulse to the pulse. Level, so that the cell is completely erased. (G) In the improved memory system according to (g), the erasing means continues the erasing cycle until the first occurrence of any one of the following conditions. The erased base level has been reached, or a predetermined number of erase pulses have been supplied, or a predetermined maximum voltage of the erase pulse has been reached, or a complete The number of non-erased cells below a predetermined, non-erasable, but acceptable number. (N) In the improved memory system according to (T), the floating gate of the transistor is:
The conductance level of the first portion of the channel between the source and drain regions is affected, and the level of conductance of the second portion of the channel between the source and drain regions is determined by the voltage of the control gate. Further, other additional objects, advantages of the present invention, and preferred embodiments are described with reference to the accompanying drawings.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to FIG. 1, a channel separation type Eprom or EEp
A rom cell structure is shown, which is suitable for the improved memory array and its operation according to the present invention. The semiconductor substrate 11 has a source region 13 and a drain 15
Which are usually formed by ion implantation. Channel region 1 between source and drain
7 are provided. A floating gate 19 is provided above the portion of the channel region labeled L1 and is separated from the substrate by a thin gate oxide 21. A control gate 23 is formed in an upper portion of the channel region where L2 is attached, and is separated from the substrate 11 by a thin gate oxide layer 25. Control 23 is also floating gate 1
9 are electrically separated from each other by an oxide layer 27. The amount of charge on floating gate 19 is programmed to correspond to the desired state to be stored in the cell. If the level of this charge exceeds a predetermined threshold, the cell is considered to be in one state. If it is below that threshold,
It is defined as being in another state. The desired level of charge is achieved by applying electrons from the substrate 11 to the floating gate 19 by applying an appropriate combination of voltages to the source, drain, substrate and control gate for a fixed period of time.
The desired charge is programmed. The floating gate is confined within one memory cell, and the gate is electrically isolated from all other parts of the structure. On the other hand, the control gate 23 extends over many cells and functions as a common word line. As will be mentioned hereinafter, the channel-separated type provides the same function as two field-effect transistors connected in series, one of which has the floating gate 19 as its control gate and the other has the control gate. The gate 23 is used as the control gate.

The primitive channel-separated Eprom or EEProm shown in FIG. 1 has a flash E by adding an erase gate (not shown).
It becomes an Eprom device. The erase gate is a separate electrode located near the floating gate 27 and separated therefrom by a tunnel dielectric. When appropriate voltages are applied to the source, drain, substrate, control gate, and erase gate, the amount of charge on the floating gate is reduced. Since one erase gate extends over many memory cells, they are erased at the same time, if not the entire array. In one prior art flash EEprom cell, the source or drain diffusion region provided under the floating gate is used as an erase electrode, while in other cells the erase electrode is the same as the layer as the control gate. Layers or separated conductive layers.

[Multi-State Storage] The channel separation type flash EEprom device has a two-state memory as shown in FIG.
It can be regarded as a composite transistor composed of two transistors T1 and T2 connected in series. The transistor T1 is a floating gate transistor having an effective channel length L1 and a variable threshold voltage _VT1 . Transistor T2 is a transistor having a fixed (enhancement) threshold voltage V _T2 and an effective channel length L2. The curve (a) of FIG. 3 shows the program characteristics of the Eprom of the synthetic transistor. The programmed threshold voltage V _tx is plotted as a function of time t when program conditions are given. These program conditions typically include V _CG = 12V, V _D = 9V, V _S =
V _BB = 0V. When either V _CG or V _D is at 0 V, no programming (unprogrammed, unerased) device will have a V _T1 of +1.5 V
V _T2 has + 1.0V. After approximately 100 milliseconds of programming, the device operates with a threshold voltage V _tx ≧ + 6.0.
Reaches V. This indicates an off ("0") state. This is because the composite device does not conduct at V _CG = + 5.0V. Conventional devices use a so-called "intelligent programming" algorithm. This provides a programming pulse that typically lasts from 100 microseconds to 1 millisecond,
Subsequently, a detection (reading) operation is performed. The pulse continues to be applied until it is detected that the device has turned off altogether, and then three extra programming pulses are provided to verify that the programmability is assured. In Flash EEprom device channel separation type of the prior art, sufficient voltage V _ERASE and erases a single pulse of sufficient duration, V _T1 is V _T2 (curve in FIG. 3 (b)) erase voltages below Check if it was done. The floating gate transistor keeps erasing until it is erased by the depletion mode operation (line (c) in FIG. 3).
The presence of the series transistor T2 obscures this depletion threshold voltage. Therefore,
The state erased to the (“1”) state corresponds to the threshold voltage V _tx =
V _T2 = + 1.0V. The memory storage “window” is ΔV = V _tx (“0”) − V
_tx (“1”) = 6.0−1.0 = 5.0V. However, the true storage window should be represented by the full swing of V _tx of transistor T1. For example, if transistor T1 was erased to a depletion threshold voltage V _T1 = −3.0V, the true window would be ΔV = 6.0V−
(-3.0) = 9.0V. None of the prior art flash EEprom devices utilize this true storage window. In fact, those of the prior art show that the operation of the device in the area (the area shown as hatched area D in FIG. 3), here where V _T1 is lower than V _T2, Ignored.

The present invention first proposes a plan that makes use of the features of this full storage window. This allows for more than two binary states of storage by using a wider storage window, and consequently more than one bit per cell. For example, one cell can store 4 instead of 2, and this state has the following threshold voltage. State "3": and _{-V T1 = -3.0V, V T2 =} + 1.0V ( highest conduction to that state) = 1,1. State “2”: −V _T1 = −0.5 V, V _T2 = + 1.0 V (intermediate conduction) = 1, 0. State "1": the _{-V T1 = + 2.0V, V T2} = + 1.0V ( lower conduction) = 0. State "0": and _{-V T1 = + 4.5V, V T2} = + 1.0V ( non-conductive) = 0,0. To detect any of these four conditions, the control gate is raised to V _CG = + 5.0V. Then, the source / drain current I _DS is detected via the composite device. For all four threshold states, V _T2 = +
Since it is 1.0 V, transistor T2 behaves simply as a series resistor. The conduction currents I _DS corresponding to the four states of the synthesis transistor are shown in FIG. 4 as a function of V _CG . The current sense amplifier can easily distinguish between these four conduction states. The number of possible states in practice is affected by the sensitivity of the noise of the sense amplifier and the loss of charge over the expected time course as the temperature rises. Eight identifiable conduction states are required for storing three bits per cell, and sixteen identifiable conduction states are required for storing four bits per cell. For multi-state storage cells, a ROM (read only memory) and a DR
It has been proposed in connection with AM (dynamic random access memory). In a ROM, one can have one of several fixed conduction states by creating two or more permanent threshold voltages by performing different channel ion implantations. Prior art multi-stage DRAM cells have been proposed, where each cell of the array is physically identical to the other cells. However, the charge stored in the capacitors of each cell is quantized, resulting in several different read signal levels.
For such prior art multi-stage DRAM storage, see IEE's Journal Solid State
Circuits (IEEE Journal of Solid-State Circuits),
M. on page 27 of 1988. A paper by M. Horiguchi et al., “A large-capacity semiconductor file memory using 16 levels of cell storage” (“An Experimental Large-
CapacitySemiconductor File Memory Using 16-Levels /
Cell Storage "), a second example of a multi-stage DRAM is at the IEE Custom Integrated Circuits Conference,
"Experiment on DRAM with 2-bit storage per cell for macrocell or logical storage applications" by T. Furuyama et al.
(“An Experimental 2-Bit / Cell Storage DRAM for Ma
crocellor Mem-ory-on-Logic Applications ”).

In order to make effective use of multi-stage storage in Eprom, it is necessary for the algorithm of the program of the device to allow any one of several conduction states to be programmed. First, "3" state (in this example + 3.0 V) of the need to be able to erase until a negative voltage V _T1 more than. The device is then programmed with a short program pulse (typically a pulse having a duration of 1 to 10 microseconds). The programming condition is that one pulse does not shift the effect of exceeding the threshold difference between the two states following the device threshold by more than half. In the device, the conduction current I _DS and i (i = 0, 1, 2, 3) of the reference power supply I _REF correspond to a desired conduction state (in order to correspond to four states, four reference levels are used). Is required) and the current is compared. The programming pulse is sustained (dashed line in FIG. 4) until the sensed current (solid line in FIG. 4) is slightly below the reference current corresponding to the four desired situations. Each programming pulse to better illustrate this point rises to V _tx with linearly 200 millivolts. And further assume that the device is initially erased by V _T1 = −3.2V. Then the required programming / sensing pulses are as follows: (V _T1 = −3.0 V) for state “3” Number of pulses = (3.2−3.0) /. 2 = 1 (V _T1 = −0.5 V) for state “2” Number of pulses = (3.2−0.5) /. 2 = 14 For state “1” (V _T1 = + 2.0 V) Number of pulses = (3.2 − (− 2.0)) /. 2 = 26 For state “0” (V _T1 = + 4.5 V) Number of pulses = (3.2 − (− 4.5)) /. 2 = 39 As a practical matter, V _tx is not linear with time. This is shown in curve (a) of FIG. as a result,
More pulses are required than indicated in state "1" or "0". If 2 microseconds is the width of the programming pulse and 0.1 microseconds is the time required for detection, then the maximum time required to program the device to any of the four states is It is approximately 39 × 2 + 39 × 0.1 = 81.9 microseconds. This is less than the time required by prior art devices "intelligent programming algorithms". In fact, in the new programming algorithm only a carefully measured group of electrons is injected during the program. Yet another advantage of this approach is that sensing when reading is the same sensing as when programming. And the same reference current source can be used for both programming and reading operations. This means
That is, all memories in the array can be programmed and sensed with the same reference level. This provides good tracking even in very large arrays of memory. Larger memory systems typically have built-in error detection and correction procedures, which are designed to address a small number of hardware defects, such as cells that respond badly to flash. Designed to withstand. For this reason, after a certain amount of the maximum number of program cycles has been performed, even when there is an indication that the memory cell is malfunctioning without the cell being programmed to the desired threshold. The algorithm of the programming and sensing cycle can be stopped automatically.

However, the EEprom transistor array
Some of the concepts of multi-state memory exist in connection with
You. An example of such a circuit is shown in FIG. This time
In one circuit, one array of memory cells is decoded.
Word line and decoded bit line
Each has a row and column cell control gate.
And drain and drain, respectively. Each bit line
The reading and programming or erasing times are usually 1.
It is pre-charged to a voltage between 0V and 2.0V.
Four sense amplifiers are fixed for each of the four stages of accumulation.
I at a certain reference level_REF 0, I_REF 1, I_REF 2, I
_REF 3 for the decoded output of each bit line.
Have a reference voltage. During the reading period,
The current flowing through the flash EEprom transistor is
Are compared (in parallel) with these four reference levels
You. This operation is similar for four consecutive reading periods.
(That is, they have one detection amplifier,
Ensure references apply to each cycle
It can be executed by If for read
Useful when additional time is not a problem
It is. ) Is also performed. The data output has four checks.
Four Di buffers (D0, D1, D
2 and D3). 4 days during the program
Data inputs Ii (I0, I1, I2 and I3) are provided to a comparison circuit.
The output of the four sensor amplifiers is also provided to the comparison circuit.
Power is supplied for the accessed cell. Also
If Di and Ii match, then
Is in the correct state and programming is not necessary.
You. However, if all four Dis are all
If the four Ii do not match, the output of the comparator is
Activate the gram control circuit. This circuit is a bit
Line (VPBL) and word line (VPWL) professional
Control the gram pulse generator. One short program
A switching pulse is applied to the selected word line and the selected bit.
Supplied to both trains. This is because Di and Ii
Second reading cycle to determine if
Obeyed by This sequence is a multiple program
And read pulses, repeated until they match
(Or, at the beginning, if there was no match,
Later, when the preset maximum number of pulses is reached
Stopped). Al of such multi-stage programming
As a result of the algorithm, each cell has four reference states
Communication state I_REF , I directly.
In fact, the same sense amplifier generates program and read pulses
Used during the detection period (normal reading
Period). This is the reference level (Figure 4
(Dashed line) and the programmed conduction level (solid line in FIG. 4)
Very large operation in large memory arrays during
Excellent tracking is allowed within the temperature range. Add
At the same time, carefully measured electrons are pushed to the floating gate.
Injected during the period of programming or erasing,
The device is minimal because it can be removed from it.
Amount of stress that can be tolerated. fact,
Four reference levels and four sense amplifiers connect the cell to four
It is used to bring one of them into conduction,
Simply 3 sense amplifiers and 3 reference levels with 4 accumulations
Necessary to detect the correct condition of one of the articles
You. For example, in FIG. _REF (“2”) is conductive
Discriminated correctly between "3" and "2", I_REF 
(“1”) is the correct difference between conduction states “2” and “1”.
Can be separated and I_REF (“0”) is the conduction state “1”
It is correctly discriminated between "0". Realistic of the circuit of FIG.
In a simple configuration, the reference level I_REF , I (i = 0, 1,
2) the lower and more corresponding them in that period
Their center point to detect the conduction state of the high cells
May be moved so as to be closer to each other. In the circuit of FIG.
The same principles used were used for two stages of storage or one cell.
Also applies to those that take four or more states
Please be careful. Of course, circuits other than those shown in FIG.
This is also possible. For example, the continuity level
This is not the same as sensing, but rather voltage level sensing.
Available.

[Improvement of Charge Retention] In the above-described example, states "3" and "2" are the result of positive charges in the floating gate, whereas states "1" and "0" are This is due to negative charges (electrons) on the floating gate (see FIG. 8). Life of this device (can be specified as 10 years at 125 ° C)
To detect the correct conduction state suitability during the 2 in substantially the V _T2 The charge from the floating gate
It is necessary not to leak more than the equivalent of the 00 millivolt shift. This condition is for stored electrons,
Epr in this example or any prior art
om or flash EEprom. Due to the physical considerations of the device, the retention of holes trapped in the floating gate should be distinctly better than the retention of trapped electrons. This is because the trapped holes are neutralized only when electrons are injected into the floating gate. Without the injection described above, it is almost impossible for holes to overcome the electric field barrier at the silicon-silicon dioxide interface of about 5.0 electron volts (the electric field barrier of trapped electrons is 3.1V). Therefore, improving the retention of this device can be improved by using the area where the holes captured in conduction are relevant. For example, in state "1", V _T1 is +2.0 V, which is associated with trapped electrons, and in a virgin device, V _T1 is 1.5.
V. However, in the virgin device, its V _T1
With a higher threshold voltage, eg, V _T1 = + 3.0V
If one increases (by increasing the p-type doping concentration of the channel region), the same state "1" is V _T1
= + 2.0V, and will be performed by the captured holes. This value of V _T1 will provide better retention. Of course, it is also possible to the reference level most or all of the state set a reference voltage to have a value of lower V _T1 than V _T1 of the virgin device.

[Erase of Information for Improved Endurance]
The endurance of flash EEprom devices is their ability to resist a given number of write and erase cycles. A physical phenomenon that limits the durability of prior art flash EEprom devices is that electrons are trapped in the active dielectric film of the device. The dielectric element used during programming captures some of the injected electrons during thermionic channel injection. During the erase, the tunnel erase dielectric also captures some of the tunnel electrons. Since the captured electrons will resist the applied electric field in the subsequent erase cycle,
This causes a decrease in threshold voltage and a shift in V _tx . This can be observed as a progressive closing of the voltage window between the "0" and "1" states (see FIG. 5).
Beyond approximately 1 × 10 ⁴ program erase cycles, the degree of closing of the window is such that the detection circuit may malfunction. If this cycle is continued, the device will experience a critical collapse phenomenon due to dielectric damage and decay. This typically occurs between 1 × 10 ⁶ and 1 × 10 ⁷ cycles. And it is known as breakdown due to impurities in this device. In the prior art memory device, the practical limit of how to close the window is approximately 1 × 10 ⁴ cycles. At a given erase voltage V _ERASE , the time required to fully erase the device can reach from the original 100 milliseconds (ie, in a virgin device) to 10 seconds in a device performed 1 × 10 ⁴ times. . The quality degradation in such prior art flash EEprom devices is 1
In order to allow a sufficient erasure after × 10 ⁴ times or more, an extremely long erasing pulse time had to be specified. However, this was excessive erasure in the virgin device, resulting in unnecessary excessive distortion. A second problem with prior art devices was that the tunnel dielectric was exposed to unnecessarily high peak stress during the erase pulse. This is because the state “0” (V _T1
= + 4.5V or higher). This device has a large negative charge Q. V _{ERAS
When E is applied, the tunnel dielectric is} instantaneously exposed to a sharp electric field due to the influence of Q, as in _VERASE . This peak electric field gradually decreases when the charge Q changes to 0 in the tunnel erasing process. Nevertheless, permanent and cumulative damage is added in the course of this erasure. This results in premature device collapse. To overcome the two problems of overstress and window closing, a new erasure algorithm has been disclosed. It is applicable to any of the preceding flash EEproms.
If it were not for such an algorithm of a new erasure, if V _T1 conductive state from the curve (b) in that FIG. 5 for realizing the apparatus for a multi-state _is more negative than _VT2, 1 × 10
It will be erased in ⁴ to 1 × 10 ⁵ write / erase cycles.

FIG. 7 shows the main steps of the new erasure algorithm. Assume that a block array of m × n memory cells has been completely erased by flash erase to state “3”, which is the state of highest V _T1 with the highest conductivity. Certain parameters are set in connection with the erasure algorithm. They are listed in FIG. 7, where V ₁ is the erase voltage of the first erase pulse. V ₁ is probably less than 5V from the erase voltage required to erase the virgin to state “3” with an erase pulse of 1 second. t is approximately 1/1 of the time required to completely erase the virgin device to state "3"
Selected as 0. Typically, V ₁ is between from 10V to 20V, whereas t is between 10 and 100 ms. The algorithm assumes a small number X of bad bits that the system can withstand (this system level is determined in the process of error detection and correction as an example. Without any error detection and correction, In that case, X = 0). These are bits that are shorted or very leaky tunnel dielectrics that are not erased by applying a sufficiently long erase pulse. To prevent excessive erasure, the total number of erase pulses can be limited to a preset n _max in the erase cycle of all blocks. ΔV is the voltage by which the subsequent erase pulse is boosted. Typically, ΔV is between 0.25V and 1.0V. As an example, if V ₁ = 15.
If ΔV = 1.0 V at 0 V, then the seventh erase pulse has a magnitude of V _ERASE = 21.0 V and a duration of t. One cell is considered completely erased. That is, when the conductance of the reading becomes greater than I _"3" . The number S of complete erase cycles experienced by each block is very important information at the system level. If for each block, S is known, if the S has reached a 1 × 10 ⁶ (or other set number) program erase cycle, those elements are automatically replaced with a new auxiliary Can be replaced with a generic block. S is initially set to 0, and is incremented sequentially for each complete block erase multiple pulse cycles. As the value of S, for example, 20 bits (2 ²⁰ corresponds to approximately 1 × 10 ⁶ ) can be prepared and accumulated in each block for each time. In that way, each block can maintain its own durable record. Alternatively, the S can be stored in a system remote from the chip.

The sequence of the complete erase cycle of the new algorithm is as follows (see FIG. 7). Read S. This value can be stored in a register file. (This step can be omitted if S is not expected to reach that limit during the operating life of the device). 1a. First erase pulse V _ERASE = V ₁ + nΔV, n =
Apply 0, pulse duration = t. Although this pulse (and the next few consecutive pulses) is sufficient to erase all memory cells, it will reduce the charge Q of the programmed cell, which is a relatively low erase field. It is stress. That is, it is 1
This is equivalent to two "condition making" pulses. 1b. Read the sparse patterns in the array. A diagonal reading pattern would read, for example, m + n cells (rather than a complete reading by m × n), and retrieve at least one cell from each row, and one cell from each column It will be. The number N and X of the cells that have not been completely erased by the state “3” are compared. 1c. If N is x (not fully erased array)
If so, the second erase pulse is larger than the first pulse by ΔV and a second erase pulse having the same duration t is applied. Read diagonal cells, count N.
In this erasing cycle, the erasing pulse of pulse / read / addition is continued until N ≦ X or the number n of erasing pulses exceeds _nmax . The first one of these two conditions leads to the final erase pulse. 2a. A final erase pulse is applied to confirm that the array has been completely and fully erased. The magnitude of V _ERASE is larger than the previous pulse by a fraction of ΔV. The duration can be between 1t and 5t. 2b. 100% of the array is read. The number N of cells that have not been completely erased is counted. If N is less than or equal to X, pulsing for erasure is completed at this point. 2c. If N is greater than X, then the address of the presence of the unerased bit N is generated. It is to exchange spare good bits at this system level. If N is significantly greater than X (if N equals 5% of all cells), flag such a case and let the user reach the limit of their patience and at the end of life Indicates that it has become. 2d. The pulse for erasing is terminated. 3a. One S is added. The new S is then saved for future reference. This step is optional. The new S is written into the newly erased block or stored in a register file separate from the chip. 3b. The erase cycle is terminated. A complete cycle is 10 to 20 erase pulses and is expected to be erased in about 1 second.

The new algorithm has the following features:
I have (A) Any cell in the array may have a sharp electric field strike.
I do not receive a reply. Time V _ERASE By relatively high power
Voltage and any charge Q from the floating gate
And has been removed by a previous low voltage erase. (B) The total erase time is the fixed V of the prior art._ERASE Pulse
It is much shorter than the one used. virgin
In the case of the device, the required erase time is the shortest pulse.
You. 1 × 10^Four Even devices that withstand more than cycles
Requires a voltage increase several times ΔV to overcome the trapped charge
Not done. And the charge trapped in the dielectric is
It only increases the total erase time by a few hundred milliseconds. (C) The window becomes narrower on the erase side (the curve in FIG. 5).
(B)) to infinity (the device cannot be used due to sudden destruction)
Until it becomes). If not, the equipment
Until the proper state “3” is erased._ERASE Is simply
It is because it is increased. New erasure algorithm
The system can save all storage windows.

FIG. 8 shows a flash EEpro according to the present invention.
4 shows the four conduction states of the m device as a function of the number of program erase times. All four states, always is possible to fix the reference conduction states by the program or erase is complete, in any state, not that at least 1 × 10 ⁶ cycles window until is narrowed. In a flash EEprom memory chip, a voltage increasing device that generates nΔV from a voltage V ₁ and a voltage increment ΔV required on the chip (or on another control chip) in order to effectively execute a new erase program; It is possible to provide a coefficient circuit for counting N and comparing it with a stored value X, a register for storing the address of the position of the defective bit, and a control and sequence circuit including an instruction for executing the aforementioned erase sequence. . What has been described in detail as embodiments of the present invention are preferred embodiments, and those skilled in the art will recognize many variations in this regard. Thus, the present invention is entitled to protection within the full scope of the appended claims.

[Brief description of the drawings]

FIG. 1. Channel-separated type Eprom or EEpro
m is a cross-sectional view of an example.

FIG. 2 is a schematic diagram showing a specific transistor representation for forming a channel-separated Eprom transistor.

FIG. 3 is a diagram showing characteristics of programming and erasing of a flash EEprom device of a channel separation type.

FIG. 4 shows a flash E of the channel separation type according to the present invention.
It is a figure showing four conduction states of an Eprom device.

FIG. 5 is a diagram showing a life characteristic of a program erase cycle of a conventional flash EEprom device.

FIG. 6 is a diagram showing a circuit diagram and a program write voltage pulse required in the multi-stage storage device.

FIG. 7 is a schematic diagram showing a basic state in a new algorithm that can be erased with minimum stress.

FIG. 8 is a diagram showing a program erase cycle life characteristic of a channel separation type flash EEprom device using a multi-step program and an information algorithm for reducing stress at the time of erase.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 Substrate 13 Source region 15 Drain region 17 Channel region 19 Floating gate 21 Gate oxide 23 Control gate

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 27/115 G11C 17/00 611A 29/788 612B 29/792 601B H01L 27/10 434 29/78 371F Terms (reference) 5B025 AA01 AC02 AD04 AD08 AD13 AE01 5F083 EP02 EP26 EP27 ER22 ZA21 5F101 BA02 BB04 BD22 BD23 BE05 BE07 BF05 5L106 AA10 BB01 BB12 CC01 CC11 CC17 CC21 CC32 GG05

Claims (3)

[Claims] An array of memory cells is divided into blocks of cells, said memory cells comprising field effect transistors having threshold voltage levels that are variable according to the amount of charge stored therein. A method of operation for an array of electrically changeable memory cells, each including: establishing more than two effective threshold voltage levels corresponding to more than two detectable states in an individual cell. Changing the amount of charge stored in the at least one addressed cell until the threshold voltage of the at least one addressed cell becomes equal to one of the plurality of effective threshold voltage levels from a starting level Before at least one addressed cell in the block, wherein the state of the addressed cell is set to one of the plurality of states Setting an effective threshold voltage level, the step moving the effective threshold voltage level of the addressed cell from a starting level toward one of the plurality of threshold voltage levels. Applying a given voltage for a predetermined amount of time sufficient to determine whether the effective threshold voltage of the addressed cell has reached one of the plurality of threshold voltage levels. Reading an electrical parameter of the addressed cell to determine an effective threshold voltage of the addressed cell is set to one of the plurality of threshold voltage levels. Repeating the voltage application and reading; and counting a count equal to the total number of times each block of cells has been reset to the starting level. Accumulating the counts in the individual blocks involved; and replacing each of the auxiliary blocks with one of the individual blocks in response to a count of each individual of the blocks exceeding a set number Providing an auxiliary block of at least one memory cell; and reading the state of said plurality of memory cells with the aid of an error correction scheme. 2. The method of claim 2, wherein the establishing comprises at least four steps.
2. The method according to claim 1, wherein the method has two threshold voltages. 3. The method of claim 1, wherein at least two of the plurality of threshold voltage levels greater than two are derived from the net positive charge of the individual cell.