JP2002315384A - Driver of two-phase brushless motor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a drive control technology of a two-phase brushless motor, in which noise can be suppressed by limiting the r.p.m. of the motor through duty control, without lowering the driving efficiency. SOLUTION: Among a first counter for measuring the rotational period of a rotor by counting the clock signals, and second and third counters for counting the count of the first counter with a clock of a different frequency, rising of a duty control pulse is determined by the output from a counter operating with a clock of higher frequency, and falling of the duty control pulse is determined by the output from a counter operating with a clock of lower frequency.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a drive control technique for a two-phase brushless motor, and more particularly to a technique effective when applied to a duty control system for limiting a rotation speed.

[0002]

2. Description of the Related Art FIGS. 1 and 2 are schematic diagrams showing two different types of conventional two-phase half-wave drive brushless motors. FIG. 1 shows a state in which one wire is wound around a stator core, the starting end is a terminal for supplying a driving current of the first field coil phase φ1, the end is a terminal for supplying a driving current of the second field coil phase φ2, To the common terminal C connected to the power supply voltage Vcc.
1 shows a so-called single-wire winding type motor as an OMM.

In FIG. 2, two wires are simultaneously wound around a core, and opposite ends of each winding are connected to supply terminals of a first field coil phase φ1 and a second field coil phase φ2, respectively. And a so-called bifilar winding type in which the other end is a common terminal COMM to which the power supply voltage Vcc is applied. 1 and 2, 1 is a rotor magnet, 2 is a stator core, 3 is a winding of the first field coil phase φ1, 4 is a winding of the second field coil phase φ2, and 5 is a rotor position. This is a detection Hall element.

[0004] The two-phase half-wave drive brushless motor as described above is economical due to its simple structure, and is frequently used as a cooling fan motor for a main body of a personal computer, a CPU, and other OA equipment.

[0005] Incidentally, it is desired that the cooling fan of the OA equipment has low noise from the usage environment. Therefore, instead of rotating the motor at full speed,
Some personal computers and other OA equipment monitor the temperature inside the equipment and perform control to limit the rotation speed of the cooling fan motor when the temperature is not so high. Conventionally, as a technique for limiting the rotation speed of such a two-phase brushless motor, a technique for controlling the duty of a pulse current flowing through a stator coil is known. Hereinafter, this duty control will be described with reference to FIG.
This will be described with reference to FIG.

FIG. 3 shows a configuration example of a drive circuit of a conventional two-phase half-wave drive brushless motor. 12 is a Hall bias circuit for supplying a bias current to the Hall element 5 for detecting the position of the rotor, 13 is a Hall amplifier with hysteresis for amplifying the output signal of the Hall element 5 and converting it to a binary signal,
14 is a control logic circuit for controlling the on / off of the output transistors Q1 and Q2 based on the output of the Hall amplifier 13, 15 is a duty control circuit for limiting the rotational speed, and 16 is preventing the stator coil from being burned out due to the rotor restraining current. Circuit that protects the chip from abnormal temperature rise when the drive circuit is composed of a monolithic IC, ZD
1, ZD2 is a Zener diode for output voltage clamp,
φ1 and φ2 indicate stator windings, and C1 and C2 indicate capacities used as needed for noise reduction.

FIG. 4 shows an example of an operation timing chart of the conventional motor drive circuit shown in FIG. From above, the input signal of the Hall amplifier 13, that is, the output signal of the Hall element 5,
Rotor rotation signal (output signal of hall amplifier 13), sawtooth signal generated in synchronization with rotation signal, DC voltage for setting duty, duty control output signal, winding φ1 during motor rotation drive Output voltage (collector voltage of output transistor Q1), output voltage of winding φ2 (Q
2 collector voltage).

The drive circuit shown in FIG. 3 integrates the rotation signal shown in FIG. 4B to generate a saw-tooth wave signal as shown in FIG. 4C and outputs the signal to a reference voltage (eg, ground potential) by a comparator. By comparison, a duty control output signal as shown in FIG. 4 (D) is generated, and when the duty control output signal is in a low level range, the output transistors Q1 and Q2 for driving either the φ1 or φ2 winding are made conductive. Instead, Q and Q2 are made conductive only during the period when the duty control output signal is at the high level. As a result, only the latter 50% of each half cycle of the Hall amplifier input conducts. In this drive control method, the duty decreases when the DC voltage for setting the duty (reference voltage by the comparator) increases, and when the DC voltage decreases, the duty increases.

[0009]

By the way, the above-mentioned conventional duty control technology does not seem to have any problem at first glance, but has three major problems. The first is the problem of driving efficiency. For example, in the case of control with a duty of 50%, there is no problem immediately after the start since the energization start point of the output transistor is a point where the maximum torque is obtained (back electromotive force is near the peak), but the back electromotive force at the end of energization is zero. No torque is generated even when the coil is energized. In addition, in the conventional method, when the duty is set to 50% or less, the energization start point is located after the point at which the maximum torque is obtained. Therefore, when the duty is 50% or less, the efficiency becomes worse as the duty is set smaller.

Second, the duty cannot be set unless the motor rotation speed at the duty to be set is known in advance. This is because the amplitude of the sawtooth wave signal cannot be determined unless the number of rotations is known. Therefore, the DC voltage cannot be set. That is, the number of revolutions is known in advance 50
%, But it is necessary to take measures such as switching the DC voltage or the charging current of the capacity by setting the rotation at that time by an experiment in advance in order to set it to any other duty. It is extremely troublesome in design.

Third, there is a variation in duty and a variation in temperature due to variations in circuit components and temperature dependence of elements. For example, when the value of the capacitance for creating the sawtooth wave becomes larger than the set value, the peak value of the sawtooth wave decreases, and the duty becomes smaller than the set value. In addition, it is necessary to use high-precision components in order to suppress variations, which increases the cost of the system.

SUMMARY OF THE INVENTION An object of the present invention is to provide a drive control technique for a two-phase brushless motor that can reduce the noise by limiting the number of revolutions of the motor by duty control without lowering the drive efficiency.

Another object of the present invention is to provide a drive control technique for a two-phase brushless motor capable of controlling the rotation speed by changing the duty setting without previously examining the relationship between the duty and the rotation speed. To provide.

Still another object of the present invention is to provide a two-phase brushless motor capable of avoiding a variation in duty, that is, a rotation speed of the motor and a temperature dependence due to variations in circuit components and temperature dependence of elements. It is to provide a drive control technology.

[0015]

SUMMARY OF THE INVENTION In order to achieve the above object, the present invention provides a first counter for counting a clock signal and counting a rotation period of a rotor, and a counter for counting a count value of the counter using clocks having different frequencies. Second and third counting
The rising edge of the duty control pulse is determined by the output of the counter that counts with the higher frequency clock, and the falling edge of the duty control pulse is determined by the output of the counter that counts with the lower frequency clock. I did it.

More specifically, in a brushless motor driving device for rotating a motor by switching a current flowing through each phase winding of a brushless motor having a two-phase stator winding, a stator winding of each phase of the motor is provided. An output circuit for selectively energizing the wire, a rotation detecting means for detecting a rotational position of the rotor, a control circuit for controlling the output circuit based on a detection signal of the rotation detection circuit, and a control circuit for controlling the output circuit from the output circuit. A duty control circuit that determines a duty of a control pulse supplied to the first and second clock signals; and a clock generation circuit that generates a clock signal required by the control circuit and the duty control circuit. A first counter for counting the half cycle of a signal indicating the rotation of the rotor by counting Of the second and third counters that count with clocks of different frequencies, the rise of the duty control pulse is determined by the output of the counter that counts with the clock with the higher frequency, and counts with the clock with the lower frequency. The falling of the duty control pulse is determined by the output of the counter.

Thus, the duty control output can be output at the timing when the maximum torque is generated, so that the motor speed can be limited by the duty control without reducing the driving efficiency, and the noise can be reduced. In addition, since the duty is controlled using the counter, the set duty does not change unless the counter overflows.Therefore, the rotation speed after the duty control is roughly assumed in advance to prevent the counter from overflowing. As long as the rotation speed is not known, the duty can be set.

Preferably, the clock generation circuit divides a frequency of a reference clock signal to generate the first and second clock signals.
And a plurality of frequency dividers for generating a third clock signal, and among the plurality of clock signals generated by the clock generator, the first, second, and third clock signals as the first, second, and third clock signals. And a clock switching means for switching a clock supplied to the third counter, wherein the duty can be changed by switching the first, second, and third clock signals. Thereby, the rotation speed of the motor can be switched in a plurality of stages by switching the duty, and the switching can be performed very easily.

Note that the first counter may measure the half cycle of the signal indicating the rotation of the rotor every half cycle, but may perform it every half cycle until the next time is measured. The previous count value may be set in the second and third counters.

Further, the rotation detecting means may be a back electromotive force detection circuit for detecting a back electromotive force induced in a winding of a non-conducting phase among the windings, or a Hall element and an amplifier for amplifying the output thereof. A circuit may be used.

Further, the control circuit includes the first and second control circuits.
It is preferable to operate with a clock signal whose frequency is at least one digit higher than that of the third clock signal.
Thus, highly accurate duty control can be performed.

[0022]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below with reference to the drawings. FIG. 5 shows a configuration example of a duty control unit in a drive circuit of a two-phase half-wave drive brushless motor according to the present invention. In a motor drive circuit using a Hall element as the rotor rotational position detecting means, the configuration of the circuit other than the duty control unit is the same as that shown in FIG.
And may be the same as the motor drive circuit shown in FIG.

In FIG. 5, reference numeral 14 denotes a control logic for controlling an output transistor to energize a coil, and the control logic 14 is configured to operate in synchronization with a clock signal CLK0. CNT1 to CNT3 are counters for counting clocks CLK1, CLK2 and CLK3 supplied from a clock generation circuit (not shown), and clocks CLK1 and CLK counted by each counter.
2, CLK3 and the operation clock CLK0 of the control logic 14 are set such that f0≪f1 <f2 <f3, where the frequencies are f1, f2, f3, and f0.

Each of the counters CNT1 to CNT3 performs a counting operation in accordance with a control signal from the control logic 14. Among them, the counter CNT1 counts a high-level time, that is, a half cycle, by performing a high-level period counting operation of the rotor rotation signal R, which is an output signal of the hall amplifier 13. Each of the counters CNT2 and CNT3 counts down the count value of the counter CNT1, outputs a high-level signal during counting, and outputs a low-level signal when the count ends (the count value becomes 0). It is configured.

In this embodiment, there is provided an AND gate 20 for calculating the logical product of the outputs of the counters CNT2 and CNT3. The output of the ADN gate 20 is supplied to the control logic 14 as a duty control signal DTC, Reference numeral 14 controls the output transistor according to the duty control signal. In this embodiment, the rotation period of the rotor by the counter CNT1 is measured every half cycle, and the count value is down-counted by the counters CNT2 and CNT3 in the next half cycle. It may be performed not at every half cycle but at an arbitrary cycle.

Next, the operation of the motor drive circuit to which the duty control circuit of FIG. 5 is applied will be described. FIG. 6 shows a timing chart in the case where the duty control circuit of FIG. 5 is applied to a motor drive circuit using a Hall element as a rotor rotational position detecting means, in which a Hall amplifier input, a rotation signal (Hall amplifier output) R , The output voltages of the coils φ1 and φ2, the output of the counter CNT2, the output of the counter CNT3, and the duty control output DTC. In FIG. 5, when the duty control circuit of this embodiment is applied to a sensorless motor drive circuit using a back electromotive force detection circuit instead of a Hall element, the mask signal MSK indicates the output of the coils φ1 and φ2. Kickback KB that appears in voltage
(See FIG. 6) is a prohibition signal for preventing the back electromotive force detection circuit from detecting erroneously.

In this embodiment, the clocks CLK1, CLK
2, the duty ratio is determined by the ratio of the frequencies of CLK3. For example, to realize a duty of 50%, CLK1,
The frequency ratio between CLK2 and CLK3 is set to 3: 4: 12.

When the control logic 14 captures an arbitrary rising edge of the rotation signal R, it initializes and starts the counter CNT. The counter CNT1 counts only during a period when the rotation signal R is at a high level. Next, the control logic 14
When the falling edge of the rotation signal R is detected, the counter CN
The counting operation of T1 is stopped, the count value of the counter CNT1 is loaded into the counters CNT2 and CNT3, the counters CNT2 and CNT3 are started, and the counter CNT1 is initialized and restarted. The frequency of the clock CLK0 for operating the control logic 14 is the clock CL
Since it is sufficiently higher than any of K1 to CLK3, the time from when the falling edge of the rotation signal is captured to when the counter CNT1 is restarted is performed within a sufficiently short time compared to the period of the rotation signal.

The counters CNT2 and CNT3 are down counters. Since the frequency of the clocks CLK2 and CLK3 is higher than the frequency of CLK1, the counters CNT2 and CNT3 are not detected before a new edge of the rotation signal is captured except at the beginning of startup. And CNT3 end the count operation. Here, since the clock CLK3 is set to four times the frequency of CLK1, as the rotation of the motor approaches a steady state, the counter CNT3 sets the quarter period of the half period T1 (or T2) of the rotation signal as shown in FIG. Stop counting with 1. On the other hand, since the clock CLK2 has a frequency that is four-thirds the frequency of CLK1, the counter CNT2 ends counting in three-fourths of the half cycle T1 (or T2) of the rotation signal.

Here, if the conduction of the output transistor is inhibited while the output of the counter CNT3 is at the high level and while the output of the counter CNT2 is at the low level, the duty 5
It can be seen that 0% control becomes possible. This duty control state does not change unless the counter overflows. When the number of bits of the counter is limited in order to reduce the cost, the counter CNT may be used at the initial stage of the startup.
May overflow. Therefore, when the overflow is detected, the duty control output may be fixed at a high level.

FIG. 7 shows a schematic configuration when the present invention is applied to a so-called sensorless motor drive circuit. As shown in FIG. 7, in this embodiment, the coils φ1,
A B-emf detection circuit 17 for monitoring the output of φ2 and detecting the back electromotive force (B-emf) is provided. 21 is a clock generation circuit. In this example,
It is necessary to prepare a mask signal MSK so that the B-emf detection circuit 17 does not erroneously detect the kickback voltage KB.
The mask signal MSK can be configured to be generated by the control logic 14.

FIG. 8 shows a specific example of the B-emf detection circuit. φ1 and φ2 are stator windings, Q1 and Q2 are output transistors, ZD1 and ZD2 are zener diodes for voltage clamp, COMP3 and COMP4 are B-emf detection comparators, AS1 and AS2 are analog switches for masking, A1 and A2 are B MSK, a detection output of the emf detection comparator, indicates a mask signal supplied from the control logic 14 to the analog switches AS1 and AS2.

The above comparators COMP3, COMP4
The threshold voltage is set to Vcc. The comparators COMP3 and COMP4 have a hysteresis characteristic. Thereby, the analog switch AS
1 and AS2 are turned on, the input terminals of the B-emf detection comparator are set to the same level, and the detection outputs A1 and A2
Maintains the previous state while the analog switches AS1 and AS2 are on.

FIG. 9 is a timing chart of signals of various parts of the sensorless motor drive circuit of FIG. 7, and from the top, the output voltages of the coils φ1, φ2 and the detection output of the back electromotive force (B-emf) of the coils φ1, φ2. (Corresponding to a rotation signal), the output of the counter CNT2, the output of the counter CNT3, the duty control output DTC, and the mask signal MSK.

FIG. 9 shows a signal waveform when the frequency ratio of CLK1, CLK2 and CLK3 is set to 3: 4: 12 in order to realize a duty of 50% as an example. As in the embodiment of FIG. 5, depending on how to select the ratio of the frequencies of the clocks CLK1, CLK2, and CLK3 input to the three counters, it is possible to perform duty control using only the portion having the highest driving efficiency. Further, since the duty control output DTC is output at the timing when the maximum torque is generated, there is a characteristic that the drive efficiency is improved as the duty is reduced.

FIG. 10 shows a configuration example of a clock generation circuit that generates clocks CLK1, CLK2 and CLK3 input to the counter from the master clock. The clock CLK0 supplied to the control logic 14 is, for example, 1 MHz.
The master clock of z is used as it is. D1, D
Reference numerals 2, D3, D4, D5, and D6 denote frequency dividers, and the fraction indicates the frequency division ratio of each of the weekly circuits. K1 and K2 are clock changeover switches that can change over the clocks input to the counters CNT3 and CNT2. Clock CLK1 input to counter CNT1
Is fixed, and the master clock is divided by the frequency dividers D1 and D1.
Clocks sequentially divided by D2, D5 and D6, that is, 1
1.953 KH obtained by dividing MHz by 1/512
z. The output frequencies of the frequency dividers D2, D3, D4, and D5 are four times, 2.666 times, and 1.times.
When the clock CLK1 is 100%, the cycle is 25%, 37.5%, 75%, 50%.
%.

If the switch K1 is set to the "1" side (output selection of the frequency dividing circuit D2) and K2 is set to the "1" side (output selection of the frequency dividing circuit D4), the counter CNT3 stops counting. Is 25% of the rotation signal half cycle, and the counter CNT2 stops counting at the time of 75% of the rotation signal half cycle. Therefore, the output transistor is turned on for 25% to 75% of the rotation signal half cycle. In this case, the duty is 50%.

The switch K1 is left as it is (output selection of the frequency dividing circuit D2), and the switch K2 is set to the "0" side (frequency dividing circuit D5).
When the counter is set to (output selection), the count of the counter CNT2 ends at 50% of the half cycle of the rotation signal, and the output transistor becomes conductive from 25% to 50%.
% And the duty is set to 25%.

Conversely, if the switch K1 is set to the "0" side (output selection of the frequency dividing circuit D3) while the switch K2 is left as it is (output selection of the frequency dividing circuit D4), the counter CNT3 stops counting. At 37.5% of the half cycle of the rotation signal, the output transistor is turned on.
It is between 5% and 75% and the duty is set to 37.5%.

When the switch K1 is set to the "0" side (output selection of the frequency dividing circuit D3) and the switch K2 is set to the "0" side (output selection of the frequency dividing circuit D5), the counter CNT3 stops counting by the rotation signal. At the time of 37.5% of the half cycle, the counter CNT2 stops counting at the time of 50% of the half cycle of the rotation signal, and the output transistor can conduct only 3 times.
Between 7.5% and 50%, ie duty is 1
This is set to 2.5%.

As described above, when the circuit of FIG. 10 is applied,
By changing the combination of the clocks CLK1, CLK2 and CLK3, the duty can be set freely. In addition, since the start and end of the conduction of the output transistor can be freely set, duty control with the highest drive efficiency can be performed.

[0042]

According to the present invention, it is possible to perform duty control using only the portion having the highest drive efficiency and to increase the duty control output to the maximum torque, depending on how to select the frequency ratio of the clock input to the counter. Can be output at the timing of the occurrence of, so that there is an advantage that as the duty is reduced, the driving efficiency is improved.

The set duty does not change as long as the counter does not overflow. Therefore, if the rotational speed after the duty control is roughly assumed in advance and the counter does not overflow, the exact rotational speed cannot be determined. Even when the duty is set, the duty can be set.

Further, even if the absolute value of the clock frequency varies, the set duty is maintained as long as the frequency ratio of the clock input to each counter does not deviate. In this case, there is no variation in duty due to variations in circuit components or elements.

[Brief description of the drawings]

FIG. 1 is a schematic configuration diagram showing a configuration example of a single-wire wound two-phase four-pole half-wave drive brushless motor.

FIG. 2 is a schematic configuration diagram showing a configuration example of a two-wire wound two-phase four-pole half-wave drive brushless motor.

FIG. 3 is a block diagram showing a configuration example of a conventional two-phase half-wave brushless motor drive circuit capable of duty control.

FIG. 4 is a timing chart showing changes in a hall amplifier input voltage, an output voltage of an output circuit, and a duty control output in a conventional two-phase half-wave brushless motor drive circuit capable of duty control.

FIG. 5 is a block diagram showing a configuration example of a duty control unit in a drive circuit of a two-phase half-wave drive brushless motor according to the present invention.

6 shows changes in a Hall amplifier input voltage, an output voltage of an output circuit, an output of a counter constituting a duty control circuit, and a duty control output when the embodiment of FIG. 5 is applied to the motor drive circuit of FIG. 3; It is a timing chart.

FIG. 7 is a block diagram showing a configuration example when the present invention is applied to a sensorless two-phase half-wave brushless motor drive circuit.

FIG. 8 is a circuit diagram showing a specific example of a B-emf detection circuit constituting the motor drive circuit of FIG. 7;

9 shows changes in the output voltage of the output circuit, the back electromotive force detection signal, the output of the counter constituting the duty control circuit, the duty control output, etc. when the embodiment of FIG. 5 is applied to the sensorless motor drive circuit of FIG. FIG.

FIG. 10 is a block diagram illustrating a configuration example of a clock generation circuit that generates a clock input to a counter configuring a duty control circuit from a master clock.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Rotor magnet 2 Stator core 3 First phase winding 4 Second phase winding 5 Hall element 13 Hall amplifier 14 Control logic 15 Duty control circuit 17 Back electromotive force detection circuit 21 Clock generation circuit φ1 For first phase Winding φ2 Second phase winding Q1, Q2 Output transistor

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Kunio Seki 2196-65 F-term, Hirai-cho, Hinode-cho, Nishitama-gun, Tokyo 5H560 AA01 BB03 BB12 DA02 DA13 EB05 TT02 TT05 TT07 TT15 UA05 XA04 XB08

Claims (6)

[Claims] 1. A brushless motor drive device for rotating a motor by switching a current flowing through each phase winding of a brushless motor having a two-phase stator winding, wherein the stator winding of each phase of the motor is provided. An output circuit for selectively energizing the wire, a rotation detecting means for detecting a rotational position of the rotor, a control circuit for controlling the output circuit based on a detection signal of the rotation detection circuit, and a control circuit for controlling the output circuit from the output circuit. A duty control circuit for determining a duty of a control pulse supplied to the control circuit, and a clock generation circuit for generating a clock signal required by the control circuit and the duty control circuit, wherein the duty control circuit comprises a first clock signal And a first counter for counting the half period of the signal indicating the rotation of the rotor, and counting the count value of the counter at different frequencies. Of the second and third counters that count with the clock of the second clock, the rising of the duty control pulse is determined by the output of the counter that counts with the clock with the higher frequency, and the counter that counts with the clock with the lower frequency. A brushless motor driving device wherein the fall of a duty control pulse is determined by an output. 2. The clock generation circuit according to claim 1, wherein the clock generation circuit divides a reference clock signal to generate the first, second, and third clock signals, and the clock generation circuit generates the first, second, and third clock signals. Clock switching means for switching a clock supplied to the first, second, and third counters as the first, second, and third clock signals from among the plurality of clock signals. 2. The brushless motor driving device according to claim 1, wherein the duty can be changed by switching between the second and third clock signals. 3. The method according to claim 1, wherein the first counter counts a half cycle of the signal indicating the rotation of the rotor every half cycle or at any half cycle. Brushless motor drive. 4. A back electromotive force detection circuit for detecting a back electromotive force induced in a winding of a non-energized phase among the windings, wherein the detection signal of the back electromotive force detection circuit is 4. The brushless motor driving device according to claim 1, wherein a signal indicating the rotation of the rotor is supplied to the control circuit. 5. The rotation detecting means comprises a Hall element and an amplifier circuit for amplifying an output of the Hall element, and an output signal of the amplifier circuit is supplied to the control circuit as a signal indicating the rotation of the rotor. The brushless motor drive device according to claim 1. 6. The control circuit according to claim 1, wherein the control circuit is configured to operate by a clock signal having a frequency one digit or more higher than the first, second, and third clock signals. 5. The brushless motor driving device according to any one of the above items 5.