JP2002314033A - Multichip module - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a multichip module in which semiconductor chips can be connected to each other at high density and, at the same time, a power source can be reinforced. SOLUTION: This multichip module is provided with semiconductor chips 21-1 to 21-3, first substrates 24-1 to 24-3, a group of wires 27, and a second substrate 26. Each semiconductor chip has a group of two-dimensionally arranged first connecting terminals 22 and a group of second connecting terminals 23 which are arranged along one side of the chip. The semiconductor chips 21-1 to 21-3 are respectively mounted on the first substrates 24-1 to 24-3 interposed with the first connecting terminals 22. The groups of second connecting terminals 23 of the semiconductor chips 21-1 to 21-3 are electrically connected to each other so that signals are delivered and received among the groups 23.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a multi-chip module having a plurality of semiconductor chips mounted on a substrate.

[0002]

2. Description of the Related Art Conventionally, a multichip module is configured as shown in FIGS. 15A to 15F and FIGS. 16A and 16B. FIGS. 15A to 15C respectively show a plurality of mounted semiconductor chips 11-1 to 11-.
FIG. 15 is a plan view of FIG. 3 viewed from the mounting surface (element forming surface) side.
(D) to (f) correspond to A in FIGS. 15 (a) to (c), respectively.
It is sectional drawing along the -A 'line, the BB' line, and the CC 'line. FIG. 16A is a plan view of the multi-chip module as viewed from the mounting surface side on a mounting board or the like, and FIG. 16B is a cross-sectional view taken along line DD ′ of FIG. 16A. .

As shown in FIGS. 15A to 15C, the mounting surfaces of the semiconductor chips 11-1 to 11-3 are solder bumps 12-1 to 12-12 at a pitch ΔP1 of several hundred μm, respectively.
-3 are two-dimensionally arranged (area arrangement).

These semiconductor chips 11-1 to 11-3
Is connected to the high-density multilayer wiring board 13 by C4 connection (Controlled Collapse Chip Connector) as shown in FIGS.
ction). Each semiconductor chip 11-1 to 11-11
-3 are electrically connected by the multilayer wiring 14 provided in the high-density multilayer wiring board 13, and the semiconductor chip 11-2 mounted at the center and the semiconductor chip 1 mounted at the left and right are connected.
Signals are transmitted and received between 1-1 and 11-3. On the back side of the mounting surface of the semiconductor chips 11-1 to 11-3 in the high-density multilayer wiring board 13, a BGA
The balls 15 are two-dimensionally arranged, and the multichip module is mounted on a mounting substrate by flip-chip connection or the like.

However, in the multi-chip module having the above-described structure, the high-density multilayer wiring board 13 has a structure between the semiconductor chips 11-1 and 11-2 and the semiconductor chip 11.
Since the connection between −2 and 11−3 is performed, the number of layers of the substrate 13 increases and the size of the substrate 13 increases, which causes a problem that the cost of the multichip module increases.

In order to reduce the cost of the multichip module, instead of the high-density multilayer wiring board 13, a TA
A technique of connecting a plurality of semiconductor chips at a narrow pitch (for example, a pitch of 40 to 50 μm) using a B tape or wire bonding has been proposed. However, with these techniques, electrical connection can be made only at the peripheral portions of the semiconductor chips 11-1 to 11-3. For this reason, there is a problem that the technique of reinforcing the power supply by arranging the solder bumps 12-1 to 12-3 two-dimensionally and supplying power to a large number of locations cannot be applied.

[0007]

As described above, the conventional multi-chip module has a problem that it is difficult to achieve both high-density connection between a plurality of semiconductor chips and power supply reinforcement.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a multi-chip module capable of achieving both high-density connection between a plurality of semiconductor chips and power supply reinforcement. It is in.

[0009]

A multi-chip module according to the present invention has a first connection terminal group arranged two-dimensionally at a central portion of a chip and a second connection terminal group arranged at a peripheral portion of the chip. A plurality of semiconductor chips each having a plurality of semiconductor chips, and the plurality of semiconductor chips are arranged so as to face the first connection terminal group, respectively, and the plurality of semiconductor chips are mounted and the first connection terminal group. A plurality of first substrates each having a third connection terminal group two-dimensionally arranged on a back surface side of a surface facing the plurality of semiconductor chips, corresponding to the plurality of semiconductor chips; A wiring group for transmitting and receiving signals between the semiconductor chips by electrically connecting the two connection terminal groups; and a second substrate to which the plurality of semiconductor chips are fixed via an insulating member. Equipped with It is characterized in Rukoto.

Further, the multichip module of the present invention has a first bump group arranged two-dimensionally and a second bump group arranged at a smaller pitch than the first bump group and arranged along at least one side. A plurality of semiconductor chips each having two bump groups; and a plurality of semiconductor chips arranged so as to face the first bump groups of the plurality of semiconductor chips, respectively.
A plurality of substrates on which the plurality of semiconductor chips are mounted via the first bump group, and first mounting balls respectively provided on a back surface side of the mounting surface of the semiconductor chip of the plurality of substrates; A device hole in which each of the plurality of semiconductor chips is arranged; and a first lead for electrically connecting the second bump group between the plurality of semiconductor chips. And a mounted TAB tape.

According to the above-described structure, since the connection between the semiconductor chips is performed by the second connection terminal group (second bump) and the wiring group (lead) which can be arranged at a narrow pitch, high-density connection is achieved. Can be. In addition, a first substrate is provided for each semiconductor chip, and the area of the mounting surface of the semiconductor chips of the plurality of first substrates can be made smaller than the area of the mounting surface of each semiconductor chip, and the number of layers is small. Cost can be reduced. Furthermore, power can be supplied to each semiconductor chip from the third connection terminal group (first mounting ball) two-dimensionally arranged, so that power supply can be reinforced.

Accordingly, high-density connection between a plurality of semiconductor chips and power supply reinforcement can be achieved at the same time.

[0013]

Embodiments of the present invention will be described below with reference to the drawings. [First Embodiment] FIGS. 1A to 1F and FIG.
FIGS. 1 (a) and 1 (b) are for describing a multichip module according to a first embodiment of the present invention, and FIGS. 1 (a) to 1 (c) show a plurality of mounted semiconductor chips 21. FIG. FIGS. 1D to 1F are plan views of -1 to 21-3 viewed from the mounting surface (element formation surface) side.
(A) to (c) A1-A1 ′ line, B1-B1 ′ line, C
It is sectional drawing along the 1-C1 'line. FIG. 2 (a)
FIG. 2B is a plan view of the multichip module as viewed from the mounting surface side on a mounting board or the like, and FIG. 2B is D1-D1 ′ in FIG.
It is sectional drawing along the line.

As shown in FIGS. 1A to 1C, the mounting surface of the semiconductor chips 21-1 to 21-3 is, for example,
The solder bumps (first connection terminal group) 22-1 to 22-3 are two-dimensionally arranged (area arranged) at a pitch ΔP1 of 0 μm, and are arranged along one opposing side close to an adjacent semiconductor chip, for example. Pitch ΔP2 of 40 to 50 μm
And solder bumps (second connection terminal group) 23-1, 23-2
A, 23-2B and 23-3 are formed. The solder bumps 22-1 to 22-3 are mainly used to supply power to the respective semiconductor chips 21-1 to 21-3, and the solder bumps 23-1, 23-2A, and 23-2 are respectively used.
B and 23-3 are the semiconductor chips 21-1 and 21 respectively.
-2 and between the semiconductor chips 21-2 and 21-3.

As shown in FIGS. 2A and 2B, the semiconductor chips 21-1 to 21-3 are connected to fan-in type substrates (first substrates) 24-1 to 24-3 by C4 connection. Has been implemented. At the time of this C4 connection, the solder bump 22
-1 to 22-3 are used. These substrates 24-1 and 24-2
BGA balls (third connection terminal group) 25-1 to 25-3 are formed on the back side of the mounting surface of the semiconductor chips 21-1 to 21-3 of 4-3, respectively. The module is mounted on a mounting substrate by flip-chip connection or the like.

The solder bumps 23-1, 23-2A, 23-2B, and 23-3 of the semiconductor chips 21-1 to 21-3 mounted on the substrates 24-1 to 24-3 are TAB, respectively. They are electrically connected by leads (wiring group) 27 of a tape (second substrate) 26. Then, the substrates 24-1 to 24-3 and the semiconductor chips 21-1 to 21-2 are used.
1-3 area, end of lead 27, TAB tape 26
And the ends of the semiconductor chips 21-1 to 21-3 are fixed and sealed by sealing resins 28-1 to 28-3, respectively.

The above sealing resins 28-1 to 28-3
Can be performed collectively in a vacuum, but by performing the sealing twice, the sealing can be performed at low cost using a normal resin sealing device. That is, first, FIG.
As shown in (a) to (c), each semiconductor chip 21-1
21-3 are fan-in type substrates 24-1 to 24-
3 and the semiconductor chips 21-1 to 21-3 and the substrate 24-1 using the capillary phenomenon.
The region between ２４24-3 is sealed with a resin layer 28A. Thereafter, each of the semiconductor chips 21-1 to 21-3 and the substrate 2
4-1 to 24-3 are mounted on a TAB tape 26, and the periphery of the resin layer 28A is sealed with a potting resin 28B.

According to the above configuration, the semiconductor chips 21-1 and 21-2, and the semiconductor chips 21-2 and 2-1,
A high density connection can be made between 1-3 using the leads 27 of the TAB tape 26. Moreover, each semiconductor chip 2
Substrates 24-1 to 24-3 are provided for each of the semiconductor chips 21-1 to 21-3. Since the area of the mounting surface can be made smaller and the number of layers can be reduced, the cost can be reduced. In addition, each of the semiconductor chips 21-1 to 21-2
1-3, BGA balls 25-1 arranged two-dimensionally
Since power is supplied from 25-3, power supply can be reinforced.

Further, since the TAB tape 26 is flexible, the space efficiency can be improved as compared with the case where the high-density multilayer wiring board 13 is used. When the high-density multilayer wiring board 13 is used, skew may occur due to the difference in the wiring length of the multilayer wiring 14. However, in the first embodiment, the semiconductor chips 21-1 and 21-1 are used. −
Since the lengths of the wires (leads 27) connecting the two and the semiconductor chips 21-2 and 21-3 are equal, the skew can be reduced.

[Second Embodiment] FIGS. 4 (a) to 4 (f)
FIGS. 5 (a) and 5 (b) are for explaining a multi-chip module according to a second embodiment of the present invention, and FIGS. FIGS. 4D to 4F are plan views of the semiconductor chips 21-1 to 21-3 as viewed from the mounting surface side, and FIGS.
A2-A2 ′ line, B2-B2 ′ line, C2-C of (c)
It is sectional drawing which followed the 2 'line. FIG. 5A is a plan view of the multichip module as viewed from a mounting surface on a mounting board or the like, and FIG. 5B is a cross-sectional view taken along line D2-D2 ′ of FIG. 5A. .

The difference between the multi-chip module according to the second embodiment and the first embodiment is that the multi-chip module is, for example, 40 to 50 μm along two opposing sides of the semiconductor chips 21-1 and 21-3. Pitch 23-1
A, 23-1B and 23-3A, 23-3B are respectively formed. The above solder bump 23-1
B, 23-3A are used for electrical connection with the semiconductor chip 21-2, and the solder bumps 23-1A, 23-3 are used.
B is connected to a lead 29 formed on the TAB tape 26. A BGA ball 30 is connected to the lead 29. The lead 29 may be used for transmitting and receiving signals to and from the outside via the BGA ball 30, or may be used as a power supply line.

Here, the BGA ball 30 is a BGA ball 30.
The size is larger than the balls 25-1 to 25-3, so that the multichip module is kept flat when mounted on a mounting board or the like, and connection failure is suppressed.

Since the other basic configuration is the same as that of the first embodiment, the same portions are denoted by the same reference numerals and detailed description thereof will be omitted.

With such a configuration, the same operation and effect as those of the first embodiment can be obtained. Further, signals can be transmitted and received not only between adjacent semiconductor chips but also between the outside and the semiconductor chips.

[Third Embodiment] FIGS. 6 (a) to 6 (f)
7 (a) and 7 (b) are for explaining a multi-chip module according to a third embodiment of the present invention, and FIGS. 6 (a) to 6 (c) show a plurality of mounted multi-chip modules. FIGS. 6D to 6F are plan views of the semiconductor chips 21-1 to 21-3 as viewed from the mounting surface side, and FIGS.
A3-A3 ′ line, B3-B3 ′ line, C3-C of (c)
It is sectional drawing which followed the 3 'line. FIG. 7A is a plan view of the multi-chip module as viewed from a mounting surface side on a mounting board or the like, and FIG. 7B is a cross-sectional view taken along line D3-D3 ′ of FIG. 7A. .

In the third embodiment, the semiconductor chip 2
A pitch Δ of, for example, 40 to 50 μm along three sides of 1-1, 21-3 and four sides of the semiconductor chip 21-2.
The solder bumps 23-1 to 23-3 are formed at P2, and the central portion of the semiconductor chip 21-2 and the semiconductor chip 21-
The solder bumps 22-1 to 22-22 are arranged at a pitch ΔP1 of, for example, several hundred μm in a region surrounded by the three sides 1, 21-3.
-3 are two-dimensionally arranged (area arrangement).

Each of the semiconductor chips 21-1 to 21-
3 not only in the region along the adjacent side, but also between the solder bumps 23-1 to 23-3 along the other side.
6, the semiconductor chips 21-1 to 21-21
-3 are electrically connected.

Another basic configuration is similar to the first and second embodiments described above.
Therefore, the same reference numerals are given to the same parts, and the detailed description is omitted.

According to such a configuration, the first and the second
The same operation and effect as those of the embodiment can be obtained. Further, the semiconductor chips 21-1 to 21-3 can be connected with a higher degree of freedom.

[Fourth Embodiment] FIGS. 8 (a) to 8 (f)
9 (a) and 9 (b) are for explaining a multi-chip module according to a fourth embodiment of the present invention, and FIGS. FIGS. 8D to 8F are plan views of the semiconductor chips 21-1 to 21-3 as viewed from the mounting surface side, and FIGS.
A4-A4 ′ line, B4-B4 ′ line, C4-C of (c)
It is sectional drawing which followed the 4 'line. FIG. 9A is a plan view of the multi-chip module as viewed from the mounting surface side on a mounting board or the like, and FIG. 9B is a cross-sectional view taken along line D4-D4 ′ of FIG. 9A. .

The difference between the multi-chip module according to the fourth embodiment and the first embodiment is that
Semiconductor chips 21-1 to 21- in AB tape 26
3 is that a stiffener (tape reinforcing plate) 31 is added to the mounting surface side. The stiffener 31 has openings 31A, 3A corresponding to the semiconductor chips 21-1 to 21-3.
1B and 31C are formed.
Semiconductor chips 21-1 to 21-A in A, 31B and 31C
3 are arranged.

According to the above-described configuration, the semiconductor chips 21-1 to 21-3 can be kept flat by the stiffener 31, so that variations in the height of the mounting surface can be suppressed.

When the multichip module is formed, the stiffener 31 is attached to the TAB tape 26, and then the TAB connection of the semiconductor chips 21-1 to 21-3 mounted on the substrates 24-1 to 24-3 is performed. By doing so, damage to the lead (TAB wiring) 27 having low wiring strength can be reduced. Furthermore, since the deflection of the lead 27 can be reduced by the stiffener 31, the precision of the resin sealing step can be improved, and the sealing resins 28-1 to 28-3 can be flattened.

In this embodiment, the wiring (lead 27) between the semiconductor chips can be formed into a microstrip structure by using a metal for the stiffener (tape reinforcing plate) 31 and grounding the metal.

[Fifth Embodiment] FIGS.
(F) and FIGS. 11 (a) and 11 (b) are for describing a multi-chip module according to a fifth embodiment of the present invention, and FIGS. 10 (a) to 10 (c) are mounted. 10D are plan views of the plurality of semiconductor chips 21-1 to 21-3 viewed from the mounting surface side, and FIGS. 10D to 10F are A5-A5 'lines in FIGS. 10A to 10C, respectively. B5-B
It is sectional drawing which followed the 5 'line and the C5-C5' line. Also,
FIG. 11A is a plan view of the multichip module as viewed from the mounting surface side on a mounting board or the like, and FIG.
It is sectional drawing along the D5-D5 'line of (a).

In the multichip module according to the fifth embodiment, the slits 32A and 32B are provided in the region between the semiconductor chips 21-1 to 21-3 of the stiffener 31 in the fourth embodiment. Things.

According to the above configuration, each of the semiconductor chips 21-1 to 21-3 is formed by the stiffener 31.
Is kept flat, the variation in height of the mounting surface is suppressed, and the stress of the entire multi-chip module can be reduced by the slits 32A and 32B.

[Sixth Embodiment] FIGS.
(F) and FIGS. 13 (a) and (b) are for describing a multichip module according to a sixth embodiment of the present invention, and FIGS. 12 (a) to (c) are mounted. 12D are plan views of the plurality of semiconductor chips 21-1 to 21-3 viewed from the mounting surface side, and FIGS. 12D to 12F are A6-A6 ′ lines in FIGS. 12A to 12C, respectively. B6-B
It is sectional drawing which followed the 6 'line and the C6-C6' line. Also,
FIG. 13A is a plan view of the multi-chip module as viewed from a mounting surface side on a mounting board or the like, and FIG.
It is sectional drawing along the D6-D6 'line of (a).

In the sixth embodiment, a cover plate (radiator plate) 33 is provided on the stiffener 31 in the fourth embodiment.

According to such a configuration, the heat radiation effect can be enhanced in addition to the effects of the above-described fourth embodiment.

In addition, by manufacturing in the following process, batch sealing can be performed without using a vacuum device or the like. That is, first, the stiffener 31 is attached to the TAB tape 26, and the leads 27 of the TAB tape 26 are attached.
And the solder bumps 23 of the semiconductor chips 21-1 to 21-3.
-1, 23-2A, 23-2B and 23-3 are connected.
Thereafter, a cover plate 33 is attached to the stiffener 31. Subsequently, each of the above semiconductor chips 21-1 to 21-2
The resin is applied with the solder bump forming surface (element forming surface) of 1-3 facing upward. Then, the substrates 24-1 to 24-3 are mounted on the solder bump forming surface to which the resin is applied, with the mounting surface facing down, and are placed in a reflow furnace and subjected to heat treatment. This heat treatment cures the sealing resins 28-1 to 28-3, melts the solder bumps 23-1 to 23-3, and turns the semiconductor chips 21-1 to 21-3 into the substrates 24-1 to 24-3.
24-3. Thereby, the resin sealing step and the substrates 24-1 to 24-2 of the semiconductor chips 21-1 to 21-3 are performed.
The mounting process for 4-3 can be performed collectively.

[Seventh Embodiment] FIG. 14 is a cross-sectional view for describing a multichip module according to a seventh embodiment of the present invention. In the seventh embodiment, each semiconductor chip 21 is bonded by wire bonding instead of the TAB tape 26 in the first to sixth embodiments.
-1 to 21-3 are connected.

That is, the insulating members 35-1 to 35-3 are formed on the substrate 34 made of, for example, AlN and serving as a heat sink.
The semiconductor chips 21-1 to 21-3 are mounted with interposing. In each of the semiconductor chips 21-1 to 21-3, the back side of the mounting surface is fixed on the insulating member 35,
These semiconductor chips 21-1 to 21-3 are mounted on fan-in type substrates 24-1 to 24-3. The semiconductor chips 21-1 and 21-2 and the semiconductor chips 21-2 and 21-3 are electrically connected using bonding wires 36A and 36B, respectively.

In the wire bonding, connection can be made at a pitch of about 50 μm, and high-density connection almost equal to the case of using the TAB tape 26 can be made.

In the above description, the substrate 34 is made of Al
Although the case where N is used has been described as an example, other metals and ceramics may be used as long as the material has a thermal expansion coefficient close to that of silicon.

Although the present invention has been described with reference to the first to seventh embodiments, the present invention is not limited to the above-described embodiments, and the scope of the present invention does not depart from the gist of the present invention. Can be variously modified. In addition, the above embodiments include inventions at various stages, and various inventions can be extracted by appropriately combining a plurality of disclosed constituent elements. For example, even if some components are deleted from all the components shown in each embodiment, at least one of the problems described in the column of the problem to be solved by the invention can be solved, and the effects described in the column of the effect of the invention can be solved. In a case where at least one of the effects described above is obtained, a configuration in which this component is deleted can be extracted as an invention.

[0047]

As described above, according to the present invention, it is possible to obtain a multi-chip module capable of achieving both high-density connection between a plurality of semiconductor chips and reinforcement of a power supply.

[Brief description of the drawings]

FIG. 1 is a plan view of a multi-chip module according to a first embodiment of the present invention, in which a plurality of semiconductor chips to be mounted are viewed from a mounting surface side and a cross-sectional view thereof.

FIGS. 2A and 2B are a plan view and a cross-sectional view of the multichip module according to the first embodiment of the present invention, as viewed from a mounting surface side on a mounting board or the like.

FIG. 3 is a view for explaining an example of a sealing step of the multi-chip module shown in FIG. 2;

FIGS. 4A and 4B are a plan view and a cross-sectional view of a multi-chip module according to a second embodiment of the present invention, in which a plurality of semiconductor chips to be mounted are viewed from a mounting surface side.

FIG. 5 shows a multi-chip module according to a second embodiment of the present invention, and is a plan view and a cross-sectional view of the multi-chip module as viewed from a mounting surface side on a mounting board or the like.

FIGS. 6A and 6B are a plan view and a cross-sectional view of a multi-chip module according to a third embodiment of the present invention, in which a plurality of semiconductor chips to be mounted are viewed from a mounting surface side.

FIG. 7 shows a multi-chip module according to a third embodiment of the present invention, and is a plan view and a cross-sectional view thereof as viewed from a mounting surface side on a mounting board or the like.

FIGS. 8A and 8B are a plan view and a cross-sectional view of a plurality of semiconductor chips to be mounted as viewed from a mounting surface side, for explaining a multichip module according to a fourth embodiment of the present invention.

FIG. 9 shows a multi-chip module according to a fourth embodiment of the present invention, and is a plan view and a cross-sectional view of the multi-chip module as viewed from a mounting surface side on a mounting board or the like.

FIGS. 10A and 10B are a plan view and a cross-sectional view of a multi-chip module according to a fifth embodiment of the present invention, in which a plurality of semiconductor chips to be mounted are viewed from a mounting surface side.

FIG. 11 shows a multi-chip module according to a fifth embodiment of the present invention, and is a plan view and a cross-sectional view of the multi-chip module as viewed from a mounting surface side on a mounting board or the like.

FIG. 12 is a plan view of a multi-chip module according to a sixth embodiment of the present invention, showing a plurality of semiconductor chips to be mounted as viewed from a mounting surface side and a cross-sectional view thereof.

FIG. 13 shows a multi-chip module according to a sixth embodiment of the present invention, and is a plan view and a cross-sectional view thereof as viewed from a mounting surface side on a mounting board or the like.

FIG. 14 is a sectional view of a multi-chip module according to a seventh embodiment of the present invention.

FIG. 15 is a plan view and a cross-sectional view of a plurality of semiconductor chips to be mounted as viewed from a mounting surface side for explaining a conventional multichip module.

FIG. 16 shows a conventional multi-chip module, and is a plan view and a cross-sectional view thereof as viewed from a mounting surface side on a mounting board or the like.

[Explanation of symbols]

21-1 to 21-3: semiconductor chip, 22-1 to 22-
3, 23-1, 23-1A, 23-1B, 23-2A,
23-2B, 23-3, 23-3A, 23-3B ... solder bumps, 24-1 to 24-3 ... fan-in type substrates, 25-1 to 25-3, 30 ... BGA balls, 26 ...
TAB tape, 27, 29 ... lead, 28-1 to 28-
3: sealing resin, 28A: resin layer, 28B: potting resin, 31: stiffener (tape reinforcing plate), 31A,
31B, 31C ... opening, 32A, 32B ... slit,
33: cover plate (heat sink), 34: board, 35-
1-35-3: insulating members, 36A, 36B: bonding wires.

Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat II (reference) H01L 25/18 (72) Inventor Yoshiaki Sugisaki 1 Kosuka Toshiba-cho, Saiwai-ku, Kawasaki-shi, Kanagawa Pref. Inside (72) Inventor Naoyuki Komuta 1st address, Toshiba Microelectronics Center, Komukai, Kawasaki City, Kanagawa Prefecture Inside (72) Inventor Masashi Otsuka 1st address, Komukai Toshibacho, Saiwai-ku, Kawasaki City, Kanagawa Prefecture In the Toshiba Microelectronics Center Co., Ltd. (72) Inventor Eiji Takano 1 in Komukai Toshiba-cho, Saiwai-ku, Kawasaki-shi, Kanagawa Prefecture In the Toshiba Microelectronics Center Co., Ltd. (72) The inventor Hiroshi Tazawa Sachi-ku, Kawasaki-shi, Kanagawa Prefecture No. 1 Komukai Toshiba-cho F-term in Toshiba Microelectronics Center Co., Ltd. (reference) 5F044 MM06 MM07 MM08

Claims (6)

[Claims] A plurality of semiconductor chips each having a first connection terminal group two-dimensionally arranged in a central portion of the chip and a second connection terminal group arranged in a peripheral portion of the chip; The plurality of semiconductor chips are mounted so as to be opposed to the first connection terminal group of the semiconductor chip, respectively, and are respectively opposed to the plurality of semiconductor chips corresponding to the first connection terminal group. Electrically connecting the plurality of first substrates having the third connection terminal group two-dimensionally arranged on the back surface side of the surface to be connected, and the second connection terminal group between the plurality of semiconductor chips; A multi-chip module comprising: a wiring group for transmitting and receiving signals between the respective semiconductor chips; and a second substrate to which the plurality of semiconductor chips are fixed via an insulating member. 2. A first bump group arranged two-dimensionally, and arranged at a narrower pitch than the first bump group,
A plurality of semiconductor chips each having a second bump group arranged along at least one side; and the first bump group arranged to face the first bump group of the plurality of semiconductor chips, respectively. A plurality of substrates on each of which the plurality of semiconductor chips are mounted, a first mounting ball provided on the back surface side of the mounting surface of the semiconductor chip of the plurality of substrates, and the plurality of semiconductor chips. A device hole to be respectively arranged, and the second hole between the plurality of semiconductor chips.
A first lead for electrically connecting the set of bumps, and a TAB tape on which the plurality of semiconductor chips are mounted. 3. The TAB tape includes a second lead for leading some of the electrodes of the plurality of semiconductor chips to the outside, and a second mounting ball electrically connected to the second lead. The multi-chip module according to claim 2, further comprising: 4. The multi-chip module according to claim 2, further comprising a tape reinforcing plate provided on the mounting surface side of the plurality of semiconductor chips in the TAB tape. 5. The multi-chip module according to claim 4, wherein the tape reinforcing plate has a slit for reducing stress provided in a region between adjacent semiconductor chips. 6. The multi-chip module according to claim 4, further comprising a heat radiating plate provided on the tape reinforcing plate.