JP2002313921A - Method for designing wiring layout of semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve the problem of a prior art optimization method where a wiring interval is not taken into account at the time of minimizing a wiring delay that sufficient optimization is not ensured. SOLUTION: At first, the enlargement and contraction of the wiring width and wiring interval are defined virtually for an original wiring net at an RC network listing step 1 and all RC networks are listed based on the definition. At an altered RC network listing step 2, the insertion of a buffer and enhancement of the driving capacity of a drive side transistor (enlargement of transistor size) are effected for all RC networks determined previously while taking account of the inclination of an input waveform and an RC network of minimum path delay is determined. Finally, at a minimum delay RC network selecting step 3, an RC network of minimum delay is selected among groups of RC networks thus determined and a corresponding wiring layout is employed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to a semiconductor integrated circuit,
In particular, the present invention relates to a method for minimizing a transmission delay of an electric signal on a wiring in an LSI.

[0002]

2. Description of the Related Art With the rapid progress of LSI manufacturing technology, transistor device size has been reduced, and as a result, LSI
Has been dramatically increasing. The device size was about 1 μm in about 1990, but it has been reduced to 0.18 μm in 2000. In addition, the speed of the device has been improved, and the delay of long-distance interconnect wiring (inter-wiring) has become so important as to determine the LSI operation, so that it is occupying an important position in LSI design. Some systems report that interconnect wiring delays account for about 50% to 70% of clock cycles.

[0003] With the advance of manufacturing technology, the relative increase in wiring delay with respect to transistor delay has led to the development of LSI
Changes are being made in the design methodology. Until the 1 μm era, the concept of transistor design was ignoring wiring delay, but since the submicron era, it has become necessary to consider wiring delay. Further, at present, the interconnect wiring delay has become so important as to affect the performance of the LSI itself. Therefore, a technique for suppressing the delay is indispensable, and research is being actively conducted.

[0004] The wiring optimization techniques can be roughly classified into (1) wiring topology optimization, (2) driving capability optimization, (3) wiring interval expansion, (4) wiring width optimization, (5) buffer insertion, and the like. is there. The brief description is as follows.

(1) When there are two or more fan-out wiring nets from a certain source (driver side), the arrival time to the sink (leaf side) differs depending on the wiring shape. “Wiring topology optimization” is a technique for finding a topology for minimizing the arrival time. Since it is often used when determining a wiring path, it is mainly used in a process of determining a schematic wiring path after placement in LSI design.

(2) The influence on the wiring delay is caused by a capacitance component and a resistance component. When the driving capability of the transistor is increased, transmission of an electric signal is increased. The technology utilizing this phenomenon is the “drive capability optimization technology”. This can be regarded as a technique for suppressing the influence of the capacitance component on the delay.

(3) By changing the viewpoint from (2), the delay can be suppressed by lowering the capacitance component.
In a CMOS circuit, charge and discharge are repeatedly performed with respect to a wiring capacitance and an input terminal capacitance. When the capacitance value is reduced, the delay is naturally reduced. Therefore, it is meaningful to reduce the capacitance component. The wiring capacitance can be roughly divided into two parts, that is, between the substrate and the wiring. However, if the wiring interval is increased, the capacitance component between the wirings can be reduced. This technique is used in "interconnect spacing control technique".
In the deep submicron era, this technology is more effective because the coupling capacitance becomes dominant over the total capacitance component.

(4) In the wiring in the deep submicron era, the influence of the resistance component on the delay becomes larger than the influence of the capacitance component on the delay with miniaturization. In particular, this tendency becomes remarkable in long-distance wiring. The “wiring width optimization technology” is a technology that involves a slight increase in wiring capacitance but reduces delay by suppressing wiring resistance.

(5) As a technique for suppressing the wiring resistance, there is a technique based on wiring net division. This is called "buffer (repeater) insertion technology". In a long-distance wiring of a certain length or more, even if a transistor having a high driving ability is connected, the delay cannot be improved because the influence of the resistance component is large.
Therefore, the effect of wiring resistance is suppressed by replacing long-distance wiring with a series of short wiring by using buffer insertion technology.
Improve delay.

[0010]

By the way, in the submicron age, the influence of the capacitance component on the delay was great.
Only the above technique (2) focusing on the capacitance component was sufficient. In the deep submicron era, the coupling capacitance becomes dominant as the capacitance component, and the influence of the wiring resistance component on the delay increases, so the above (1), (3) to (5)
Technology is needed even more.

Recent researches have developed a technique (composite technique) that can further improve the optimality by using the above-described delay minimizing technique in a combined manner. For example, (1) and (5) are combined to create a wiring topology and at the same time a buffer insertion position is determined. (2) and (4) are combined to optimize driving capability and wiring width. )
And (5) are combined to optimize the wiring width simultaneously with the buffer insertion, and (2), (4) and (5) are combined to optimize the driving capability and the wiring width simultaneously with the buffer insertion. .

[0012] Known materials that systematically describe these techniques include Cong, J., L. He, CK Koh, and P. Madden,
"Performance Optimization of VLSI Interconnect La
yout "Integration, the VLSI Journal, Vol. 21, 199
6, pp. 1-94.

The background behind the development of composite technology is
It is pointed out that there is a limit in the optimality only with each technology such as the driving capability, the wiring width, and the buffer insertion. Therefore, 2
Attempts have been made to enhance optimization by combining two or more techniques. However, there is no delay minimizing technique that combines a technique for controlling the interval between wires and another technique.

An object of the present invention is to provide a novel method for designing a wiring layout so as to minimize a wiring delay between functional blocks or between logic cells of a semiconductor integrated circuit.

[0015]

A first point of focus of the present invention is to optimize the wiring in consideration of the wiring interval in addition to other techniques. For example, in the past, optimization was performed at the expense of an increase in the wiring capacity because only the wiring width was increased to reduce the wiring resistance. However, when the wiring width is increased at the same time as the wiring width, the wiring can be optimized without increasing the wiring capacitance. According to the present invention, delay minimization is realized by performing optimization in consideration of four techniques for suppressing delay, such as drive capability, wiring interval, wiring width, and buffer insertion. In particular, in the deep submicron era, the coupling capacitance between wirings occupies most of the total capacitance, so that widening the wiring interval is a very useful means.

Specifically, according to the present invention, a wiring net in which a specific wiring interval and wiring width are defined is converted into an RC network expressed by a resistance component and a capacitance component corresponding to the wiring net, Furthermore, a first step of listing RC networks corresponding to each of a plurality of wiring nets obtained by virtually changing the wiring interval and / or wiring width of the wiring net, and a first step obtained by the first step. A second step of selecting a plurality of buffers having different driving capacities for each of the RC networks and listing RC networks in which the path delay is adjusted by changing the buffer insertion position; and The RC network with the minimum delay is selected from all the RC networks obtained in the above, and the wiring layout corresponding to the selected RC network is selected. The third wiring layout design method comprising a step of adopting the adopted.

A second point of interest of the present invention is to take into account the slope of the input signal waveform. In the conventional delay minimizing technique, no consideration is given to the slope of the input signal waveform of each gate. Reducing the slope of the input signal waveform is effective in both reducing power consumption and transistor reliability. Therefore, it is useful to consider the slope of the input signal waveform during delay minimization.

Specifically, when performing the delay adjustment, each RC
It is assumed that the adjustment of the path delay has been completed only when the slope of the input signal waveform of the gate in the network is suppressed below a certain constraint value.

The third point of interest in the present invention is the position where the buffer is inserted. Conventionally, a buffer insertion position has been determined based on a branching position of a wiring or within a predetermined wiring length. In these methods, it is difficult to divide the wiring by a wiring net corresponding to the driving capability of the buffer to be inserted, and as a result, an extra buffer is inserted.

Therefore, according to the present invention, a buffer is inserted at a position where the delay of the critical path having the maximum delay is reduced, thereby realizing the minimum delay of the entire wiring net.

Specifically, for each of the RC networks, a delay calculating step of calculating the total path delay on the RC network, and a maximum delay path selection for selecting a critical path having the maximum delay on the RC network A buffer deletion step of deleting all buffers existing on the critical path; a buffer insertion candidate enumeration step of enumerating buffer insertion position candidates on the critical path; and a delay of the critical path from the candidates. Buffer insertion position determining step of determining a buffer insertion position capable of reducing the above, an RC network updating step of updating the RC network by arranging a buffer at the determined position, and updating the RC network by updating the RC network. Maximum delay of A method comprising an end condition determining step of determining whether or not a change in the critical path has occurred, until the critical path does not change, the delay calculating step, the maximum delay path selecting step, The buffer deletion step, the buffer insertion candidate enumeration step, the buffer insertion position determination step, and the RC network update step are repeatedly executed.

Further, according to the present invention, in determining the buffer insertion position, a "gain value" relating to the slope of the waveform is defined as an index for maximizing the driving capability of the buffer, and it is close to "1". By the way, by dividing
Eliminate excessive buffer insertion.

Specifically, the ratio of the slope of the signal waveform immediately after the output terminal of the buffer to be inserted to the slope of the signal waveform immediately before the next gate connected to the buffer, that is, the gain value is substantially equal to "1". A buffer is inserted at a certain position.

[0024]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a wiring layout designing method according to an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 conceptually shows an application example of a wiring layout designing method according to the present invention. In FIG. 1, 2
Reference numerals 1 to 24 denote buffers in the initial wiring layout. Reference numeral 31 denotes a buffer whose driving capability has been increased, and reference numerals 41 and 42 denote inserted buffers. According to FIG. 1, by changing the wiring width and the wiring interval for the wiring portion, inserting a buffer (an inverter can be used if the polarity is taken into consideration), and improving the driving capability (enlarging the transistor size) for the transistor portion, The amount of path delay has been reduced.

FIG. 2 shows an example of an initial layout of the wiring pattern.
This is a network with fan-out = 3 driving 2, 23 and 24. In FIG. 2, W is a wiring width, S is a wiring interval, and X and Y are branch points of the wiring.

FIG. 3 shows an RC network corresponding to FIG. In FIG. 3, R1 to R7 are resistors, C1
C12 is a capacity. The RC network is a representation of wiring layout information in a network of transistors, resistors, and capacitors. However, in FIG. 3, the buffer is shown as it is for convenience. According to FIG.
A π-type or ladder-type RC circuit is configured between the buffer and the branch position or between branches. For example, the wiring from the driving-side buffer 21 to the next branch point X is connected to the capacitor C1.
And a π-type circuit of the resistor R1 and the capacitor C2. The wiring from the branch point Y to the buffer 22 is represented by a ladder-shaped circuit including a capacitor C5, a resistor R3, a capacitor C6, a resistor R4, and a capacitor C7.

Here, the wiring capacitance will be described with reference to FIG. FIG. 4 shows lines of electric force between conductors. As shown in FIG. 4A, if the wiring is a simple parallel flat plate having no thickness with respect to the substrate, if the area is doubled, the wiring capacitance is doubled. However, in practice, electric lines of force are generated from each side as shown in FIG. In particular, in the wiring structure in the era of the deep submicron, the capacitance in the vertical direction dominate the entire capacitance, so that even if the wiring width is increased, the capacitance value does not greatly increase. Therefore, the wiring capacitance is accurately obtained by the capacitance simulator.

FIG. 5 shows the results obtained by the capacity simulator.
The increase and decrease of the wiring capacitance with respect to the fluctuation of the wiring interval and the wiring width are shown. According to FIG. 5, 0.1 based on certain data
In 8 μm CMOS technology, the capacitance increment was about 5% or less for twice the wiring width. Further, the capacity reduction was 40% or less with respect to doubling the wiring interval.

FIG. 6 shows a wiring layout when the wiring width W of FIG. 2 is doubled, and FIG. 7 shows an RC network corresponding to FIG. When the wiring width W is increased, the wiring resistance value is reduced by half according to Ohm's law. Therefore,
When the wiring width W is evenly doubled, R1, R2,. . . , R7 are R1 ×
0.5, R2 × 0.5,. . . , R7 × 0.5.
On the other hand, from the results of FIG. . . , C12
Are C1 × 1.05, C2 × 1.05,. . . , C12
× 1.05.

FIG. 8 shows a wiring layout when the wiring interval S in FIG. 2 is doubled, and FIG. 9 shows an RC network corresponding to FIG. From the results in FIG.
1, C2,. . . , C12 are C1 × 0.6, C2 ×
0.6,. . . , C12 × 0.6. Wiring resistance R
1, R2,. . . , R7 remain unchanged since there is no change in the wiring width W.

FIG. 10 shows a procedure of a wiring layout designing method according to the present invention. The wiring layout design method according to the present invention is roughly composed of three steps 1 to 3.
That is, RC network enumeration step 1, change RC
It is a network enumeration step 2 and a delay minimum RC network selection step 3.

First, RC network enumeration step 1
Then, the original wiring net is converted into the RC network, and the enlargement and reduction of the wiring width and the wiring interval are virtually defined for the original wiring net, and all the RC networks based on them are listed. For example, in addition to FIG. 3, the RC networks of FIGS. here,
It is assumed that any type of wiring width and wiring interval can be set. At this time, the change in capacitance differs depending on the wiring layer. Therefore, it is necessary to obtain a capacitance simulator for all wiring layers. That is, it is better to predict the capacitance change by associating the simulation result with the wiring layer on the layout for the target RC network,
It will be more accurate. However, for example, when it is desired to apply the present invention to a schematic wiring in which the layout has not been completed, one method is to set the prediction of the capacitance change to the average value of all the wiring layers.

Next, in the modified RC network enumeration step 2, buffers are inserted and the driving capability on the driving side is increased (enlarged transistor size) for all the RC networks obtained above, and each RC network is Find the one with the minimum path delay. Details will be described later.

Finally, in a minimum delay RC network selection step 3, an RC network having a minimum delay is selected from the obtained RC network group, and a wiring layout corresponding to this is adopted.

As described above, according to the method of FIG. 10, since the wiring delay is minimized by simultaneously considering the driving capability of the transistor, the wiring interval, the wiring width, and the buffer insertion, the method of FIG. As a result, a wiring layout result with high optimality can be obtained.

Now, the modified RC network enumeration step 2 is roughly divided into seven steps 2a to 2a as shown in FIG.
2 g. That is, the delay calculation step 2a,
A maximum delay path selection step 2b, a buffer deletion step 2c, a buffer insertion candidate enumeration step 2d, a buffer insertion position determination step 2e, an RC network update step 2f, and an end condition determination step 2g. 11 to 13 show the detailed procedure of the step 2 for listing the changed RC network.

FIG. 11 (a) shows one of the RC network groups obtained in the RC network enumeration step 1. In order to make it easy to understand without losing generality, a buffer 21 is connected to the driving side and buffers 22, 23, and 24 are connected to the driven side, and the wiring has a single width. The description will be made using a layout diagram instead of an RC circuit diagram.

First, in a delay calculating step 2a, the total path delay on the RC network is calculated. That is, the delay times tp1, tp2, and tp3 are calculated for the path between the buffers 21 and 22, the path between the buffers 21 and 23, and the path between the buffers 21 and 24, respectively. Here, there is no limitation on the delay calculation method used in the process. That is, as a representative method, for example, the Elmore method (Journal
of Applied Physics, 1948, pp. 55-63) or a higher-order AWE method (IEEE Trans. Computer-Aided Design, 1990, pp. 352-
366) may be used. Higher order A
If the delay calculation accuracy is improved by using the WE method, the optimality can be improved as a result.

Then, the maximum delay path selection step 2b
Then, the path with the maximum delay is selected from those paths. This maximum delay path is called a critical path in the RC network. Since reducing the delay of the critical path reduces the delay of the RC network, it is realized by inserting a buffer in the following processing.

Next, in a buffer deletion step 2c, all buffers existing on this critical path are deleted.
In this example, there is no buffer on the critical path since it is in the initial state at this stage. Therefore, nothing happens here.

Next buffer insertion candidate enumeration step 2d
Enumerate buffer insertion position candidates on the critical path. Here, only insertion candidates are obtained. Details of how to determine the insertion position will be described later. Here, assuming that FIG.
It is assumed that two points P and Q are listed as shown in FIG.

In the next buffer insertion position determination step 2e, the delay of the critical path is determined assuming that the buffer has actually been inserted at the points P and Q. It should be noted here that there are a plurality of combinations of buffer insertion. That is, there are three insertion patterns: insertion of both points P and Q, insertion of only point P, and insertion of only point Q. For all combinations, the delay of the critical path is determined, and the one that minimizes the delay is selected to obtain an optimal insertion pattern. However, in this case, there are only three insertion patterns because there are only two points.
The number increases exponentially to 6 for points and 14 for 4 points.
In that case, the delay calculation time will be enormous. In the present invention, the method itself is not specified, but a heuristic method is preferable. For example, assuming that a buffer is inserted at point P, the delay of the critical path is calculated. If the insertion can reduce the delay, the buffer is inserted at the point P, otherwise, the buffer is not inserted. Then, assuming that a buffer is inserted at the point Q, the delay of the critical path is calculated. If the insertion reduced the delay, we would insert a buffer at point Q,
Otherwise, do not insert. This way,
Buffer insertion that always reduces the delay of the critical path can be realized. Although an example has been described above, any heuristic method can be applied.
In the present embodiment, it is assumed that point P has been selected.

Subsequently, RC network update step 2
At f, as shown in FIG. 11C, the buffer 40 is arranged at the determined insertion position P to update the RC network. However, it must be noted that the RC network obtained here is a temporary solution. Because the buffer insertion position obtained by these series of steps is the result of optimization to reduce the delay of the initially determined critical path, and how the other paths changed by this buffer insertion Could not be evaluated. That is, there is a possibility that the critical path fluctuates due to the buffer insertion. Therefore, for the obtained RC network, it is necessary to return from the termination condition determination step 2g to the delay calculation step 2a and execute the steps 2a and subsequent steps again to further try to reduce the delay.

In the present invention, the termination condition determination step 2 is further performed.
g, the gradient of the input waveform of the next cell connected to the buffer after the buffer is inserted, that is, slew (sle)
w) is evaluated to determine whether the value exceeds a predetermined constraint value. If the value exceeds the limit value, the buffer insertion is not performed and another pattern is searched. Here, the reason for evaluating the slope of the input waveform is
If the slope of the waveform is gentle, the operating time of the transistor will be longer, and there will be a problem in terms of transistor reliability. is there. This is L
Since it leads to the reliability of the entire SI, it is important to take care when designing the LSI. The present invention has the feature of having this determination criterion, and has a higher quality R
A C network can be created. For the sake of simplicity, the slope of the waveform will not be particularly described below. Note, however, that it is included in the criteria. In the present embodiment, the delay calculation step 2
a and the maximum delay path selection step 2b is performed again, and it is determined that the critical path has changed to another place due to the buffer insertion.
(A).

The buffer deletion step 2c is executed again, but nothing is performed here, since there is no buffer on the critical path. In the next buffer insertion candidate list step 2d, candidates for insertion positions are listed. Here, point R and point S
Are enumerated (FIG. 12B). Further, it is assumed that the buffer insertion position determination step 2e is executed by the same heuristic algorithm described above, and the buffer 41 is inserted at the point R by the RC network update step 2f (FIG. 12C). Then, in the RC network update step 2f, the RC network is updated again. Again, the delay calculation step 2a and the maximum delay path selection step 2b are executed to evaluate the critical path delay. If the delay of the critical path is reduced and the path is changed, the steps after the buffer deletion step 2c are executed again. Here, it is assumed that the critical path has been changed as shown in FIG.

Next, a buffer deletion step 2c is applied. This time, since the buffer 40 exists on the critical path, this is deleted. Specifically, the buffer 40 inserted at the point P is deleted (FIG. 13B). Subsequently, a buffer insertion candidate enumeration step 2d is performed, and points T and U are enumerated as insertion position candidates (FIG. 13).
(C)). Note that the point T
And point U is different from point P and point Q. The reason for this will be described later, but simply speaking, the optimum position fluctuates due to the influence of the buffer 41 inserted at the point R.

Next, buffer insertion position determination step 2e
Selects the point U, and the buffer 42 is inserted therein (FIG. 13D). Again, the RC network is updated in the RC network update step 2f. Next, the delay calculation step 2a and the maximum delay path selection step 2b are executed to evaluate the delay of the critical path. In the present embodiment, it is assumed that the delay does not decrease. That is, this is the optimal solution (FIG. 13E).

FIG. 13A and FIG. 13E show that, although the number of inserted buffers is the same, FIG.
In (e), the delay is reduced. According to the present invention,
Although the buffer is inserted so as to reduce the delay of the path by always focusing on only one critical path, the buffer insertion position changes dynamically, which means that there is an opportunity to obtain a more optimal solution. .

In this embodiment, the delay is reduced by using the buffer. However, the same can be easily realized by using an inverter in consideration of the polarity of the logic. Further, in the present embodiment, the delay of the critical path in the RC network is minimized, but it is also possible to optimize using the delay margin (slack value) of the path as an index. For example, assume that the time of arrival at the buffer 21 is 0, and the request times at which the buffers 22, 23, and 24 must arrive are t1, t2, and t3. The slack value is defined as “request time−path delay time”, and t1−tp
1, t2-tp2, t3-tp3 are determined. When all of these values become positive values, it can be satisfied within the required time. It is also possible to optimize the RC network by such evaluation.

Although the type of buffer to be inserted is not described in the above description, a plurality of buffers with different driving capacities are prepared. By selecting a more suitable buffer type, the delay can be further reduced. Then, it is easy to change the size (driving capability) of the transistor on the driving side. That is, it is possible to further reduce the delay by changing (enlarging) the driving capability of the finally obtained RC network. In addition, an excessively large transistor size can be suppressed by reducing the size.

Here, buffer insertion candidate enumeration step 2
For the explanation of d, the slope of the signal waveform is defined. FIG.
As shown in FIG. 4, when there is a non-linear signal waveform (function of voltage v with respect to time t) for a certain power supply voltage Vdd, a straight line connecting the Vdd × 20% voltage and the Vdd × 80% voltage is drawn. The time difference between the time when the straight line v = 0 and the time when the straight line v = Vdd is defined as the slope Ts of the waveform.

FIG. 15 shows the concept of positioning in the buffer insertion candidate enumeration step 2d. FIG.
As shown in (a), it is assumed that there is one buffer at each end of a certain wiring. The slope of the output signal waveform of the driving buffer is Ts (out), and the slope of the input signal waveform of the driven buffer is Ts (in). Further, a gain value Gslew relating to the slope of the waveform is defined. Here, it is simply expressed as Gslew = Ts (in) / Ts (out).

FIG. 16 shows the increase and decrease of the wiring delay and the signal slew values [Ts (in) and Ts (out)] when the wiring length is changed in a certain process technology. Referring to the graph of FIG. 16, Ts (in) and Ts (out) show almost the same value up to about 2 mm wiring, and when it is longer than that, the difference between Ts (in) and Ts (out) increases. Ts
(out) increases gradually but slows down,
The increase in Ts (in) is accelerating. On the other hand, the wiring delay initially increases almost linearly, but gradually becomes nonlinear. In other words, the longer the wiring, the more Ts (in)
And Ts (out) becomes large, and although the wiring delay is small, it can be said that the increase is accelerated. The difference between Ts (in) and Ts (out) becomes large because of the wiring resistance, which causes the current to flow less easily due to the resistance (resistance s).
hielding). Therefore, the wiring delay also gradually increases. This effect can be interpreted as a loss of the electric signal due to the wiring resistance. Therefore, the present invention considers inserting a buffer in an area where this effect does not occur. That is, it can be said that the wiring delay can be controlled only by the driving capability of the buffer without considering the wiring resistance.

As shown in FIG. 15A, if Gslew
If >> 1, there is a possibility that wiring resistance is greatly affected. It can be seen from the graph of FIG. 16 that if the gain value Gslew is substantially equal to "1", the effect of the wiring resistance is very small (because the difference between Ts (in) and Ts (out) is small). Therefore, when inserting the buffer, the gain value G
The slew is calculated, and a buffer is inserted at a position where the gain value Gslew approaches “1” as shown in FIG.

Specifically, it takes a long time to calculate the slope of the waveform every time a buffer is inserted. Particularly, in the buffer insertion candidate enumeration step 2d, since a plurality of buffer insertion positions are obtained, the number of combinations increases, and the processing time becomes enormous. Therefore, in the present invention, in order to avoid this, a simple method focusing on the following wiring capacitance is adopted.

First, a pattern when the gain value Gslew becomes substantially "1" is checked in advance. For example, FIG.
When there is a wiring with a fan-out = 1 as shown in (a), the wiring length at which the gain value Gslew becomes substantially “1” is obtained. If the wiring length can be obtained, the approximate value of the wiring capacitance corresponding thereto can be easily obtained. By using this value, candidates for buffer insertion positions are enumerated so as to cut the net in an arbitrary wiring path for each wiring capacitance value. In this case, the position can be obtained only by calculating the path in the wiring while going back from the driven-side cell, and the processing is fast. The gain value Gslew does not need to be strictly set to “1”. As shown in FIG. 16, the gain value Gslew is “1”.
Even if the value is slightly larger, the effect of the wiring resistance is small and “1”
Any value close to is acceptable.

There is also a method that focuses on the wiring resistance. That is, the wiring resistance is obtained for the wiring capacitance, and the net is cut based on the obtained wiring resistance. However, this method works well if fanout = 1, but fanout =
If it is more than 2, it will not work. This is because if there is a branch in the wiring, it is very difficult to define the wiring resistance in the path. Note that the method described here is only an example.
Any heuristic method that can make the gain value Gslew close to “1” can be applied.

[0059]

As described above, according to the present invention, the RC network in which the wiring interval and the wiring width are changed can be taken into account by the RC network enumeration step, and each RC network can be optimized by the changed RC network enumeration step. As a result, it is possible to insert the buffer and change the transistor size, and as a result, it is possible to minimize the delay while simultaneously considering the driving ability, the wiring interval, the wiring width, and the buffer insertion. Therefore, it is possible to obtain a wiring layout result having higher optimumness as compared with the conventional method in which the wiring interval is not considered. In addition, by setting an end condition that restricts the slope of the waveform on the input terminal side during the optimization process,
The secondary effect that the delay can be minimized while ensuring the reliability of the transistor can also be obtained.

In the step of listing the changed RC networks, the delay of the critical path is reduced while dynamically changing the insertion position of the buffer, so that the delay can be further reduced. Further, there is no limitation on the delay calculation method used in the process of this processing.

Further, in the buffer insertion candidate enumeration step in the changed RC network enumeration step, the buffer insertion position candidates are enumerated at intervals that are not easily affected by the wiring resistance. Becomes possible. As a result, since the driving capacity can be used efficiently, the effect of suppressing the number of inserted buffers can be obtained.

[Brief description of the drawings]

FIG. 1 is a conceptual diagram showing an application example of a wiring layout design method according to the present invention.

FIG. 2 is a conceptual diagram showing an example of an initial layout of a wiring pattern.

FIG. 3 is a circuit diagram showing an RC network corresponding to FIG. 2;

FIGS. 4A and 4B are conceptual diagrams showing lines of electric force between conductors for explaining wiring capacitance; FIGS.

FIG. 5 is a graph showing an increase / decrease of a wiring capacity with respect to a change in a wiring interval and a wiring width obtained by a capacitance simulator.

FIG. 6 is a conceptual diagram showing a wiring layout when the wiring width of FIG. 2 is doubled.

FIG. 7 is a circuit diagram showing an RC network corresponding to FIG. 6;

FIG. 8 is a conceptual diagram showing a wiring layout when the wiring interval in FIG. 2 is doubled.

FIG. 9 is a circuit diagram showing an RC network corresponding to FIG. 8;

FIG. 10 is a flowchart showing a procedure of a wiring layout designing method according to the present invention.

11 (a) to 11 (c) are explanatory diagrams showing detailed procedures of a step of listing changed RC networks in FIG. 10;

12 (a) to 12 (c) are explanatory diagrams following FIG. 11 (c).

13 (a) to 13 (e) are explanatory diagrams following FIG. 12 (c).

FIG. 14 is an explanatory diagram regarding the definition of the slope of a signal waveform.

FIGS. 15A and 15B are explanatory diagrams regarding a buffer insertion position.

FIG. 16 is a graph showing increase / decrease of a wiring delay and a signal slew value with respect to a fluctuation of a wiring length.

[Explanation of symbols]

 1 RC network enumeration step 2 Changed RC network enumeration step 2a Delay calculation step 2b Maximum delay path selection step 2c Buffer deletion step 2d Buffer insertion candidate enumeration step 2e Buffer insertion position determination step 2f RC network update step 2g Termination condition determination step 3 Delay minimum RC network selection step 21-24, 31, 40-42 Buffer

Claims (9)

[Claims] 1. A method for designing a wiring layout between functional blocks or between logic cells of a semiconductor integrated circuit, comprising: forming a wiring net in which a specific wiring interval and a wiring width are defined;
Converting to an RC network represented by a resistance component and a capacitance component corresponding to the wiring net, and corresponding to each of a plurality of wiring nets obtained by virtually changing a wiring interval and / or a wiring width of the wiring net. A first step of enumerating the RC networks obtained, and selecting a plurality of buffers having different driving capacities for each of the RC networks obtained in the first step;
And a second step of enumerating RC networks whose path delays have been adjusted by changing the buffer insertion position, and selecting an RC network with the minimum delay from all RC networks obtained in the second step, And a third step of adopting a wiring layout corresponding to the selected RC network. 2. The wiring layout design method according to claim 1, wherein the second step is performed only when the slope of the input signal waveform of the gate in each RC network is suppressed to a certain constraint value or less. A wiring layout design method comprising the step of determining that adjustment has been completed. 3. The wiring layout design method according to claim 1, wherein said second step includes a step of inserting a buffer at a position where a delay of a critical path having a maximum delay is reduced. Layout design method. 4. The wiring layout design method according to claim 1, wherein the second step calculates, for each of the RC networks obtained in the first step, a total path delay on the RC network. Delay calculating step, a maximum delay path selecting step of selecting a critical path having a maximum delay on the RC network, a buffer deleting step of deleting all buffers existing on the critical path, and a buffer on the critical path. A buffer insertion candidate enumeration step for enumerating insertion position candidates; a buffer insertion position deciding step for deciding a buffer insertion position capable of reducing the delay of the critical path from the candidates; and arranging a buffer at the determined position. RC network that updates the RC network A network update step, and an end condition determining step of determining whether the update of the RC network causes a change in a critical path having a maximum delay on the RC network. Repeating a delay calculation step, the maximum delay path selection step, the buffer deletion step, the buffer insertion candidate enumeration step, the buffer insertion position determination step, and the RC network update step. Wiring layout design method. 5. The wiring layout design method according to claim 4, wherein said buffer insertion candidate enumeration step comprises the steps of: includ- ing a signal waveform immediately after an output terminal of a buffer to be inserted and a signal waveform immediately before a next gate connected to said buffer. A step of setting a position at which the ratio with respect to the inclination to be substantially equal to 1 as a candidate for a buffer insertion position. 6. A method for designing a wiring layout between functional blocks or between logic cells of a semiconductor integrated circuit, wherein a certain wiring net is represented by a resistance component and a capacitance component corresponding to the wiring net. First to convert to network
And adjusting the path delay of the RC network obtained in the first step, and reducing the path delay only when the slope of the input signal waveform of the gate in the RC network is suppressed below a certain constraint value. A wiring layout designing method, comprising: a second step in which the adjustment is completed; and a third step of adopting a wiring layout corresponding to the RC network obtained in the second step. 7. A method for designing a wiring layout between functional blocks or between logic cells of a semiconductor integrated circuit, wherein a certain wiring net is represented by a resistance component and a capacitance component corresponding to the wiring net. First to convert to network
And a second step of adjusting a path delay by inserting a buffer at a position for reducing a delay of a critical path having a maximum delay in the RC network obtained in the first step; and And a third step of adopting a wiring layout corresponding to the RC network obtained in the step. 8. A method for designing a wiring layout between functional blocks or between logic cells of a semiconductor integrated circuit, wherein a certain wiring net is represented by a resistance component and a capacitance component corresponding to the wiring net. First to convert to network
And a second step of adjusting a path delay of the RC network obtained in the first step; and a third step of adopting a wiring layout corresponding to the RC network obtained in the second step. The second step is a step of calculating a total path delay on the RC network with respect to the RC network obtained in the first step, and a maximum delay on the RC network. A maximum delay path selecting step of selecting a critical path having, a buffer deleting step of deleting all buffers existing on the critical path, and a buffer inserting candidate enumerating step of enumerating candidates of buffer inserting positions on the critical path A buffer that can reduce the delay of the critical path from among the candidates A buffer insertion position determining step of determining an entry position; an RC network updating step of updating the RC network by placing a buffer at the determined position; and a maximum delay on the RC network by updating the RC network. An end condition determining step of determining whether or not a change in the critical path has occurred, the delay calculating step, the maximum delay path selecting step, and the buffer deleting step until the critical path does not change. A wiring layout design method, wherein the buffer insertion candidate enumeration step, the buffer insertion position determining step, and the RC network updating step are repeatedly executed. 9. A method for designing a wiring layout between functional blocks or between logic cells of a semiconductor integrated circuit, wherein a certain wiring net is represented by a resistance component and a capacitance component corresponding to the wiring net. First to convert to network
And a second step of adjusting a path delay by inserting a buffer into the RC network obtained in the first step; and a wiring corresponding to the RC network obtained in the second step A third step of adopting a layout, wherein the second step is a ratio between a gradient of a signal waveform immediately after an output terminal of a buffer to be inserted and a gradient of a signal waveform immediately before a next gate connected to the buffer. A step of inserting a buffer at a position where is substantially equal to 1.