JP2002313560A - El display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the destruction of an element such as a transistor inside in the case of changing the size of an EL element or placing connection in an open state, and prevent the flicker and non-lighting of the EL element when lowering supply voltage or reducing current consumption. SOLUTION: When boosted voltage VDC applied to the EL element 1 becomes a prescribed set voltage or higher, a voltage detecting circuit 11 allows a control circuit 12 to reverse the polarity of the applied voltage to the EL element regardless of a polarity reversing period set by a driving circuit 9. When the boosted voltage VDC applied to the EL element 1 is less than the prescribed set voltage, the polarity of the applied voltage to the EL element is reversed without fail by the dividing circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to an EL display device including a driving circuit for an EL element, and more particularly to an EL display device using a semiconductor device externally provided with a booster coil or the like.

[0002]

2. Description of the Related Art First, an EL display device using a conventional EL drive circuit will be described. FIG. 4 is a circuit block diagram showing a configuration of an EL display device using a conventional EL drive circuit. In FIG. 4, reference numeral 53 denotes a step-up
A boosting circuit 55 as a boosting signal generating means for generating a voltage to be applied to the L element 51, and 55 indicates a region integrated on a semiconductor substrate.

The booster circuit 53 has a coil 56 having one end connected to the DC power supply 52, a DC terminal (DC in FIG. 4) having an anode connected to the other end of the coil 56, and a cathode connected to the switching circuit 54. , A diode 57 for preventing application of a reverse voltage to the coil 56, a source electrode grounded, and a drain electrode as a main electrode connected to a common connection portion between the coil 56 and the diode 57 ( N-channel MOSFET connected to (CIL in FIG. 4)
And a step-up transistor 58.

[0004] Reference numeral 67 denotes a capacitor, which is connected to the output terminal of the booster circuit 3 for increasing the light emission luminance of the EL element 51. The capacitor 67 is connected to the step-up transistor 8.
The noise synchronized with the switching cycle of the above is also reduced.

[0005] Reference numeral 60 denotes an oscillation circuit that determines the frequency of the switch of the boosting transistor 58. Reference numeral 59 denotes the frequency of the output frequency of the oscillation circuit 60, which is divided and output to the switching circuit 54. This is a frequency dividing circuit that determines the frequency at which the polarity is inverted.

The switching circuit 54 is composed of a high-breakdown-voltage N-channel MOSFET, and charges the polarity inversion transistors 63 and 6 for charging the EL element 51 with a boosted voltage.
5 and polarity inversion transistors 64 and 66 for discharging the EL element 51. A signal for controlling the gate electrode of each of the polarity inversion transistors 63, 64, 65, 66 is determined by an output signal from the frequency dividing circuit 59. There is an inverter 62 for inverting the polarities of signals applied to the gate electrodes of the polarity inversion transistors 63 and 64 and the polarity inversion transistors 65 and 66, respectively.

The gate voltages of the polarity reversing transistors 63 and 64 operate in opposite phases. The gate voltage of the polarity reversing transistor 63 is in phase with the gate voltage of the polarity reversing transistor 66. The voltage is configured to operate in the same phase as the polarity inversion transistor 65.

Next, the operation of the circuit configuration of FIG. 4 will be described with reference to the timing chart of FIG. The frequency of the gate voltage of the boosting transistor 58 is
FIG. 5 shows the time change of the gate voltage V58G.

In FIG. 5, T indicates a cycle of the gate voltage V58G. The voltage V5 applied to the EL element 51
The frequency (for example, about 400 Hz) of the polarity inversion of 1 is determined by the frequency dividing circuit 59. For example, when the frequency dividing circuit 59 is configured to divide by 16, the period of the voltage V51 applied to the EL element 51 is 16 × T.

First, in the period of t = 0 to 8 × T (period a in the figure), the gate voltage V
Since 63 is at a high level, the polarity inversion transistors 63 and 66 are turned on, and the polarity inversion transistors 64 and 65 are turned on.
Turns off. At this time, the terminal name of the EL element 51 is changed as shown in FIG.
As shown in FIG. 5, when the terminal Y is at GND, the terminal X is at the coil 56 and the boost transistor 58.
As a result, the voltage is raised to a voltage VDC of, for example, about 50 to 80 V. In FIG. 5, the voltage V51 applied to the EL element 51 (hereinafter, abbreviated as EL voltage) is based on the terminal Y side of the EL element 51.

Next, in the period of t = 8 × T to 16 × T (period b in the drawing), the output voltage V65 of the inverter 62 applied to the gate of the polarity inversion transistor 65 is at the high level. , The polarity inversion transistors 64 and 65 are turned on, and the polarity inversion transistors 63 and 66 are turned off.
At this time, the boosted EL voltage V51 is discharged by the polarity inversion transistor 64. Contrary to the period a, the terminal X side of the EL element 51 becomes GND, and the terminal Y side is boosted.

As described above, the conventional EL display device is constituted by the EL drive circuit which raises the voltage applied to the EL element 51 at a constant period determined by the frequency dividing circuit 59 and inverts the polarity.

Another conventional example is disclosed in Japanese Patent Application Laid-Open No. 10-7 / 1998.
The EL display device disclosed in US Pat.
A voltage detection circuit for detecting a boost signal output to the element is provided. The polarity of the voltage applied to the EL element is inverted by an output signal from the voltage detection circuit, and the boost signal is supplied to the EL element.

[0014]

However, the configuration of the above-mentioned conventional EL display device has the following problem because the polarity of the voltage applied to the EL element is inverted at a constant period.

First, when the EL element is replaced or the EL element is disconnected for some reason,
Since the capacitance that is much larger than the capacitance of the switch element is lost, and the capacitance is proportional to the voltage, the drain voltage of each switch element composed of a high-voltage transistor increases so as to exceed the withstand voltage of the transistor. In addition, there is a problem that the transistor is broken.

That is, when the EL element is replaced or when the EL element is
When the connection of the elements is disconnected for some reason, the load is only the drain capacitance of the high-breakdown-voltage N-channel MOS transistors 58 and 63 to 66 in FIG.
The capacitance value is several pF to several tens pF, and the EL element 51
Is extremely small as compared with the capacitance value of about 1000 pF or more of
Each high-breakdown-voltage N-channel MOS transistor 58, 63
６６66 are boosted to the drain voltage or more. That is, there is a possibility that the device operates in a state where a voltage higher than the drain withstand voltage is applied to the drain of the high withstand voltage N-channel MOS transistor.

Second, it is necessary to change the frequency condition according to the size of the EL element to be used.
For example, an area of 50 cm ² from the EL element of 10 cm ² E
If you change the L elements, using the same frequency conditions, the voltage applied area to is 50 cm ² EL element, even less drain breakdown voltage of the high voltage N-channel MOS transistor, the area of 10 cm ² EL In the element, EL
Since the capacitance value of the element is reduced to 1/5, the applied voltage is further increased and may exceed the drain withstand voltage of the high withstand voltage N-channel MOS transistor.

The EL display device disclosed in Japanese Patent Application Laid-Open No. 10-79296 can solve the above two problems, but has another problem. That is, when the power supply voltage decreases or when a coil having a large inductance is used to reduce the current consumption, the boosting energy generated by the coil decreases. The voltage does not reach the detection voltage of the detection circuit, the polarity of the voltage applied to the EL element does not reverse, and the EL element does not flicker or light.

An object of the present invention is to prevent the destruction of elements such as internal transistors when the size of the EL element is changed or when the connection is left open.
Further, it is another object of the present invention to prevent the EL element from flickering or not lighting when the power supply voltage is reduced or the current consumption is reduced.

[0020]

To achieve the above object, an EL display device according to the present invention comprises: a booster circuit for boosting a power supply voltage in response to a pulse signal to generate a boosted voltage; A switching circuit that receives the boosted voltage and inverts the polarity of the boosted voltage applied to the EL element, a control circuit that controls the timing of inverting the polarity of the boosted voltage by the switching circuit, and outputs a pulse signal to the boosting circuit. An oscillator circuit, a frequency divider circuit for dividing a pulse signal from the oscillator circuit and outputting the divided signal to a control circuit to set a polarity inversion cycle of the boosted voltage by the switching circuit, and a booster voltage applied to the EL element. A voltage detection circuit for comparing the voltage with a predetermined set voltage and outputting a comparison result to the control circuit and the frequency dividing circuit;

In this EL display device, when the boosted voltage becomes equal to or higher than the predetermined set voltage, the voltage detection circuit applies the voltage applied to the EL element to the control circuit regardless of the polarity inversion cycle set by the frequency dividing circuit. It is preferable to invert the polarity of the voltage.

It is preferable that the predetermined set voltage is set to be equal to or lower than the withstand voltage of the switching elements forming the booster circuit and the switching circuit.

The booster circuit has a coil to which a power supply voltage is supplied at one end and an anode connected to the other end of the coil.
It includes a diode that supplies a boosted voltage from a cathode to a switching circuit, and a boosting switch element that receives a pulse signal from an oscillation circuit and switches energy stored in a coil.

With the above configuration, the voltage detecting circuit detects the boosted voltage generated by the boosting circuit, and when the detected voltage reaches a predetermined set voltage, the control circuit inverts the polarity of the voltage applied to the EL element. E to output a signal
Before the voltage applied to the L element becomes equal to or higher than the breakdown voltage of each transistor in the switching circuit, the polarity of the voltage applied to the EL element can be inverted.

Thus, even when the size of the EL element is changed or the connection of the EL element is disconnected for some reason, each transistor constituting the drive circuit has:
Since a voltage higher than the predetermined voltage is not applied, the transistors are not destroyed.

When the voltage applied to the EL element is lower than the withstand voltage of each transistor in the switching circuit, E
Since the inversion of the polarity of the voltage applied to the L element is determined by the polarity inversion cycle set by the frequency dividing circuit, the polarity of the voltage applied to the EL element is always inverted.

As a result, when the power supply voltage decreases or when a coil having a large inductance is used to reduce the current consumption, the boosting energy generated by the coil decreases. The voltage does not reach the detection voltage of the voltage detection circuit, and the polarity of the voltage applied to the EL element does not reverse so that the EL element does not flicker or does not turn on.

[0028]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing an E as an embodiment of the present invention.
FIG. 3 is a circuit block diagram illustrating a configuration of an EL display device using an L drive circuit.

In FIG. 1, reference numeral 1 denotes an EL element, 2 denotes a DC power supply, and 3 denotes a booster circuit as boosting signal generating means for generating a voltage to be applied to the EL element 1 by boosting the DC power supply 2.
Indicates a region integrated on a semiconductor substrate.

The booster circuit 3 has a coil 6 having one end connected to the DC power supply 2, an anode connected to the other end of the coil 6, and a cathode connected to a DC terminal (DC in FIG. 1) to which the switching circuit 4 is connected. And a diode 7 for preventing a reverse voltage from being applied to the coil 6.
And a source electrode is grounded, and a drain electrode as a main electrode is connected to a common connection portion of the coil 6 and the diode 7 (CI in FIG. 1).
L) and a boosting transistor 8 composed of a high breakdown voltage N-channel MOSFET.

Reference numeral 17 denotes a capacitor, which is connected to the output terminal of the booster circuit 3 for increasing the emission luminance of the EL element 1. The capacitor 17 also reduces noise synchronized with the switching cycle of the boosting transistor 8.

Reference numeral 10 denotes an oscillation circuit, which includes a booster transistor 8
Is determined. Reference numeral 9 denotes a frequency dividing circuit which divides the output frequency of the oscillation circuit 10 and outputs the frequency to the control circuit 12, which will be described later, to determine the frequency at which the polarity of the voltage applied to the EL element 1 is inverted.

Reference numeral 11 denotes a voltage detecting circuit for detecting a boosted voltage from the boosting circuit 3. An input terminal of the voltage detecting circuit is a DC terminal to which the cathode of the diode 7 and the switching circuit 4 are connected.
(DC in FIG. 4), a first output terminal thereof is connected to a control circuit 12 described later, and a second output terminal thereof is connected to the frequency dividing circuit 9.

A control circuit 12 receives an output signal from the frequency dividing circuit 9 or an output signal from the voltage detecting circuit 11, and determines a timing for inverting the polarity of the voltage applied to the EL element 1 to the switching circuit 4. Is output.

The switching circuit 4 is a switch for inverting the polarity of the voltage applied to the EL element 1 and has a high breakdown voltage N
A first polarity inversion transistor 13 composed of a channel type MOS transistor, a second polarity inversion transistor 15, a third polarity inversion transistor 14,
And a transistor 16 for inverting the polarity.

The first polarity inversion transistor 13 and the second polarity inversion transistor 15 each have a drain electrode connected to the cathode of the diode 7 in the booster circuit 3 and a source electrode connected to the first output terminal X and the first output terminal X, respectively. Second
Are connected to the output terminal Y.

The third polarity inversion transistor 14 and the fourth polarity inversion transistor 16 both have a source electrode grounded and a drain electrode of the first polarity inversion transistor 13 and the second polarity inversion transistor 15. Connected to the source electrode, each of the polarity inversion transistors 13 to 16
Are connected to the control circuit 12.

The polarity of the control signal applied to the gate electrodes of the polarity inversion transistors 13 and 15 by the control circuit 12 is opposite to the polarity of the control signal applied to the gate electrodes of the polarity inversion transistors 13 and 16. Are in phase, and the polarity inversion transistors 14 and 1
The polarities of the control signals applied to the gate electrodes 5 operate in phase.

Hereinafter, the operation of the EL display device having the driving circuit configured as described above will be described with reference to FIGS.

FIGS. 2 and 3 are timing diagrams of an EL driving circuit in an EL display device according to an embodiment of the present invention. 2 and 3, V8G indicates the gate voltage of the boosting transistor 8 output from the oscillation circuit 10, VA indicates the gate voltage of the first polarity inverting transistor 13, and VB indicates the second polarity inverting transistor. Transistor 15
VDC indicates the voltage of the DC terminal in FIG. 1 to which the cathode of the diode 7, the switching circuit 4, and the respective terminals of the voltage detection circuit 11 are connected.
Reference numeral 1 denotes a voltage applied to the EL element 1 with reference to the second output terminal Y to the EL element 1.

VDSS is a boost transistor 8,
The drain withstand voltage of the polarity inversion transistors 13 to 16 is denoted by VPEAK, and VPEAK is a detection voltage set by the voltage detection circuit 11. As shown, the detection voltage VPEAK set by the voltage detection circuit 11 is equal to the drain withstand voltage VDS of the step-up transistor 8 and the polarity inversion transistors 13 to 16.
The voltage is sufficiently lower than S.

When the voltage VDC at the DC terminal operates at a voltage lower than the detection voltage VPEAK set by the voltage detection circuit 11, such as when the size of the EL element 1 is large or when the current consumption is reduced, The operation is as shown in FIG.

That is, the frequency of the gate voltage of the boosting transistor 8 is determined by the oscillation circuit 10 and its cycle is set to T
Indicated by The frequency (for example, about 400 Hz) of the polarity inversion of the voltage applied to the EL element 1 is determined by the frequency dividing circuit 9. For example, when the frequency dividing circuit 9 is configured to divide the frequency by 16, a signal is output to the control circuit 12 at a cycle of 16 × T.

Since the voltage VDC at the DC terminal is equal to or lower than the detection voltage VPEAK of the voltage detection circuit 11 in all the periods of FIG. 2, no signal is output from the voltage detection circuit 11 to the control circuit 12 and the output of the control circuit 12 All signals are determined by the output signal from the frequency dividing circuit 9.

First, during the period of t = 0 to 8 × T (period a in the figure), the gate voltage VA of the first polarity inversion transistor 13 is at a high level, so that the first and fourth polarity inversions are performed. Transistors 13 and 16 are turned on, and the second and third polarity inversion transistors 14 and 15 are turned off. At this time, assuming that the terminal names of the EL element 1 are X and Y as shown in FIG. 2, the terminal Y side is GND, and the terminal X side is, for example, 50 to 80 V by the coil 5 and the boosting transistor 8.
The voltage is raised to about VDC.

Next, in the period of t = 8 × T to 16 × T (period b in the figure), the gate voltage VB of the second polarity inversion transistor 15 is at the high level, and the second and third gates are switched.
Are turned on, and the first and fourth polarity inverting transistors 13 and 16 are turned off. At this time,
The boosted EL voltage V1 is discharged by the third polarity inversion transistor 14 and, contrary to the period a, the EL element 1
Terminal X side becomes GND, and the terminal Y side is boosted.

As described above, when the voltage VDC at the DC terminal is equal to or lower than the detection voltage VPEAK of the voltage detection circuit 11, the signal E is generated at a constant period determined by the oscillation circuit 10 and the frequency dividing circuit 9.
The configuration is such that the voltage applied to the L element 1 is increased and the polarity is inverted.

Next, when the size of the EL element 1 is reduced, when the EL element is replaced, or when the connection of the EL element is disconnected for some reason, the period determined by the frequency dividing circuit 9 (FIG. 2).
If the voltage VDC at the DC terminal becomes higher than the detection voltage VPEAK of the voltage detection circuit 11 by 8T), the operation shown in FIG. 3 is performed.

That is, as shown in FIG.
Period until PEAK is reached (period c (c <a =
8T)), the first and fourth polarity inversion transistors 13 and 16 are turned on, and the second and third polarity inversion transistors 14 and 15 are turned off. At this time, of the two output terminals to the EL element 1 shown in FIG. 1, the second output terminal Y becomes GND, and the first output terminal X is boosted by the coil 6 and the boosting transistor 8.

The DC terminal voltage VDC is equal to the detection voltage VPAEK.
, The voltage detection circuit 11 detects the voltage and outputs a signal to the control circuit 12. As a result, the control circuit 12 turns off the first and fourth polarity inversion transistors 13 and 16 and turns on the second and third polarity inversion transistors 14 and 15. At this time, of the two output terminals to the EL element 1 shown in FIG. 1, the first output terminal X becomes GND, the voltage accumulated at the output terminal X is discharged, and the polarity of the voltage applied to the EL element 1 becomes Since it is inverted, the DC terminal voltage VDC becomes constant at the detection voltage VPEAK.

The signal from the voltage detecting circuit 11 is also output to the frequency dividing circuit 9, and all the output signals from the frequency dividing circuit 9 to the control circuit 12 are turned off. In the subsequent periods, the control circuit 12 determines the timing for inverting the polarity of the voltage applied to the EL element 1 based on the output signal from the voltage detection circuit 11.

Next, a period in which a voltage is applied to the second output terminal Y of the EL element 1 (period d, d <b = 8T in FIG. 3).
Then, contrary to the period c, the first and fourth polarity inversion transistors 13 and 16 are turned off, and the second and third polarity inversion transistors 14 and 15 are turned on. At this time, of the two output terminals to the EL element 1 shown in FIG. 1, the first output terminal X becomes GND, and the second output terminal Y is boosted by the coil 6 and the boosting transistor 8.

The voltage detection circuit 11 is composed of a circuit using a Zener diode, a circuit using resistance division, a comparator, or the like. A circuit using a highly accurate and inexpensive Zener diode is preferable. In this case,
Variations in the applied voltage V1 to the EL element 1 can be suppressed to variations in the characteristics of the Zener diode itself.

As described above, according to the present embodiment, the voltage detection circuit 11 monitors that the voltage VDC at the DC terminal is boosted to the predetermined detection voltage VPEAK, and monitors the boosting transistor 8 and the polarity inversion 13 to 16. A predetermined detection voltage VPEA set equal to or lower than the drain withstand voltage of the transistor
When K is detected, the polarity of the voltage V1 applied to the EL element 1 is inverted. Therefore, even if the size of the EL element 1 is changed or the connection of the EL element 1 is disconnected for some reason, the driving circuit is not driven. Is not applied with a voltage equal to or higher than the predetermined detection voltage VPEAK,
The respective transistors are not destroyed.

By the time the voltage VDC at the DC terminal reaches the predetermined detection voltage VPEAK set by the voltage detection circuit 11, the output signal from the frequency dividing circuit 9 is output from the control circuit 1
2, the timing of inverting the polarity of the voltage applied to the EL element 1 is determined by the cycle thereof.
The polarity of the voltage applied to the EL element 1 is always inverted.

For this reason, when the power supply voltage decreases or when a coil having a large inductance is used to reduce the current consumption, the boosting energy generated by the coil decreases. When the voltage does not reach the detection voltage of the voltage detection circuit 11, the EL element 1
The EL element does not flicker or does not stop lighting without inverting the polarity of the voltage applied to the EL element.

[0058]

As described above, according to the present invention,
It is possible to prevent the destruction of elements such as internal transistors when the size of the EL element is changed or when the connection is left open, while reducing the power supply voltage and reducing the current consumption. In this case, it is possible to prevent the EL element from flickering or not lighting.

[Brief description of the drawings]

FIG. 1 is a circuit block diagram of an EL display device according to an embodiment of the present invention.

FIG. 2 is a timing chart of signals of respective parts when the voltage VDC operates at a voltage lower than a detection voltage VPEAK in the EL display device of FIG. 1;

FIG. 3 is a timing chart of signals of respective parts when the voltage VDC reaches the detection voltage VPEAK in the EL display device of FIG. 1;

FIG. 4 is a circuit block diagram of a conventional EL display device.

FIG. 5 is a timing chart of signals of respective parts in the EL display device of FIG. 5;

[Explanation of symbols]

 Reference Signs List 1 EL element 2 DC power supply 3 Boost circuit 4 Switching circuit 5 Area integrated on semiconductor substrate 6 Coil 7 Diode 8 Boost transistor 9 Divider circuit 10 Oscillator circuit 11 Voltage detection circuit 12 Control circuit 13 First polarity inversion Transistor 14 Third polarity inversion transistor 15 Second polarity inversion transistor 16 Fourth polarity inversion transistor 17 Capacitor

Claims (4)

[Claims] A booster circuit for boosting a power supply voltage in response to a pulse signal to generate a boosted voltage; and a switching circuit for receiving the boosted voltage from the booster circuit and inverting the polarity of the boosted voltage applied to an EL element. A control circuit that controls a timing of inverting the polarity of the boosted voltage by the switching circuit; an oscillation circuit that outputs a pulse signal to the boosting circuit; and a circuit that sets a polarity inversion cycle of the boosted voltage by the switching circuit. A frequency divider that divides a pulse signal from the oscillation circuit and outputs the divided signal to the control circuit, and a boosted voltage applied to the EL element is compared with a predetermined set voltage. An EL display device comprising: a voltage detection circuit that outputs to the frequency dividing circuit. 2. The voltage detection circuit according to claim 1, wherein when the boosted voltage becomes equal to or higher than the predetermined set voltage, the control circuit sends the voltage to the EL element regardless of the polarity inversion cycle set by the frequency dividing circuit. 2. The EL display device according to claim 1, wherein the polarity of the applied voltage is inverted. 3. The EL display device according to claim 1, wherein the predetermined set voltage is set lower than a withstand voltage of a switching element forming the booster circuit and the switching circuit. 4. The booster circuit includes: a coil to which a power supply voltage is supplied at one end; a diode having an anode connected to the other end of the coil, for supplying the boosted voltage from a cathode to the switching circuit; 2. The EL display device according to claim 1, further comprising: a boosting switch element that receives a pulse signal from the switch and switches the energy stored in the coil.