JP2002304302A - Optimizing device and optimizing method for microprocessor object code, and recording medium recorded with optimizing program - Google Patents

Abstract

PROBLEM TO BE SOLVED: To relocate data codes in object codes to improve an execution speed of a program even if the data codes are outside a displacement range. SOLUTION: In this optimizing device, a simulator 1 analyzes a data access command in the primary object codes F1. The simulator 1 has a data access information generation part 14 outputting a data address and a size to data access information F3; a data relocation part 15 referring to the data access information F3, sorting the data codes in descending order of an access frequency of each address, selecting the data code of a maximum size in the same address as a selection data code, relocating the selection data codes in the descending order of the access frequency in a cache area and correcting command code; and a secondary object code generation part 16 generating the relocated data and the corrected command code as secondary object codes F4.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a device for optimizing an object code for a microprocessor, an optimizing method, and a recording medium on which an optimizing program is recorded, and more particularly to a device for optimizing an object code for a microprocessor. An apparatus, an optimization method, and an optimization program for a microprocessor purpose code for generating a secondary purpose code for analyzing an instruction code of a primary purpose code to generate an instruction code accessible by one instruction are recorded. It relates to a recording medium.

[0002]

2. Description of the Related Art Conventionally, this kind of optimization processing of an object code for a microprocessor is realized by reading and executing a compiling program or a compiler by a data processing device, and a source program code (primary object code generated by the compiler). Is used to output a target code (secondary target code) for increasing the execution speed of the program corresponding to the microprocessor.

Here, the primary purpose code generated by the compiler means a high-level programming language such as C language, FORTRAN, COBOL translated into a machine language instruction code and data code on a target CPU.

For example, in a pipelined microprocessor, in order to avoid a conflict between instructions and to increase the execution speed of a program, a plurality of instructions that do not depend on each other are interpreted by a compiler using the results of other instructions. There has been proposed an instruction code scheduling method in which an instruction having a short waiting time is automatically arranged before the instruction.

At present, the microprocessor is a CP.
It is common to arrange a high-speed, small-capacity cache memory between the U and the main memory to speed up access to data codes stored in the main memory. However, there still remains a reduction in execution speed due to a cache miss in which the required data code does not exist in the cache. To reduce this reduction in execution speed, the compiler reduces the cache miss penalty during instruction execution. A method of performing instruction scheduling has been devised.

FIG. 13A is a block diagram showing a compiling apparatus which is a conventional apparatus for optimizing an object code for a microprocessor described in Japanese Patent Application Laid-Open No. 10-333916. The conversion device converts the input code F5, which is a compile program recorded on a recording medium, into profile data F2.
And a simulator 100 that compiles the target code F100 to generate the target code F100, and simulates the target code F100 to generate the profile data F2.

The input code F5 is, for example, C language, JA
It is described in a high-level language such as VA (registered trademark) language or FORTRAN language.

[0008] The compiling unit 2 includes a front end 21 which receives the input code F5 and performs lexical analysis and syntax analysis of the input code F5, and a back end 2 which will be described later as software function means for executing the input code F5.
2 is provided.

The back end 22 has a purpose code F100
Profile data F2 which is the simulation result of
A code scheduling unit 221 that schedules instruction codes to minimize the cache miss penalty based on the above, and an object code generation unit that generates an object code F100 executable on the simulator 100 based on the code scheduling result of the code scheduling unit 221. A part 222.

Referring to FIG. 13B, which shows a configuration example of a simulator 100 by blocks,
0 designates an instruction code analyzing unit 11 for analyzing an instruction code of a primary object code F100 which is an object code generated by the compiling unit 2, an instruction simulation unit 12 for executing the analyzed instruction code, and generating profile data. And a profile data generating unit 13 for storing the profile data in the profile data F2.

Next, referring to FIGS. 13A and 13B,
First, the front end 21 of the compiling unit 2 receives the input code F5, performs lexical analysis and syntax analysis of the input code F5, and describes the analysis result. Is supplied to the back end 22.

Next, when the code scheduling section 221 of the back end 22 is set to be valid, the instruction scheduling is performed to minimize the cache miss penalty based on the profile data F2. If it is invalidated, it will not operate and will not execute anything.

In the case of the valid setting, first, the code scheduling unit 221 analyzes the profile data F2 which is a record of the CPU operation obtained by executing the target code F100 by the simulator 100, detects the cache miss penalty occurrence part, The cache operation information to be used by the scheduling execution unit 224 is generated. Next, instruction code rescheduling for reducing cache miss penalty detected based on the cache operation information is performed.

Here, the cache operation information is information indicating whether or not the operation of reading the cache-missed data from the main memory into the cache is performed at each operation clock.

The target code generator 222 receives the result of rescheduling the instruction code by the code scheduler 221, generates a target code executable on the simulator 100, and outputs the target code to the target code F 100.

In the simulator 100, first, the instruction code analyzing section 11 analyzes an instruction code (hereinafter, a primary instruction code) of a target code F100 which is a primary target code generated by the compiling section 2. Next, the instruction simulation unit 12 executes the analyzed primary instruction code. Finally, the profile data generation unit 13 generates profile data and outputs the profile data to the profile data F2.

As described above, in the prior art, the simulator 1
Based on the profile data F2 obtained by executing the above process, a cache miss penalty that reduces the execution speed is analyzed, and a code scheduling process for rescheduling the target code F100 is performed to minimize the cache miss penalty. The code generator 222 generates the final target code F100, and improves the execution speed.

In general, a microprocessor is limited in the displacement (offset) of a data code that can be accessed in a data code access instruction of a machine language instruction. For example, the microprocessor can take only a 16-bit value as a displacement. Can not. For this reason, in the conventional microprocessor object code optimization apparatus, a pointer is set at an arbitrary position in the data code area, and the pointer is stored in a pointer-dedicated register. ) To access the data code area. There is a technique of arranging as many small-sized data codes as possible near the pointer, thereby accessing as many data codes as possible with a single data code access instruction to improve the execution speed.

However, data codes outside the range of accessible data code displacements (hereinafter, data codes outside the displacement range) cannot be accessed by one instruction.
Since a program needs to be accessed by a plurality of instructions, there is a problem that the execution speed is reduced in a program that frequently accesses the data code outside the displacement range.

Next, a data code access instruction can take only a 16-bit value as a displacement (hereinafter, 16-bit displacement).
FIG. 14A showing the data code area for the microprocessor in an explanatory diagram and FIG. 14 showing an example of an instruction code
The reason why the above problem occurs will be described with reference to FIGS.

Referring to FIG. 14A, a pointer P1 shown in FIG. 14A indicates a pointer indicating an arbitrary position in the data code area for accessing the data code area at high speed, and a 16-bit display is provided from the pointer P1. “Sdata” is arranged in the data code area 901 accessible by the statement. For this reason, "Sda
ta ”, as shown in FIG. 14B, the data code access instruction ld. w, the data code access instruction ld. w
4 (A), the value of Sdata stored in the displacement $ Sdata from [gp] indicating the pointer is extracted and stored in the general-purpose register r20.

However, “Data” in FIG.
“Data1” is a data code area 9 that cannot be accessed by a 16-bit displacement from the pointer P1.
00 and 901 respectively, as shown in FIG.
As shown in (1), two instructions are required because they cannot be expressed by the 16-bit displacement specification of the data code access instruction. First, by the instruction movhi, Dat
a, the upper 16 bits of the data code access instruction ld. By using w, the lower 16 bits of the data and the general-purpose register r1 represent a 32-bit displacement, and the value of Data is extracted and stored in the general-purpose register r20. Therefore, the data code areas 900 and 901 that cannot be accessed by the 16-bit displacement
The execution speed of a program that frequently accesses the data code arranged in the program is reduced.

Further, in the prior art, there is a technique capable of designating where in the data code area which data code is to be arranged. However, since there is no means for knowing the access frequency of the data code, efficient access is required. It has been difficult to arrange frequently used data codes in a data code area accessible by 16-bit displacement.

[0024]

The above-described conventional object code optimizing apparatus for a microprocessor, an optimizing method, and a recording medium on which an optimizing program are recorded include an instruction code (hereinafter, referred to as a primary object code) generated by a compiling unit. (Primary instruction code) is analyzed, and then the analyzed primary instruction code is executed. Finally, profile data is generated. Based on the profile data obtained by executing on the simulator, the execution speed is calculated. Analyze the cache miss penalty that reduces the cache miss penalty, perform code scheduling processing to reschedule the target code in order to minimize the cache miss penalty, generate the final target code by the target code generator, and reduce the execution speed. Improved display of accessible data codes Assessments range data code at the (hereinafter, displacement range data code)
In this case, the program cannot be accessed by one instruction but must be accessed by a plurality of instructions. Therefore, in a program in which the frequency of accessing the data code outside the displacement range is high, there is a disadvantage that the execution speed is reduced.

An object of the present invention is to provide an object code optimizing apparatus for a microprocessor which rearranges data codes in an object code even if the data code is out of a displacement range, thereby improving a program execution speed. An object of the present invention is to provide a recording medium recording a method and an optimization program.

[0026]

According to a first aspect of the present invention, there is provided an apparatus for optimizing an object code for a microprocessor, comprising compiling an input code, which is a compile program recorded on a recording medium, using profile data to obtain a primary code. An object code optimization device for a microprocessor, comprising: a compiling unit that generates an object code; and a simulator that simulates the primary object code and generates the profile data, wherein the simulator generates the primary object generated by the compiling unit. Data access information in which the instruction code of the code is analyzed to execute the instruction code corresponding processing, and the number of accesses of the data code by the execution of the instruction code is recorded for each address and the size of the data code to be accessed. Access frequently based on , A secondary purpose code is generated by relocating to the cache area which is a data code area accessible by one instruction, and the instruction code of the secondary purpose code is analyzed to execute the instruction code. Is performed to enable high-speed simulation execution.

According to a second aspect of the present invention, in the apparatus for optimizing an object code for a microprocessor according to the first aspect, the simulator comprises a primary object code or an object code generated by the compiling unit. An instruction code analyzing unit that analyzes an instruction code of one of the secondary objective codes (hereinafter, an objective code) that is the generated objective code; an instruction simulation unit that executes the analyzed instruction code; A profile data generating unit for generating the profile data based on a result of the execution, analyzing a data access instruction in the primary object code, and determining a data access address (hereinafter an address) and a data access size (hereinafter a size) by data access; A data access information generating unit for outputting information, Referring to over data access information to sort the data code in descending order of access frequency of each address,
A data rearrangement unit that selects the maximum size data code at the same address as a selected data code, rearranges the selected data code in the cache area in descending order of the access frequency, and corrects an instruction code; A secondary purpose code generation unit configured to generate the rearranged data and the corrected instruction code as the secondary purpose code by the arranging unit.

According to a third aspect of the present invention, in the apparatus for optimizing an object code for a microprocessor according to the second aspect, the data access information generating section analyzes the data access instruction in the primary object code. A data access instruction analysis unit for detecting the data access address and size, and a data access information output unit for outputting the data address and the data access size detected by the data access instruction analysis unit to the data access information. It is provided with.

According to a fourth aspect of the present invention, in the apparatus for optimizing an object code for a microprocessor according to the second aspect, the data rearrangement unit refers to the data access information in descending order of access frequency for each address. The data to be sorted, the data code having the largest size is selected, the data is rearranged in the cache area in descending order of access frequency, the addresses after the rearrangement are added to the data access information, and the data is output as the rearrangement information. A relocation execution unit that, when the read target code is a data code access instruction and the access address matches the access address before the relocation of the relocation information, sets the access address of the target code after the relocation; And an instruction code correction unit for correcting the instruction code replaced with the address. That.

According to a fifth aspect of the present invention, there is provided a method for optimizing an object code for a microprocessor, comprising: compiling an input code, which is a compile program recorded on a recording medium, by using profile data to generate a primary object code; In a method for optimizing a target code for a microprocessor that simulates the primary target code and generates the profile data, the simulation includes:
The instruction code of the primary purpose code generated by the compilation is analyzed to execute the instruction code corresponding to the execution of the instruction code corresponding process, and the number of times the data code is accessed by executing the instruction code is determined by the address and the access target data code. Detects frequently accessed data codes based on data access information recorded for each size,
A high-speed simulation is performed by rearranging in the cache area which is a data code area accessible by one instruction, generating a secondary purpose code, analyzing the instruction code of the secondary purpose code, and executing the instruction code. It is characterized in that it can be executed.

According to a sixth aspect of the present invention, there is provided a method for optimizing an object code for a microprocessor, comprising: compiling an input code which is a compile program recorded on a recording medium by using profile data to generate a primary object code; In the method for optimizing a target code for a microprocessor that simulates the primary target code and generates the profile data, an instruction code analyzing step of analyzing an instruction code of the primary target code; and executing the analyzed primary instruction code. An instruction simulation step to perform, a profile data generation step to generate the profile data based on a result of the execution of the primary instruction code, and an analysis of a data access instruction in the instruction code to determine an access address and an access size of data. Detect A data access information generating step of storing the access address and the access size of the detected data in data access information, and the number of accesses of the data code generated in the data access information generating step for each of the access address and the access size. Based on the recorded data access information, the data code is detected in the descending order of the access frequency, and is relocated to the cache area, which is a data code area accessible by one instruction, in the descending order of the access frequency to correct the instruction code. And a secondary object code generating step of generating the object code corrected in the data rearrangement step as a secondary object code.

According to a seventh aspect of the present invention, in the method for optimizing an object code for a microprocessor according to the fifth aspect, the instruction code analyzing step includes the step of compiling the object code as an input of the simulation by the compiling. A primary / secondary objective code determining step of determining whether the primary objective code is the generated primary objective code or the secondary objective code generated by the simulation; and If it is a primary purpose code, a primary purpose code analysis step for analyzing the instruction code of the primary purpose code, and if the primary purpose code is the secondary purpose code in the primary / secondary purpose code determination step, the primary purpose code is analyzed. And a secondary purpose code analyzing step of analyzing the instruction code.

According to an eighth aspect of the present invention, in the method of optimizing an object code for a microprocessor according to the sixth aspect, the data access information generating step analyzes the data access instruction in the instruction code. A data access instruction analyzing step of detecting the data access address and the access size of the data access instruction, and outputting the detected data access address and the access size to the data access information;
Outputting a data access information for incrementing the number of accesses in the data access information.

According to a ninth aspect of the present invention, in the method of optimizing an object code for a microprocessor according to the sixth aspect, the data relocation step refers to the data access information to determine an access frequency for each address. The data code having the maximum access size is selected as the selected data code by sorting the data codes in descending order of the data size, the selected data code is rearranged in the cache area in the descending order of the access frequency, and the address after the rearrangement is set to the data access A data relocation execution step of adding the information to each piece of information and outputting as relocation information; reading the object code one instruction code at a time; If the previous access address matches, the matched data code access It is characterized in that it has an instruction code correction step of correcting the instruction code by replacing the access address of the scan instruction access address after placement.

The invention according to claim 10 is the same as that in claim 8
In the method for optimizing an object code for a microprocessor according to the above, the data access instruction analyzing step determines whether the data access instruction in the instruction code is a data access instruction, and determines whether the data access instruction is a data access instruction. A data access instruction determining step for proceeding to an instruction code end determining step; and an address size extracting step for extracting the data access address and the access size in the data access instruction if the data access instruction determining step is the data access instruction. An entry search step for searching for an entry in the data access information corresponding to the data access address and the access size extracted in the address size extraction step; and an entry corresponding to the data access information. If there is a corresponding entry, the corresponding entry presence count determining step proceeds to the corresponding entry access count increment step, the corresponding entry access count increment step increments the access count of the corresponding entry, and If there is no corresponding entry, a new entry adding step of adding the data access address and the access size entry extracted in the address size extracting step to the data access information, and determining whether the end of the instruction code is reached. A determination is made, and if not completed, the process returns to the instruction code analysis step, and if completed, the process proceeds to a data rearrangement step.

The invention according to claim 11 is the invention according to claim 9
In the method for optimizing an object code for a microprocessor according to the above, the data relocation execution step includes a step of sorting the data codes in descending order of access frequency for each address based on the data access information to generate sort data. A data fetching step of fetching data codes in descending access frequency order from the sorted data, and a maximum size for searching for a data code having a maximum access size among the data codes having the same address as the fetched access address and selecting the data code as a selected data code An entry search step, a cache area moving step of moving the selected data code to the cache area, a rearrangement information output step of adding a post-placement address to the data access information and outputting it as relocation information, It is determined whether or not there is an empty area in the cache area. If the empty area in the cache area still remains, the process proceeds to a data end determination step described later. Proceeding to a step, there is no free cache area determination step, and if all the addresses of the sort data are completed, proceed to the instruction code correction step; if not, return to the data fetching step and repeat the above processing. The data end determination step, and move the data code of the remaining access address of the sorted data to a non-cache area that is a low-speed accessible data code area, and output the relocation information to the relocation information; Moving the non-cache area to the instruction code correcting step. And it is characterized in Rukoto.

The invention according to claim 12 is the invention according to claim 9
In the method for optimizing an object code for a microprocessor according to the above, the instruction code correcting step includes: an instruction code extracting step of extracting one instruction code from the primary object code; and determining whether the instruction code has been read to the end. When the instruction code to be read is read, the operation is terminated. If there is still an instruction code to be read, an instruction code end determination step proceeds to an access instruction determination step described later. If it is not a code access instruction, the process returns to the one instruction code fetching step, and if the instruction code is the data code access instruction,
An access instruction determining step for proceeding to a next match search step; and a matching entry for searching the relocation information, wherein an access address of the data code access instruction matches an address before arrangement in the relocation information. If the match entry is found in the match search step and the match search step, the process proceeds to the next replacement step, returns to the one instruction code extraction step, and repeats the above processing. When a matching entry is not found, the method returns to the one instruction code fetching step, and includes a matching determining step of repeating the above processing, and a replacing step of replacing an address of a data code access instruction with a post-arrangement address of the matching entry. It is characterized by the following.

The thirteenth aspect of the present invention provides the ninth aspect.
In the method for optimizing an object code for a microprocessor according to the above, the data relocation execution step includes a step of sorting the data codes in descending order of access frequency for each address based on the data access information to generate sort data. A data fetching step of fetching a data code in descending access frequency order from the sorted data; and a maximum size for searching for a data code having a maximum access size among the data codes having the same address as the fetched access address and selecting the data code as a selected data code. An entry search step and a determination as to whether there is no empty area in the cache area, and if an empty area in the cache area still remains, proceed to a cache area moving step described below, and if there is no empty area in the cache area, Non-keys described later Determining that there is no free cache area, proceeding to a cache area moving step, moving the selected data code to the cache area, and moving the data code of the remaining access address of the sorted data at a low speed. A non-cache area moving step of moving to a non-cache area which is a code area; a rearrangement information output step of adding a post-placement address to the data access information and outputting it as relocation information; If it is completed, the process proceeds to the instruction code correction step, and if not all the addresses are completed, the process returns to the data fetching step, and the data end determining step of repeating the above processing is provided.

The invention according to claim 14 is the invention according to claim 9
In the method for optimizing an object code for a microprocessor according to the above, the instruction code correcting step is a step of retrieving one entry from the relocation information, and determining whether or not the search is performed up to the end of the relocation information. If it is the end of the relocation information, the process is terminated. If the end of the relocation information is not the end, the process proceeds to the next first instruction code fetching step. The first one instruction code fetching step of fetching an instruction code; and if the instruction code read in the one instruction code fetching step is not the data code access instruction, the process returns to the one instruction code fetching step, and the instruction code is If it is the data code access instruction, go to the next post-placement address replacement step. An access instruction determining step; searching the relocation information for a matching entry in which the access address of the data code access instruction matches the pre-placement address in the relocation information; The post-placement address replacement step of performing a replacement process to a second instruction code extracting step of extracting one instruction code from the primary target code, and determining whether or not the instruction is completed. The method further comprises an instruction code end determining step of returning to the access instruction determining step, repeating the following processing, and returning to the relocation information extracting step if it is completed, and repeating the following processing.

According to a fifteenth aspect of the present invention, there is provided a recording medium on which a program for optimizing an object code for a microprocessor is compiled, wherein an input code which is a compile program is compiled using profile data to generate a primary object code. In a recording medium storing a microprocessor object code optimization program that simulates a primary object code and generates the profile data, the simulation analyzes an instruction code of the primary object code generated by the compilation, and executes the instruction code. An instruction code is executed, which is the execution of the code-corresponding process, and the number of accesses to the data code by the execution of the instruction code is determined based on data access information recorded for each address and the size of the data code to be accessed. By relocating to the cache area, which is a data code area accessible by one instruction, to generate a secondary purpose code, analyze the instruction code of the secondary purpose code, and execute the instruction code. ,
It is characterized in that a high-speed simulation can be executed.

According to a sixteenth aspect of the present invention, there is provided a recording medium on which a program for optimizing an object code for a microprocessor according to the present invention is recorded. An instruction code analyzing step of analyzing an instruction code of the primary object code on a recording medium storing an optimization program of an object code for a microprocessor that simulates a primary object code and generates the profile data; and the analyzed primary instruction. An instruction simulation step for executing the code, a profile data generation step for generating the profile data based on a result of the execution of the primary instruction code, and a data access instruction in the instruction code is analyzed to access the data. Address and the access size of the detected data, and storing the access address and the access size of the detected data in data access information, and the number of accesses of the data code generated in the data access information generating step is The data code is detected in descending order of access frequency based on the access address and the data access information recorded for each access size, and is rearranged in a cache area which is a data code area accessible by one instruction in descending order of access frequency. A data rearrangement step of correcting an instruction code; and a secondary object code generation step of generating the object code corrected in the data rearrangement step as a secondary object code.

[0042]

Next, embodiments of the present invention will be described in detail with reference to the drawings.

The apparatus and method for optimizing the object code for a microprocessor according to the present embodiment compiles an input code, which is a compile program recorded on a recording medium, using profile data to generate a primary object code. And a simulator that simulates the primary object code and generates the profile data, wherein the simulator has an instruction code of the primary object code generated by the compiling unit. And executes the instruction code corresponding to the execution of the instruction code corresponding processing. The access frequency based on the data access information recorded for each address and the size of the data code to be accessed by the execution of the instruction code. High Data code is detected and rearranged in a cache area, which is a data code area accessible by one instruction, to generate a secondary purpose code, analyze the instruction code of the secondary purpose code, and execute the above instruction code. Thus, a high-speed simulation can be performed.

Here, the primary purpose code generated by the compiler means a high-level programming language such as C language, FORTRAN, COBOL translated into a machine language instruction code and data code on a target CPU.

A data code area that can be accessed by one instruction, that is, a cache area is not only a general cache memory (hereinafter, cache), but also a 16-bit pointer P1 described in FIG. It means a data code storage area such as a displacement range area 901.

Next, referring to FIG. 2 (A), which shows the embodiment of the present invention in the same manner as FIG. The object code optimizing device for a microprocessor according to the present embodiment compiles an input code F5, which is a compile program recorded on a recording medium, using profile data F2 to generate a primary object code F1. And a simulator 1 that is a machine or a simulator that simulates the primary purpose code F1 to generate profile data F2 and generates the secondary purpose code F4.

The simulator 1 analyzes the primary instruction code read from the primary purpose code F1, simulates the execution of the instruction code of the primary instruction code, generates profile data F1, and accesses the data code with the execution of the instruction code. Is generated for each address and access size, a data code having a high access frequency is detected based on the data access information F3, and is rearranged in a data code area accessible by one instruction. A purpose code F4 is generated.

The input code F5 is, for example, C language, JA
It is described in a high-level language such as a VA language or a FORTRAN language.

The compiling unit 2 includes a front end 21 which receives the input code F5 and performs lexical analysis and syntax analysis of the input code F5, and a back end 2 which will be described later, as software function means for executing the input code F5.
2 is provided.

The back end 22 has a primary purpose code F1
/ A code scheduling unit 221 for scheduling instruction codes to minimize cache miss penalty based on profile data F2, which is a simulation result of the secondary purpose code F4, and a simulator 1 based on the code scheduling result of the code scheduling unit 221. And a target code generation unit 222 that generates a primary target code F1 that can be executed above.

Referring to FIG. 2B, which shows a block diagram of an example of the configuration of the code scheduling section 221, the code scheduling section 221 analyzes profile data F2, which is a simulation result of the primary target code F1, and generates a cache miss penalty generating portion. And a code for rescheduling an instruction code for reducing cache miss penalty detected based on the cache operation information, and a profile data analysis unit 223 for outputting cache operation information for use by the code scheduling execution unit 224. A scheduling execution unit 224.

Here, the cache operation information is information indicating whether or not the operation of reading the cache-missed data from the main memory into the cache is performed at each operation clock.

Simulator 1 characterizing the present embodiment
FIG. 1A, in which the same components as those in FIG. 13B are denoted by the same reference characters / numbers as in FIG. Primary purpose code F1 which is a code or simulator 1
The instruction code analyzing unit 11 analyzes the instruction code of the secondary object code F4 generated by the program (hereinafter, the case where both the primary and secondary object codes are referred to as the object code FX), and executes the analyzed instruction code. Instruction simulation unit 1
2 and a profile data generating unit 13 that generates profile data and stores the profile data in a profile data file F2 (hereinafter, the file is omitted unless otherwise specified, and is referred to as, for example, profile data F2). The data access instruction in the primary purpose code F1 is analyzed, and the data access address (hereinafter, the address) and the data access size (hereinafter, the size: the data access address and the data access size are abbreviated as the data address and the size) are described in data access information F3 The data codes are sorted in the order of decreasing access frequency (descending order) for each address with reference to the data access information generating unit 14 and the data access information F3, and the data code of the maximum size at the same address is selected. As a single instruction A data rearrangement unit 15 for rearranging selected data codes in an accessible data code area (hereinafter referred to as a cache area) in descending order of access frequency and correcting an instruction code; data rearranged by the data rearrangement unit 15 and corrected instructions A secondary purpose code generation unit 16 that generates a code as a secondary purpose code F4.

Referring to FIG. 1B, which shows the configuration of the data access information generation unit 14 by blocks, the data access information generation unit 14 analyzes the data access instruction in the primary purpose code generated by the compilation unit 2. Data access instruction analysis unit 1 for detecting addresses and sizes
41, and a data access information output unit 142 that outputs the data address and size detected by the data access instruction analysis unit to the data access information F3.

Referring to FIG. 1C, which shows the configuration of the data rearrangement section 15 by blocks,
Refers to the data access information F3, sorts the data codes in descending order of access frequency for each address, selects the data code of the maximum size, rearranges them in the cache area in order of access frequency, and performs data access for the relocated addresses. A data relocation execution unit 151 that adds the information to the information F3 and outputs it as relocation information;
Is a data code access instruction, and when the address (of the target code FX) matches the address before the relocation of the relocation information, the access of the target code is replaced with the address after the relocation, and the instruction code correction for correcting the instruction code And a unit 152.

Next, the operation of the present embodiment will be described with reference to FIG. 1 and FIG. 2 and FIG. 3 which is a flowchart showing the processing of the simulator 1 of the present embodiment. 21 is an input code F5
And analyzes the lexical and syntax of the input code F5, and supplies the analysis result to the back end 22.

Next, the code scheduling section 221 of the back end 22, when enabled, performs instruction code scheduling based on the profile data F2 to minimize cache miss penalty. If it is invalidated, it will not operate and will not execute anything.

In the case of the valid setting, first, the profile data analysis unit 223 of the code scheduling unit 221
CPU obtained by executing target code FX on simulator 1
The profile data F2, which is a record of the operation, is analyzed to detect a cache miss penalty occurrence portion, and at the same time, outputs cache operation information to be used by the code scheduling execution unit 224 and supplies it to the code scheduling execution unit 224. Next, the code scheduling execution unit 224 reschedules the instruction code for reducing the cache miss penalty detected by the profile data analysis unit 223 based on the supplied cache operation information.

The target code generator 222 receives the result of the instruction code rescheduling by the code scheduling executor 224, generates a target code executable on the simulator 1, and outputs the target code to the primary target code F1.

In the simulator 1, first, the instruction code analyzing unit 11 analyzes the instruction code of the primary purpose code F1 generated by the compiling unit 2 (hereinafter, the primary instruction code) (instruction code analyzing step S1). Next, the instruction simulation unit 12 executes the analyzed primary instruction code (instruction simulation step S2). Next, the profile data generation unit 13 generates profile data based on the execution result of the primary instruction code, and outputs the profile data to the profile data F2 (profile data generation step S3). The processing so far is the same as the conventional processing.

Next, the data access information generation unit 14
The data access instruction in the instruction code is analyzed, the address and size of the data are detected, and the address and size of the detected data are stored in the data access information F3 (data access information generation step S4).

First, the data access instruction analyzer 141
Analyzes the data access instruction in the instruction code, and detects the data address and size of the data access instruction (data access instruction analysis step S41). Next, the data access information output unit 1
42 outputs the data address and size detected by the data access instruction analysis unit 141 to the data access information F3 when the valid setting is made, and increments the number of accesses in the data access information F3 (data access information output step S42). .

FIG. 7 is an explanatory diagram showing an example of the contents of data access information F3 generated by data access information generating section 14.
Referring to (A), this data access information is composed of “address”, “access size”, and “access count”. Here, “address” indicates the storage address of the data code at the time of access, “access size” indicates the size of the data code at the time of access,
The “access count” indicates the access count of the data code.

When the data relocation unit 15 is set to be valid, the access frequency of the data code generated by the data access information generation unit 14 is determined based on the data access information F3 recorded for each address and access size. Data code is detected in descending order,
The instruction code is rearranged in the data code area accessible by the instruction, that is, the cache area in descending order of access frequency to correct the instruction code (data rearrangement step S5).

In the data relocation step S5, first,
In the data relocation execution unit 151, the data access information F3
, Sort the data codes in descending order of access frequency for each address, select the data code of the maximum access size as the selected data code, and rearrange the selected data code in the cache area in descending order of access frequency,
The addresses after the rearrangement are added to the data access information F3 and output as the rearrangement information (data rearrangement execution step S51). FIG. 7B shows a description example of the relocation information.

Next, the instruction code correction unit 152 reads the target code FX one instruction code at a time, and the target code FX is a data code access instruction, and its address matches the address of the relocation information before relocation. If
The instruction code is corrected by replacing the address of the matched data code access instruction with the address after arrangement (instruction code correction step S52).

The secondary purpose code generator 16 generates the target code corrected by the instruction code corrector 15 as a secondary target code F4 (secondary target code generation step S4).
6).

The data access command analysis step S41 of the data access command analysis section 141 and the data access information output step S42 of the data access information output section 142
The detailed process of the data access information generation step S4 will be described with reference to FIG. 4 which shows each process in a flowchart. The data access command analysis step S41 first includes a data access command determination step S411 and an instruction simulation It is determined whether the instruction code executed by the unit 12 is a data access instruction. If it is a data access instruction, the process proceeds to the next address size fetching step S412. If it is not a data access instruction, the process proceeds to an instruction code end determination step S425.

Next, address size extracting step S
At 412, the data address and the size in the data access instruction are extracted.

Next, the corresponding entry search step S421
In step S412, an entry in the data access information F3, which is the direct access storage data inside the device, corresponding to the data address and size extracted in the address size extraction step S412 is searched.

Next, the corresponding entry existence determination step S4
If there is a corresponding entry in the data access information F3 which is the direct access storage data at 22, the process proceeds to the corresponding entry access count increment step S423. Corresponding entry access count increment step S423
Then, the access count of the corresponding entry is incremented. If there is no corresponding entry in the data access information in the corresponding entry existence determination step S422, the process proceeds to a new entry adding step S424, and a new entry of the data address and size extracted in the address size extracting step S412 is added to the data access information F3. .

Finally, instruction code end determination step S4
At 25, it is determined whether or not the end of the instruction code is reached,
If not, the process returns to the instruction code analysis step S1.
If completed, the process proceeds to the data relocation step S5.

Next, the respective processes of the data relocation execution step S51 of the data relocation execution section 151 and the instruction code correction step S52 of the instruction code correction section 152 will be described with reference to FIGS. The detailed processing of the data relocation step S5 will be described below.
First, in a data rearrangement execution step S51, in a data sort step S511, based on the data access information F3, the data codes are sorted in the order of decreasing access frequency for each address (descending order) and output to the sort data F6.

Next, a data fetching step S512
Then, the data codes are extracted from the sort data F6 in descending order of the access frequency, and the maximum size entry search step S
In step 513, the data code having the maximum access size is searched and selected from among the data codes of the same address as the extracted address, and this data code is moved to the cache area which is a data area accessible by one instruction in the cache area moving step S514. And relocation information output step S5
At 15, an address is added to the data access information after the arrangement,
Output as relocation information F7. FIG. 7B is an explanatory diagram showing an example of the relocation information F7.

Next, in the step S516 of determining that there is no free cache area, if there is still an empty area in the cache area, the process proceeds to a data end determination step S518. Proceeding to S52, if all addresses are not completed, the process returns to the data fetching step S512, and the above processing is repeated.

If there is no free space in the cache area in step S516 of determining that there is no free cache area, the flow advances to step S517 to move the remaining data to the data code area where the data code of the remaining address of the sort data can be accessed only at low speed. , And outputs the relocation information to the relocation information F7, and proceeds to the instruction code correction step S52.

In the instruction code correction step S52, first, in one instruction code extraction step S521, one instruction code is extracted from the primary purpose code F1.

Next, an instruction code end determination step S52
In step 2, it is determined whether the instruction code has been read to the end. If the instruction code has been read to the end, the instruction code correction step S52 ends, and the process proceeds to the secondary purpose code generation step S6.

In the instruction code end determination step S522,
If there is still an instruction code to be read, the process proceeds to an access instruction determination step S523. In the access instruction determination step S523, if the instruction code read in the one instruction code fetch step S521 is not a data code access instruction, the one instruction code fetch step S521
Returning to 521, the next instruction code is read. If the instruction code is a data code access instruction, the process proceeds to a match search step S524 to search the relocation information F7 and find an entry in which the address of the data code access instruction matches the pre-arrangement address in the relocation information F7. look for.

Finally, in the match determination step S525,
If a matching entry that is a matching entry is found in the matching search step S524, the process proceeds to the replacing step S526, where the address of the data code access instruction is replaced with the address after the arrangement of the matching entry, and the process returns to the one instruction code extracting step S521. Is repeated. If no matching entry is found in the matching search step S524, the process returns to the one instruction code extracting step S521, and the above processing is repeated.

For example, in the apparatus for optimizing the object code for a microprocessor according to the present embodiment, like the code example of the union in the C language as shown in FIG. When compiling the input code to be accessed, the data access information F3 is as shown in FIG. 12B. In the data code of the same address, the number of accesses of the small-size data code is changed to the access number of the large-size data code. May be more than the number of times.

In this case, in the data rearrangement step S5, the data code having a high access frequency is prioritized for rearrangement. Therefore, the 2-byte data code of number 2 is to be rearranged. Since the data code area is accessed even with the 4-byte data code of number 1, the 4-byte data code is not divided so that
The 4-byte data code of number 1, which is the maximum access size, is selected as a relocation target. That is, when the same data area is accessed but the access size is different, the data code area is rearranged using the data code accessed with the larger access size as one unit.

As described above, the simulator 1 characterizing the present embodiment comprises the data access information generator 1
4 generates the data access information F3, and the data rearrangement unit 15 rearranges the frequently accessed data in the cache area. Therefore, the object code generated by the secondary object code generation unit 6 is regenerated on the simulator 1 again. In the case of execution, access to a data code area having a high access frequency is accelerated, and the execution speed of a program is improved.

Particularly, when the loop processing is performed on the data code in the data code area, there is a remarkable effect. For example, in an example of a program that requires 100 loops to initialize a value in a certain data code area to 0, if the data code area is a target code that can be accessed by one instruction instead of two instructions, The execution time of the program is improved by the execution time.

Next, the processing of the data access information generating step S4A characterizing the second embodiment of the present invention is similarly shown by a flowchart with common reference characters / numerals added to components common to FIG. Referring to FIG. 8, the difference between the data access information generation step S4A of the present embodiment shown in FIG. 8 and the data access information generation step S4 of the first embodiment described above is the internal direct access storage data. Has external data access information F3A which is an external storage device instead of the data access information F3,
It has a corresponding entry search step S421A for searching the external data access information F3A instead of the corresponding entry search step S421.

The processing of the data access information generation step S4A of the present embodiment will be described with reference to FIG. 8 focusing on the differences from the first embodiment. The data access instruction analysis step S411 and the address size extraction Step S412 performs the same process as in the first embodiment. That is, it is determined in step S411 whether the instruction is a data access instruction, and in step S412, the address and size in the data access instruction are extracted.

Next, the corresponding entry search step S421
In A, an entry in the external data access information F3A, which is external storage data corresponding to the extracted data address and size, is searched.

Hereinafter, the corresponding entry existence determination step S4
22, the corresponding entry access count increment step S423, the new entry addition step S424, and the instruction code end determination step S425 perform the same processing as in the first embodiment.

Next, the process of the data rearrangement execution step S51A characterizing the third embodiment of the present invention is similarly shown by a flowchart with the same reference characters / numerals as those of FIG. Referring to FIG. 9, the data relocation execution step S51 according to the first embodiment of the data relocation execution step S51A according to the embodiment shown in FIG.
The difference from the first embodiment is that the maximum size entry search step S
After 513, there is no free cache area determination step S
516 and free cache area absence determination step S51
If there is a free cache area in step 6, the cache area is moved to the cache area.
And a non-cache area move step S517 for moving data to a non-cache area which is an area other than the cache area when there is no free cache area, and relocation after the cache area move step S514 and the non-cache area move step S517 Information output step S515
And performing the data end determination step S517.

With reference to FIG. 9, the processing of the data relocation execution step S51A of this embodiment will be described focusing on the differences from the first embodiment. First, in the data sorting step S511, the data access is executed. The data codes are sorted in descending order of the access frequency for each address based on the information F3, and output to the sorted data F6. Next, in a data fetching step S512, data codes are fetched from the sort data F6 in descending order of access frequency, and in a maximum size entry search step S513, a data code having a maximum access size is searched in a data code having the same address as the fetched address. select.

Next, in the step S516 of determining that there is no free cache area, if a free cache area still remains, the process proceeds to the cache area moving step S514, in which the maximum size entry search step S513 is selected. The data code is moved to the cache area. If there is no free cache area, the process proceeds to the non-cache area moving step S517, and the data code selected in the non-cache area moving step S517 is moved to the non-cache area.

In the same manner as in the first embodiment, in the relocation information output step S515, the post-placement address is added to the data access information, and the data is output as relocation information, and the end determination is made in the data end determination step S518. .

Next, the process of the instruction code correcting step S52A characterizing the fourth embodiment of the present invention is shown in the same flowchart as FIG. 6 with common components being denoted by common reference characters / numerals. 10, the difference from the first embodiment will be mainly described. The instruction code correction step S52A of the present embodiment shown in FIG.
In the relocation information extracting step S527, the relocation information F7
Fetch one entry from

Next, relocation information end determination step S52
At 8, it is determined whether or not the search has been performed up to the end of the relocation information F7. If the search has been completed, the process ends, and the process proceeds to the secondary purpose code generation step S6. Relocation information F7
If it is not the end, one instruction code fetching step S5
Proceed to 21.

Next, one instruction code extracting step S5
At 21, one instruction code is extracted from the head of the primary purpose code F1.

Next, an access instruction determination step S523
If the instruction code read in one instruction code fetching step S521 is not a data code access instruction,
Returning to one instruction code fetching step S521, the next instruction code is read. If the instruction code is a data code access instruction, the post-placement address replacement step S53
0, searching the relocation information for a matching entry in which the access address of the data code access instruction matches the pre-placement address in the relocation information, and replaces the matching entry with the post-placement address. Do.

Next, one instruction code extracting step S5
At 31, the next instruction is fetched from the primary purpose code.

Finally, instruction code end determination step S5
At 22, it is determined whether or not the instruction is completed. If not, the process returns to the access instruction determination step S523,
The following processing is repeated. If the instruction has ended, the process returns to the relocation information extracting step S527 and the following processing is repeated.

Next, referring to FIG. 11 which is a flowchart showing the processing of an instruction code analyzing step S1 characterizing the fifth embodiment of the present invention, the instruction code analyzing step S1 is executed by the input of the simulator 1 (input of the simulation). ) Is determined as the primary target code F1 generated from the result of compilation by the compiling unit 2 or the secondary target code F4 generated by the simulator 1 (primary / secondary target). Code determination step S11).

Next, if it is the primary purpose code F1 generated by the compiling unit 2, the process proceeds to the primary purpose code analysis step S12, where the instruction code of the primary purpose code F1 is analyzed.

If it is the secondary purpose code F4 generated from the simulator 1, the process goes to the primary purpose code analyzing step S13 to analyze the instruction code of the secondary purpose code F4.

[0102]

As described above, the optimizing apparatus, the optimizing method, and the recording medium storing the optimizing program for the object code for the microprocessor of the present invention are provided by the simulator characterizing the present invention, which is generated by the compiling section. Analyzes the instruction code of the primary purpose code, executes the instruction code corresponding to the execution of the instruction code corresponding processing, and records the number of accesses of the data code by the execution of the instruction code for each address and the size of the data code to be accessed. A data code having a high access frequency is detected based on the access information, rearranged in a cache area which is a data code area accessible by one instruction, a secondary purpose code is generated, and an instruction code of the secondary purpose code is analyzed. And execute the above instruction code to access the data code area with high access frequency. Access can speed up, there is an effect that the execution speed of the program is improved.

Particularly, when the loop processing is performed on the data code in the data code area, there is a remarkable effect. For example, in an example of a program that requires 100 loops to initialize a value in a certain data code area to 0, if the data code area is a target code that can be accessed by one instruction instead of two instructions, The execution time of the program is improved by the execution time.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a simulation device that characterizes a device for optimizing an object code for a microprocessor according to a first embodiment of the present invention.

FIG. 2 is a block diagram illustrating an apparatus for optimizing an object code for a microprocessor according to an embodiment;

FIG. 3 is a flowchart illustrating an example of a simulation method that is a processing operation of the simulation apparatus according to the present embodiment.

FIG. 4 is a flowchart showing a detailed process of a data access instruction analysis process of FIG. 3;

FIG. 5 is a flowchart showing a detailed process of a data relocation process by the data relocation unit 15 of FIG. 3;

FIG. 6 is a flowchart showing a detailed process of a data relocation process by a data relocation unit.

FIG. 7 is an explanatory diagram illustrating an example of relocation information.

FIG. 8 is a flowchart illustrating a detailed process of a data access information generation unit characterizing the second embodiment of the present invention.

FIG. 9 is a flowchart showing a detailed process of a data access information analysis unit characterizing the third embodiment of the present invention.

FIG. 10 is a flowchart illustrating a detailed process of a code correction processing unit characterizing a fourth embodiment of the present invention.

FIG. 11 is a flowchart illustrating a detailed process of an instruction code analyzing unit characterizing a fifth embodiment of the present invention.

FIG. 12 is an explanatory diagram showing an example of data access information of a union code in C language.

FIG. 13 is a block diagram showing an example of a conventional object code optimization device for a microprocessor.

FIG. 14 is an explanatory diagram showing an example of a data code area and an instruction code for a microprocessor which can take only a 16-bit value as a displacement of a data code access instruction.

[Explanation of symbols]

 1,100 Simulator 2 Compiling unit 11 Instruction code analysis unit 12 Instruction simulation unit 13 Profile data generation unit 14 Data access information generation unit 15 Data relocation unit 16 Secondary purpose code generation unit 21 Front end 22 Back end 141 Data access instruction analysis Unit 142 Data access information output unit 151 Data relocation execution unit 152 Instruction code correction unit 221 Code scheduling unit 222 Object code generation unit 223 Profile data analysis unit 224 Code scheduling execution unit F1 Primary object code F2 Profile data F3, F3A Data access information F4 Secondary purpose code F5 Input code F6 Sort data F7 Positioning information F100 Purpose code

Claims (16)

[Claims] 1. A compiling section for compiling an input code, which is a compiling program recorded on a recording medium, using profile data to generate a primary purpose code, and simulating the primary purpose code to generate the profile data. A microprocessor object code optimization device comprising a simulator, wherein the simulator analyzes an instruction code of the primary object code generated by the compiling unit and executes an instruction code corresponding to execution of the instruction code corresponding process. The number of accesses of the data code by the execution of the instruction code is detected based on the data access information recorded for each address and the size of the data code to be accessed. A certain cap A second object code generated by rearranging the second object code, analyzing the instruction code of the second object code, and executing the instruction code, thereby enabling high-speed simulation execution. Object code optimization device for processors. 2. The method according to claim 1, wherein the simulator analyzes an instruction code of one of a primary target code as a target code generated by the compiling unit and a secondary target code as a target code generated by the simulator. An instruction code analysis unit that executes the analyzed instruction code; a profile data generation unit that generates the profile data based on a result of the execution of the instruction code; and data in the primary object code. A data access information generating unit that analyzes an access instruction and outputs the data access address (hereinafter referred to as an address) and a data access size (hereinafter referred to as a size) to data access information; and an access frequency for each address with reference to the data access information. Data codes in descending order of A data rearrangement unit that selects the data code having the maximum size as a selected data code as a selected data code, rearranges the selected data code in the cache area in descending order of the access frequency, and corrects an instruction code; and 2. The apparatus according to claim 1, further comprising a secondary purpose code generation unit configured to generate the data rearranged by the unit and the corrected instruction code as the secondary purpose code. 3. The data access information analysis section, wherein the data access information generation section analyzes the data access instruction in the primary object code, and detects the data access address and the size, and the data access instruction analysis section. 3. The apparatus according to claim 2, further comprising a data access information output unit that outputs the data address and the data access size detected in the step (c) to the data access information. 4. The data rearrangement section references the data access information, sorts data codes in descending order of access frequency for each address, selects a data code having a maximum size, and places the data code in the cache area in descending order of access frequency. A data relocation execution unit that adds the relocated address to the data access information and outputs the data as relocation information, wherein the read target code is a data code access instruction and the access address is 3. An instruction code correcting unit for correcting an instruction code by replacing an access address of the object code with an access address after the arrangement when the access address before the relocation of the relocation information matches the access address. Object code optimization device for microprocessors. 5. A microprocessor for compiling an input code as a compiling program recorded on a recording medium using profile data to generate a primary purpose code, simulating the primary purpose code, and generating the profile data. In the method of optimizing an object code, the simulation analyzes an instruction code of the primary object code generated by the compilation, executes an instruction code corresponding to execution of the instruction code corresponding process, and executes a data code by executing the instruction code. The number of times of access is detected based on data access information recorded for each address and the size of the data code to be accessed, and a frequently accessed data code is detected and relocated to a cache area which is a data code area accessible by one instruction. Secondary purpose It generates said by performing the instruction code executed by analyzing the instruction code of the secondary object code, a method of optimizing object code for a microprocessor, characterized in that to enable high-speed simulation runs. 6. A microprocessor for compiling an input code, which is a compilation program recorded on a recording medium, using profile data to generate a primary purpose code, simulating the primary purpose code, and generating the profile data. In the method for optimizing an object code, an instruction code analyzing step for analyzing an instruction code of the primary object code; an instruction simulation step for executing the analyzed primary instruction code; and, based on a result of the execution of the primary instruction code. A profile data generating step of generating the profile data, and analyzing a data access instruction in the instruction code,
Detects data access address and access size,
A data access information generating step of storing the access address and the access size of the detected data in data access information; and an access count of the data code generated in the data access information generating step for each of the access address and the access size. Based on the recorded data access information, the data code is detected in the descending order of the access frequency, and is relocated to the cache area, which is a data code area accessible by one instruction, in the descending order of the access frequency to correct the instruction code. A method of optimizing an object code for a microprocessor, comprising: an arranging step; and a secondary object code generating step of generating, as a secondary object code, the object code corrected in the data rearranging step. 7. The instruction code analyzing step, wherein the object code serving as an input of the simulation is the primary object code generated by the compilation or the secondary object code generated by the simulation. A primary / secondary target code determining step of determining whether the primary / secondary target code is the primary target code in the primary / secondary target code determining step; and a primary target code analyzing step of analyzing an instruction code of the primary target code. 7. The method according to claim 6, further comprising a secondary object code analyzing step of analyzing an instruction code of the secondary object code if the primary / secondary object code determining step is the secondary object code. To optimize object code for microprocessors. 8. The data access information generating step analyzes the data access instruction in the instruction code, and detects the data access address and the access size of the data access instruction. 7. The microprocessor according to claim 6, further comprising: outputting the detected data access address and the access size to the data access information, and incrementing a number of accesses in the data access information. How to optimize purpose code. 9. The data rearrangement step refers to the data access information, sorts data codes in descending order of access frequency for each address, and selects a data code having a maximum access size as a selected data code. A data rearrangement execution step of rearranging the selected data code in the cache area in descending order of access frequency, adding the rearranged address to the data access information and outputting the data access information as relocation information; When the target code is a data code access instruction and the access address matches the access address before the relocation of the relocation information, the access address of the matched data code access instruction is replaced with the access address after the read. To correct the instruction code Method of optimizing object code for the microprocessor according to claim 6, characterized in that it comprises a correction step. 10. The data access instruction analyzing step determines whether or not the data access instruction in the instruction code is a data access instruction. If the data access instruction is not the data access instruction, the data proceeds to an instruction code end determination step. An access instruction determination step; an address size extraction step for extracting the data access address and the access size in the data access instruction if the data access instruction is the data access instruction in the data access instruction determination step; A corresponding entry search step of searching for an entry in the data access information corresponding to the data access address and the access size, and, if the data access information has a corresponding entry, a corresponding entry access count A corresponding entry presence determination step for proceeding to an increment step; a corresponding entry access count increment step for incrementing the access count of the corresponding entry; and a new entry if the data access information does not have the corresponding entry in the corresponding entry presence determination step. A new entry adding step of adding the data access address and the access size entry fetched in the address size fetching step to the data access information; and determining whether or not the end of the instruction code has been reached. 9. The method for optimizing an object code for a microprocessor according to claim 8, further comprising: an instruction code end determination step of returning to a code analysis step and proceeding to a data rearrangement step when the instruction code end is completed. 11. The data rearrangement execution step includes the steps of: sorting the data codes in descending order of access frequency for each address based on the data access information to generate sort data; A data fetching step of fetching data codes in descending order; a maximum size entry search step of searching for a data code having a maximum access size among the data codes having the same address as the fetched access address and selecting the selected data code as a selected data code; A cache area moving step of moving a code to the cache area; a relocation information output step of adding a post-placement address to the data access information and outputting it as relocation information; and determining whether there is an empty area in the cache area. Before doing When the empty area of the cache area still remains, the process proceeds to a data end determination step described later. When the empty area of the cache area is exhausted, the empty cache area absence determination step proceeds to a non-cache area moving step described below. If all the addresses of the data are completed, the process proceeds to the instruction code correction step. If not all the addresses are completed, the process returns to the data fetching step, and the above process is repeated. Moving the data code of the access address to a non-cache area which is a data code area accessible at a low speed, outputting the relocation information to the relocation information, and proceeding to the instruction code correction step; 10. The microphone according to claim 9, comprising: Optimization method for object code for low-speed processors. 12. The instruction code correction step includes: extracting one instruction code from the primary object code; and determining whether the instruction code has been read to the end.
If the instruction code has been read to the end, the operation is terminated, and if there is still an instruction code to be read, an instruction code end determination step that proceeds to an access instruction determination step described below; If it is not a data code access instruction,
Returning to the one instruction code fetching step, if the instruction code is the data code access instruction, the access instruction determining step to proceed to the next matching search step; and searching the relocation information for the data code access instruction. The match search step for finding a match entry that is an entry where the access address of the relocation information matches the pre-placement address in the relocation information.If the match entry is found in the match search step, proceed to the next replacement step. Returning to the one instruction code fetching step and repeating the above processing; if the matching entry is not found in the matching search step, returning to the one instruction code fetching step and repeating the above processing; The address of the data code access instruction is assigned to the matching entry. Method of optimizing object code for the microprocessor of claim 9, characterized in that it comprises a said replacement step of replacing the rear address. 13. The data rearrangement execution step includes the steps of: sorting the data codes in descending order of access frequency for each address based on the data access information to generate sort data; A data retrieval step of retrieving data codes in descending order; a maximum size entry retrieval step of retrieving a data code having a maximum access size from the data codes at the same address as the retrieved access address and selecting the selected data code as a selected data code; It is determined whether or not there is an empty area. If the empty area of the cache area still remains, the process proceeds to a cache area moving step described below. If the empty area of the cache area is exhausted, the process proceeds to a non-cache area moving step to be described later. Advancing free cash Determining a non-cache area, a cache area moving step of moving the selected data code to the cache area, and a non-cache area which is a data code area that can access the data code of the remaining access address of the sort data at a low speed. Moving the non-cache area to the data access information; adding a post-placement address to the data access information; and outputting the rearrangement information as relocation information. 10. The microprocessor according to claim 9, further comprising: a code correction step; if not all addresses are completed, returning to the data fetching step and repeating the above processing. Method. 14. The instruction code correcting step includes: a relocation information extracting step of extracting one entry from the relocation information; and determining whether or not the search has been performed until the end of the relocation information. If it is the end, the process ends. If it is not the end of the relocation information, the process proceeds to the next first instruction code fetching step. One instruction code fetching step; and if the instruction code read in the one instruction code fetching step is not the data code access instruction,
Returning to the one instruction code fetching step, if the instruction code is the data code access instruction, an access instruction determining step to proceed to the next post-placement address replacement step; A post-placement address replacement step of searching for a matching entry in which the access address of the instruction matches the pre-placement address in the relocation information, and replacing the matched entry with a post-placement address; A second one-instruction-code fetching step for fetching an instruction code; and determining whether or not the instruction is completed. If not, return to the access-instruction determination step. Repeat the following processing. Return to the relocation information extracting step and repeat the following processing. 9. method of optimizing object code for a microprocessor as claimed, characterized in that the. 15. A program for optimizing a target code for a microprocessor which compiles an input code which is a compile program using profile data to generate a primary target code, simulates the primary target code, and generates the profile data. In the recording medium, the simulation analyzes the instruction code of the primary target code generated by the compilation, executes the instruction code corresponding to the execution of the instruction code corresponding process, and executes the instruction code execution. A data code having a high access frequency is detected based on the data access information recorded for each address and the size of the data code to be accessed, and relocated to a cache area which is a data code area accessible by one instruction. Next Generating a code, analyzing the instruction code of the secondary object code, and executing the instruction code, thereby enabling a high-speed simulation execution; and recording a program for optimizing an object code for a microprocessor. Recording medium. 16. A program for optimizing a target code for a microprocessor which compiles an input code which is a compile program using profile data to generate a primary target code, simulates the primary target code, and generates the profile data. An instruction code analyzing step of analyzing the instruction code of the primary object code, an instruction simulation step of executing the analyzed primary instruction code, and a step of executing the primary instruction code based on a result of the execution of the primary instruction code. Profile data generating step of generating profile data, and analyzing a data access instruction in the instruction code,
Detects data access address and access size,
A data access information generating step of storing the access address and the access size of the detected data in data access information; and an access count of the data code generated in the data access information generating step for each of the access address and the access size. Based on the recorded data access information, the data code is detected in the descending order of the access frequency, and is relocated to the cache area, which is a data code area accessible by one instruction, in the descending order of the access frequency to correct the instruction code. Recording a program for optimizing an object code for a microprocessor, comprising: an arrangement step; and a secondary object code generation step of generating the object code corrected in the data rearrangement step as a secondary object code. Medium.