JP2011081836A - Compiler device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a compiler for reducing the development man-hours for a program. <P>SOLUTION: A compiler 58 which translates a source program 72 described in a high level language into a machine language program is provided with an instruction acquiring part which acquires an instruction to optimize the generated machine language program, a parser part 76 which analyzes the source program 72, an intermediate code conversion part 78 which converts the source program 72 into an intermediate code based on the analysis result of the parser part 76, an optimizing part 68 which optimizes the intermediate code according to the instruction, and a code generation part 90 which converts the intermediate code into the machine language program. The instruction is the optimization instruction taking a processor using a cache memory, as a target processor. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a compiler apparatus that converts a source program written in a high-level language such as C language into a machine language program, and more particularly to an instruction for optimization by a compiler.

  Conventionally, various high-level language compilers that compile a source program written in a high-level language into a machine language instruction sequence have been proposed (for example, see Patent Document 1).

  In a high-level language compiler that compiles a source program written in such a high-level language into a machine language instruction sequence, a machine language instruction sequence for improving the execution speed in consideration of the hardware configuration such as a cache memory Could not be optimized.

  For this reason, to create a machine language instruction sequence that takes into account the hardware configuration, create a program in assembly language, create an algorithm that takes into account the hardware configuration, and create a source program based on that algorithm. It is.

JP 2003-99269 A

  However, there is a problem that it takes a lot of development man-hours to develop a program in assembly language.

  Another problem is that programs written in assembly language have poor portability because of their poor portability.

  Furthermore, in today's hardware becoming larger and more complex, there is a problem that it is very difficult to manually tune the performance by manually creating an algorithm that considers hardware.

  The present invention has been made to solve the above-described problems, and a first object of the present invention is to provide a compiler apparatus that does not require a program development man-hour.

  It is a second object of the present invention to provide a compiler apparatus having a high program asset.

  It is a third object of the present invention to provide a compiler device that does not require performance tuning manually.

  In order to achieve the above object, a compiler apparatus according to the present invention is a compiler apparatus that translates a source program written in a high-level language into a machine language program, and issues an instruction to optimize the machine language program to be generated. Instruction acquisition means for acquiring; parser means for analyzing the source program; intermediate code conversion means for converting the source program into intermediate code based on the analysis result in the parser means; and the intermediate code in accordance with the instructions. Optimizing means for optimizing and code generating means for converting the intermediate code into the machine language program, wherein the instruction is an optimization instruction for a processor that uses a cache memory as a target processor.

  According to this configuration, the intermediate code is optimized based on the optimization instruction. Therefore, it is possible to generate a machine language program that can efficiently use the cache memory only by giving an instruction without developing a program in assembly language. For this reason, development man-hours are not required as compared with the case of developing a program in assembly language. The source program is written in a high-level language, and a machine language program that can efficiently use the cache memory can be generated simply by giving an instruction as described above. For this reason, various optimizations are performed by changing the instructions in various ways. For this reason, the asset of the program is improved. Furthermore, there is no need to manually tune performance.

  Preferably, the instruction acquisition unit divides a specific loop process in the source program into a plurality of loop processes so that an object included in the loop process is arranged in the cache memory for each predetermined capacity. The optimization unit divides the loop processing that is the target of the instruction acquired by the instruction acquisition unit into a plurality of loop processes according to the instruction.

  The loop division is performed so that the objects included in the loop processing are arranged in the cache memory at a time. For this reason, since a large number of objects are to be processed at a time, it is possible to prevent hit mistakes that occur because these objects cannot be placed in the cache memory at a time.

  More preferably, the instruction acquisition unit acquires an instruction to store a specific object in the cache memory in advance in the source program before the object is referred to, and the optimization unit includes the object Are stored in advance in the cache memory before the object is referred to.

  By performing this instruction, it is possible to prevent a hit miss that occurs because an object to be used during program execution is not stored in the cache memory.

  More preferably, the instruction acquisition means groups specific objects in the source program according to the size of the line data of the cache memory, and objects included in different groups have different set numbers of the cache memory. An instruction to place in the cache entry and the name of the specific object are obtained, and the optimization unit groups the specific object according to the size of the line data of the cache memory, and belongs to different groups Objects are not arranged in cache entries having the same set number in the cache memory.

  It is possible to prevent hit misses caused by a race condition in which objects accessed at close timings scramble the blocks having the same set number in the cache memory and drive out the objects.

  More preferably, each of the plurality of cache entries included in the cache memory has a weak flag for storing a value indicating the easiness of eviction of an object stored in the cache entry, and the main memory used by the processor is The stored object is arranged in the cache memory, and a weak space in which a value that makes the object easy to kick out is set in the weak flag at the time of the arrangement, and the stored object is stored in the cache memory. And a cacheable space in which a value that facilitates expelling the object is not set in the weak flag at the time of the arrangement, and the instruction acquisition unit includes the specific object in the source program. We An instruction to place the specific object in the weak space or the cacheable space, a name of the specific object, and the placement information based on placement information indicating whether to place the space in the space or the cacheable space And the optimization means arranges a specific object in either the weak space or the cacheable space according to the arrangement information.

  By arranging the objects in an appropriate space, for example, by using a weak space, a weak bit can be set for an object that is not frequently used, and the object can be preferentially driven out. As a result, it is possible to prevent hit misses due to a race condition in which objects scramble blocks of the same set number in the cache memory and drive out objects from each other.

  More preferably, the instruction acquisition unit acquires an instruction to cause the cache memory control unit to execute a dedicated command of the cache memory control unit that controls the cache memory in the source program, and the optimization unit includes: Based on the instruction, the cache memory control unit executes the dedicated command.

  By making it possible to designate a dedicated command to be executed by the cache memory control means, the user can designate fine control of the cache memory, and hit misses in the cache memory can be prevented.

  The present invention can be realized not only as a compiler apparatus including such characteristic means, but also as a compile method using the characteristic means included in the compiler apparatus as a step, or provided in the compiler apparatus. It can also be realized as a program for causing a computer to function as each means. Needless to say, such a program can be distributed via a recording medium such as a CD-ROM or a transmission medium such as the Internet.

  Compared to developing a program in assembly language, development man-hours are not required.

  In addition, the asset of the program is improved.

  Furthermore, there is no need to manually tune performance.

  Furthermore, hit misses that occur because objects cannot be placed in the cache memory at once can be prevented.

  In addition, it is possible to prevent a hit miss that occurs because an object to be used during program execution is not stored in the cache memory.

  Further, it is possible to prevent hit misses caused by a race condition in which the objects scramble the blocks having the same set number in the cache memory and drive out the objects.

It is a block diagram which shows a part of hardware constitutions of the computer targeted by the compilation system which concerns on embodiment of this invention. It is a block diagram which shows the hardware constitutions of a cache memory. It is a figure which shows the detailed bit structure in a cache entry. It is a block diagram which shows the hardware constitutions of a subcache memory. It is a figure for demonstrating the kind of storage area contained in the main memory. It is a block diagram which shows the structure of the program development system which develops a machine language program. It is a functional block diagram which shows the structure of a compiler. It is a figure for demonstrating a tiling process. It is a figure for demonstrating the check process of capacitive miss generation. It is a figure for demonstrating the designation | designated method of prefetch instruction insertion processing. It is a figure for demonstrating the designation | designated method of prefetch instruction insertion processing. It is a figure for demonstrating the prefetch command insertion process by the pragma command with respect to the arrangement | sequence in a loop. It is a figure for demonstrating the designation | designated method of the prefetch instruction insertion process using profile information. It is a figure for demonstrating the outline of a data arrangement | positioning process. It is a figure for demonstrating the method regarding designation | designated of data arrangement | positioning. It is a figure which shows an example of the source program containing the pragma command which designates data arrangement | positioning. It is a figure of the object divided into groups. It is a figure which shows an example of the source program containing the pragma command which designates data arrangement | positioning. It is a figure which shows the designation | designated method for arrange | positioning an object in a specific space. It is a figure which shows the information stored in the exclusive register DPTEL. It is a figure which shows the list of built-in functions. It is a figure which shows an example of the intermediate code produced | generated by the cache command insertion part. It is a figure which shows the list of the built-in functions for investigating whether the built-in function shown in FIG. 21 is functioning effectively. It is a figure for demonstrating the designation | designated method for inputting / outputting various information with respect to a compiler.

  FIG. 1 is a block diagram showing a part of a hardware configuration of a computer targeted by a compile system according to an embodiment of the present invention. The computer 10 includes a processor 1, a main memory 2, a cache memory 3, a sub-cache memory 4, and a cache control unit 5. The processor 1 is a processing unit that executes a machine language program, and includes a dedicated register 6 (dedicated register DPTEL), which will be described later, in addition to the functions of a normal processor.

  The main memory 2 is a memory for storing machine language instructions executed by the processor 1 and various data.

  The cache memory 3 is a memory that operates according to the 4-way set associative method and can read and write data at a higher speed than the main memory 2. Note that the storage capacity of the cache memory 3 is smaller than that of the main memory 2.

  The sub-cache memory 4 is a memory that operates according to the direct mapping method and can read / write data at a higher speed than the main memory 2. Note that the storage capacity of the sub-cache memory 4 is smaller than that of the cache memory 3.

  The cache control unit 5 is a processing unit for controlling the cache memory 3 and the sub-cache memory 4, and has dedicated registers 7 to 9 (dedicated registers TACM, TACSZ and TACSTAD) which will be described later.

  FIG. 2 is a block diagram showing a hardware configuration of the cache memory 3. As shown in the figure, the cache memory 3 is a 4-way set associative cache memory, and includes an address register 20, a decoder 30, four ways 31a to 31d (hereinafter abbreviated as ways 0 to 3), and four Comparators 32a to 32d, four AND circuits 33a to 33d, an OR circuit 34, a selector 35, and a demultiplexer 37 are provided.

  The address register 20 is a register that holds an access address to the main memory 2. This access address is assumed to be 32 bits. As shown in the figure, the access address includes a 21-bit tag address and a 4-bit set index (SI in the figure) in order from the most significant bit. Here, the tag address indicates an area in the memory mapped to the way. The set index (SI) indicates one of a plurality of sets over the ways 0 to 3. This set number is 16 sets because the set index (SI) is 4 bits. The block specified by the tag address and the set index (SI) is a replacement unit, and is also called line data or a line when stored in the cache memory. The size of the line data is a size determined by address bits lower than the set index (SI), that is, 128 bytes. If one word is 4 bytes, one line data is 32 words. The least significant 7 bits in the address register 20 are ignored when accessing the way.

  The decoder 30 decodes 4 bits of the set index (SI), and selects one of 16 sets that straddle the four ways 0 to 3.

  The four ways 0 to 3 have the same configuration and have a total capacity of 4 × 2 kbytes. Way 0 has 16 cache entries.

  FIG. 3 shows a detailed bit configuration in one cache entry. As shown in the figure, one cache entry holds a valid flag V, a 21-bit tag, 128-byte line data, a weak flag W, and a dirty flag D. The valid flag V indicates whether or not the cache entry is valid. The tag is a copy of the 21-bit tag address. Line data is a copy of 128-byte data in a block specified by a tag address and a set index (SI). The dirty flag D indicates whether or not the cache entry has been written, that is, whether or not it is necessary to write back to the memory (write back) because the data cached during the cache entry differs from the data in the memory due to the write. Indicates. The weak flag W is a flag indicating an object to be evicted from the cache entry, and when a cache miss occurs, data is preferentially evicted from the cache entry having the weak flag W of 1.

  Ways 1 to 3 are the same as way 0. Four cache entries spanning four ways selected through the decoder 30 by the four bits of the set index (SI) are called “sets”.

  The comparator 32a compares whether or not the tag address in the address register 20 matches the tag of the way 0 among the four tags included in the set selected by the set index (SI). The comparators 32b to 32c are the same except that they correspond to the ways 31b to 31d.

  The AND circuit 33a compares whether or not the valid flag V matches the comparison result of the comparator 32a. The comparison result is h0. When the comparison result h0 is 1, it means that there is line data corresponding to the tag address and set index (SI) in the address register 20, that is, a hit in way 0. If the comparison result h0 is 0, it means that a miss-hit has occurred. The AND circuits 33b to 33d are the same except that they correspond to the ways 31b to 31d. The comparison results h1 to h3 mean whether the hits are made in ways 1 to 3 or missed.

  The OR circuit 34 calculates the logical sum of the comparison results h0 to h3. Let this logical sum be hit. hit indicates whether or not the cache memory 3 has been hit.

  The selector 35 selects the line data of the hit way among the line data of the ways 0 to 3 in the selected set.

  The demultiplexer 37 outputs write data to one of the ways 0 to 3 when writing data to the cache entry.

  FIG. 4 is a block diagram showing a hardware configuration of the sub-cache memory 4. As shown in the figure, the sub cache memory 4 is a direct mapping type (1-way set associative) cache memory, and includes an address register 44, a decoder 40, one way 41, a comparator 42, and an AND circuit. 43.

  The address register 44 is a register that holds an access address to the main memory 2. This access address is assumed to be 32 bits. As shown in the figure, the access address includes a 21-bit tag address and a 1-bit set index (SI in the figure) in order from the most significant bit. Here, the tag address indicates an area in the memory mapped to the way. The set number of ways 41 is two sets because the set index (SI) is 1 bit. The block specified by the tag address and the set index (SI) is a replacement unit, and is also called line data or a line when stored in the cache memory. The size of the line data is 128 bytes. If one word is 4 bytes, one line data is 32 words. The least significant 10 bits in the address register 20 are ignored when accessing the way.

  The decoder 40 decodes one bit of the set index (SI) and selects one of the two sets. One cache entry is the same as that shown in FIG.

  The comparator 42 compares whether or not the tag address in the address register 44 matches the tag included in the set selected by the set index (SI).

  The AND circuit 43 compares whether or not the valid flag V matches the comparison result of the comparator 42. Let this comparison result be hit. When the comparison result hit is 1, it means that line data corresponding to the tag address and set index (SI) in the address register 44 exists, that is, hit. If the comparison result hit is 0, it means that a miss-hit has occurred.

  FIG. 5 is a diagram for explaining the types of storage areas included in the main memory 2. The storage area has four types of storage areas: a cacheable space, a weak space, a sub-cache space, and an uncacheable space. Instructions or data arranged in the cacheable space and the weak space are read from and written to the cache memory 3. In particular, when the data arranged in the weak space is arranged in the cache memory 3, the weak bit W is set to 1. Instructions or data arranged in the sub-cache space are read from and written to the sub-cache memory 4. Instructions or data arranged in the uncacheable space are exchanged directly with the processor 1 without being arranged in the cache memory 3 and the sub-cache memory 4.

  FIG. 6 is a block diagram showing a configuration of a program development system 50 that develops a machine language program to be executed by the processor 1 of the computer 10. The program development system 50 includes a debugger 52, a simulator 54, a profiler 56, and a compiler 58.

  The compiler 58 is a program for reading the profile information 64 output from the source program and the profiler 56 and converting it into a machine language program, and has an optimization unit 68 for optimizing machine language instructions therein. Yes. Details of the compiler 58 will be described later.

  The debugger 52 is a program for specifying the position and cause of the bug found when compiling the source program in the compiler 58. The simulator 54 is a program that virtually executes the machine language program, and the execution result is output as execution log information 62. The simulator 54 internally includes a cache memory simulator 60 that outputs simulation results such as hits and miss hits of the cache memory 3 and the sub-cache memory 4 in the execution log information 62 and outputs them.

  The profiler 56 is a program that analyzes the execution log information 62 and outputs profile information 64 that serves as hint information such as optimization in the compiler 58.

  FIG. 7 is a functional block diagram showing the configuration of the compiler 58. This compiler is a cross compiler that converts a source program 72 described in a high-level language such as C language or C ++ language into a machine language program 92 using the processor 1 as a target processor, and is executed on a computer such as a personal computer. This is realized by a program to be executed and roughly divided into a parser unit 76, an intermediate code conversion unit 78, an optimization unit 68, and a code generation unit 90.

  The parser unit 76 is a preprocessing unit that extracts reserved words (keywords) and the like from the source program 72 to be compiled and performs lexical analysis.

The intermediate code conversion unit 78 is a processing unit that converts each statement of the source program 72 passed from the parser unit 76 into an intermediate code based on a certain rule. Here, the intermediate code is typically a code expressed in the form of a function call (for example, a code indicating “+ (int a, int b)”; “adding an integer b to an integer a” It is shown.) However, the intermediate code includes not only such a function call type code but also a machine language instruction of the processor 1. The intermediate code conversion unit 78 refers to the profile information 64 when generating the intermediate code, and generates an optimal intermediate code.

  The optimization unit 68 performs processing such as instruction combination, redundancy removal, instruction rearrangement, and register allocation on the intermediate code output from the intermediate code conversion unit 78, thereby improving the execution speed and reducing the code size. This is a processing unit that performs optimization processing peculiar to the compiler 58 in addition to normal optimization processing (tiling unit 84, prefetch instruction insertion unit 86, arrangement set information setting unit 87, cache command insertion unit 88). Have Processing executed by the tiling unit 84, the prefetch instruction insertion unit 86, the arrangement set information setting unit 87, and the cache command insertion unit 88 will be described in detail later. The optimization unit 68 also outputs tuning hint information 94 that serves as a hint when the user re-creates the source program 72, such as information on a cache miss in the cache memory 3.

  The code generator 90 refers to the intermediate code output from the optimizing unit 68 and refers to a conversion table or the like held therein, thereby replacing all the codes with machine language instructions, thereby Generate.

  The compiler 58 specifically aims to reduce cache misses in the cache memory 3. Cache misses can be broadly divided into three categories: (1) initial miss, (2) capacitive miss, and (3) competitive miss. “Initial miss” refers to a hit miss that occurs because an object to be used during program execution is not stored in the cache memory 3. A “capacity miss” refers to a hit miss that occurs because a large number of objects are to be processed at one time and cannot be placed in the cache memory 3 at a time. The “competitiveness miss” refers to a hit miss that occurs when different objects try to use cache entries in the cache memory 3 at the same time, and perform mutual pursuit from the cache entries.

  Next, a characteristic operation of the compiler 58 configured as described above will be described with a specific example.

(1) Tiling processing Tiling processing means that when a capacity error occurs in loop processing, one loop is divided into a plurality of loops, so that the capacity of objects processed at one time is cache memory. This is a technique for suppressing the capacity to 3 or less. This tiling process is executed in the tiling unit 84.

  FIG. 8 is a diagram for explaining the tiling process.

  FIGS. 8A and 8B are diagrams illustrating an example of a pragma for designating execution of the tiling process. The “pragma (or pragma command)” is an instruction to the compiler 58 that can be arbitrarily designated (placed) by the user in the source program 72, and is a character string starting with “#pragma”.

  The pragma command shown in FIG. 8A designates execution of tiling processing in which the capacity of an object used in loop processing is constant (byte capacity designated by NUM). If the capacity NUM is not designated, execution of the tiling process is designated so as to have a predetermined (default) capacity.

  The pragma command shown in FIG. 8B designates execution of tiling processing so that the number of loop processing loops is constant (number of times specified by NUM). If the number of times NUM is not specified, the execution of the tiling process is specified to be the default number of times.

  Note that in the above-described pragma command, the loop process described immediately after the pragma command is a processing target.

  FIG. 8C is a diagram illustrating an example of a loop process that does not include a pragma command. FIG. 8D is a diagram schematically showing changes in the value of the loop counter in this loop processing. As shown in FIG. 8D, in this loop process, every time the loop counter i increases by 1, the loop counter j increases by 1 from 0 to 999. Therefore, when the object c is arranged in the cacheable space or the weak space of the main memory 2, the object c (1000 array elements) is tried to be arranged in the cache memory 3 at a time, causing a capacity error. End up.

Therefore, as shown in FIG. 8E, by inserting a pragma command “# pragma_loop_tiling_times = 100” immediately before the second loop processing of the source program 72,
The source program 72 shown in FIG. 8C is converted into the source program 72 as shown in FIG. That is, instead of incrementing the loop counter j from 0 to 999 by 1000 times, the process of incrementing the loop counter k by 100 times is converted into a process of looping 10 times. FIG. 8G is a diagram schematically showing changes in the value of the loop counter after conversion. As shown in FIG. 8G, the process of incrementing the loop counter k by 100 times is repeated 10 times. As a result, the objects placed in the cache memory 3 at a time can be reduced to 100 elements of the array c, and the occurrence of a capacitive miss can be prevented. Note that the tiling process is performed by the tiling unit 84 as described above. Therefore, the conversion from the source program 72 shown in FIG. 8 (e) to the source program 72 shown in FIG. 8 (f) is actually executed in the intermediate code format.

  According to the pragma command, even if the hardware configuration such as the capacity of the cache memory 3 is changed, it is only necessary to change the value of the capacity NUM or the number of times NUM and recompile. For this reason, it is possible to improve the asset property of the source program.

  Note that the tiling unit 84 may check whether a capacitive error has occurred. FIG. 9 is a diagram for explaining a check process for occurrence of a capacitive miss. For example, a pragma for outputting information as to whether or not a capacitive error has occurred as tuning hint information 94 is defined as shown in FIG. 9A, and this pragma is immediately before the loop of the source program 72 to be checked. By describing, information indicating whether or not a capacitive error has occurred in the designated loop is output as tuning hint information 94.

  FIG. 9B is a diagram showing an example of the source program 72 including loop processing, and FIG. 9C is a diagram immediately before two loops included in the source program 72 shown in FIG. 9B. This is an example of the source program 72 in which the pragma command shown in FIG. As shown in FIG. 9 (d), by compiling the source program shown in FIG. 9 (c), information on whether or not a capacitive error has occurred in the two loop processes is displayed in the tuning hint information 94. Is output. The user can know whether or not a capacitive error has occurred by referring to the output tuning hint information 94. The pragma command shown in FIG. 8A or FIG. By inserting it into the program 72, it is possible to execute a tiling process and prevent a capacitive error.

  Note that the pragma command shown in FIG. 8 (a) or FIG. 8 (b) and the pragma command shown in FIG. 9 (a) can be simultaneously specified for the same loop.

  In addition, by inserting the pragma command shown in FIG. 9A immediately before the loop, the tiling unit 84 checks whether or not a capacitive error has occurred, and prevents a capacitive error from occurring. The tiling process may be automatically executed.

(2) Prefetch instruction insertion process The prefetch instruction insertion process is a process for inserting an instruction for prefetching an object in a specified area stored in the main memory 2 into the cache memory 3 in the intermediate code in advance. . This prefetch layer instruction insertion processing is executed in the prefetch instruction insertion unit 86.

  10 and 11 are diagrams for explaining a designation method of the prefetch instruction insertion processing. FIG. 10A to FIG. 10D show how to specify prefetch instruction insertion processing for a specific variable.

  FIGS. 10A and 10B show designation of prefetch instruction insertion processing by a pragma instruction, and is an instruction insertion instruction for prefetching the value of the designated variable name in the cache memory 3 in advance. When the number of cycles is designated as shown in FIG. 10B, the prefetch instruction is inserted by the number of cycles before the designated variable is referred to. As shown in FIG. 10A, when the number of cycles is not specified, the prefetch instruction is inserted before the specified variable is referred to by a predetermined number of cycles (default number of cycles). . That is, as shown in FIG. 10E, for example, a prefetch instruction for prefetching the variable a is inserted before the actual access of the variable a by the designated cycle number or the default cycle number.

  FIG. 10C and FIG. 10D show the specification of the prefetch instruction insertion processing by the built-in function, and the size in the main memory 2 having the address as the start address by specifying the address and the size as arguments. Is an instruction to insert an instruction for prefetching the value of the area specified in (1) into the cache memory 3 in advance. When the number of cycles is designated as shown in FIG. 10 (d), the same processing as the pragma command in FIG. 10 (b) is performed, and the number of cycles is designated as shown in FIG. 10 (c). If not, the same process as the pragma command in FIG. 10A is performed.

  FIG. 11A and FIG. 11B show how to specify prefetch instruction insertion processing for an array in a loop by a pragma instruction. The loop processing described immediately after the pragma command is the target of processing. As shown in FIG. 11B, when the number of cycles is specified, the latency of the cache memory 3 is taken into consideration, and the corresponding number of cycles before the element of the array is actually referred to before Instructions that prefetch elements are inserted. As shown in FIG. 11A, when the number of cycles is not specified, an instruction for prefetching the element is inserted by the number of default cycles.

  FIG. 12 is a diagram for explaining prefetch instruction insertion processing by a pragma instruction for an array in a loop. In the loop processing of the source program 72 as shown in FIG. 12A, when a pragma for prefetching the array a as shown in FIG. 12B is described, a prefetch instruction as shown in FIG. The insert command dpref () is inserted. By executing “dref (& a [0])” and “dpref (& a [4])”, the array value a [0] referred to when the loop counter i is i = 0 and i = 1. ˜a [7] is prefetched into the cache memory 3. Thereafter, loop processing is started, and by executing “dpref (& a [i + 1])”, the elements of the array used in the loop processing two times later are prefetched into the cache memory 3. In this way, elements are prefetched across loop processing iterations (iterations). That is, the element is prefetched in an iteration before the iteration in which the element of the array is referenced. Actually, the prefetch instruction insertion unit 86 inserts a prefetch instruction into the intermediate code.

  By executing the prefetch instruction insertion process as described above, an initial miss can be prevented.

  Note that a prefetch instruction may be automatically inserted using the profile information 64. FIG. 13 is a diagram for explaining a designation method for prefetch instruction insertion processing using profile information 64.

  FIG. 13A shows a designation method using compile options. When this option is attached at the time of compiling, an object causing an initial error is checked from the profile information 64, and an instruction for prefetching the object is inserted. With this compile option, it is also possible to specify the number of cycles at the position where the prefetch instruction is inserted, as in the above-described specification method.

FIG. 13B to FIG. 13D are designation methods using pragmas. As shown in FIG. 13 (e), the pragma shown in FIG. 13 (b) and the pragma shown in FIG. A prefetch instruction is inserted based on the profile information 64 for the range delimited by.

  When the pragma shown in FIG. 13D is specified in the source program 72, it indicates that the subsequent instructions follow the compile option. That is, when the compile option shown in FIG. 13A is set, a prefetch instruction is inserted based on the profile information 64 according to the option, but when the compile option is not set, No prefetch instruction is inserted. Note that the pragmas shown in FIGS. 13B to 13D may be written as built-in functions.

  FIG. 13 (f) and FIG. 13 (g) are designation methods using built-in functions. If an area specified by the size in the main memory 2 having the address as the start address by causing the address and size to be an argument, an initial miss has occurred, and the value of the area is stored in the cache memory 3 in advance. This is an instruction to insert a prefetch instruction. As shown in FIG. 13G, it is also possible to specify the number of cycles at the position where the prefetch instruction is inserted, as in the above-described specification method. These designations may be pragma commands.

  As described above, by inserting a prefetch instruction, it is possible to prevent an initial miss for a specific object in consideration of the latency of the cache memory 3. In particular, in the prefetch instruction insertion process considering the profile information 64, for example, when there is no other instruction before the prefetched variable is accessed, the designated cycle number or default cycle number is set. It is not possible to insert a prefetch instruction because it is empty. Therefore, in such a case, since it is useless to insert a prefetch instruction, the instruction is not inserted. Further, since there is no need to prefetch an object already stored in the cache memory 3, no prefetch instruction is inserted in this case. Such information can be understood by looking at the profile information 64.

(3) Data Placement Specifying Process FIG. 14 is a diagram for explaining the outline of the data placement process. As shown in FIG. 14A, it is assumed that there are three groups of variables (for example, variables with overlapping life spans) that are accessed at close timings among variables included in the source program (variable groups A to A). C). Here, it is assumed that the data size included in one variable group is the size of the line data in the cache memory 3, that is, 128 bytes. In the compiling system, when these three variable groups are written into the cache memory 3, machine language instructions are generated so as to be written into blocks having different set numbers. For example, if variable groups A, B, and C are arranged in blocks 0, 1, and 15 of cache memory 3, respectively, as shown in FIG. When written in the cache memory 3, it is stored in the storage area of the main memory 2 which is written in the blocks of the sets 0, 1, and 15. Therefore, as shown in FIG. 14C, when the variable groups A, B, and C are written from the main memory 2 to the cache memory 3, they are written to the blocks of the sets 0, 1, and 15, respectively. It becomes. By doing so, objects that are accessed at timings close to each other compete for a block having the same set number in the cache memory, and a conflicting state in which the objects are driven out from each other does not occur. Therefore, competitive mistakes can be reduced.

  FIG. 15 is a diagram for explaining a method related to designation of data arrangement. When the object names are specified side by side by the pragma shown in FIG. 15A, if the sum of these object sizes is equal to or smaller than the size of the line data (128 bytes), the same set of the cache memory 3 Optimization is performed such as placing objects. In the case of 128 or more, the objects are grouped every 128 bytes, and optimization is performed such that objects of different groups are arranged in different sets of the cache memory 3.

  For example, as shown in FIG. 16, the integer type arrays a [32], b [32], and c [32] are accessed at close timings by specifying the pragma “#pragma_overlap_access_object a, b, c”. Is explicitly indicated by the user. When the array a [32], b [32], and c [32] are set as one object group according to the instruction of the pragma, the arrangement set information setting unit 87 groups them every 128 bytes. Assuming that the integer type variable is 4 bytes, the arrays a [32], b [32], and c [32] are each 128 bytes. For this reason, this object group is divided into three groups (group data_a, data_b, and data_c) as shown in FIG. 17, the group data_a includes the array a [32], and the group data_b includes the array b [ 32] is included, and the array data [c] is included in the group data_c.

  After the grouping process, the arrangement set information setting unit 87 assigns a different set number to each group. For example, it is assumed that set numbers 0, 1, and 2 are assigned to the groups data_a, data_b, and data_c, respectively.

  Thereafter, the arrangement set information setting unit 87 generates an intermediate code so that the object of the group is arranged in the block of the cache memory 3 having the set number.

  It is also possible to specify the set number of the cache memory 3 in which the object is arranged by the pragma shown in FIG. For example, as shown in FIG. 18, when pragmas “#pragma _cache_set_number = 0 i”, “#pragma _cache_set_number = 1 j” and “#pragma _cache_set_number = 2 k” are specified in the source program 72, Intermediate codes are generated so that the arrays i, j, and k are arranged in the sets of the set numbers 0, 1, and 2 of the cache memory 3, respectively.

  According to the pragma shown in FIG. 15C, by specifying the object name and address, the arrangement set information setting unit 87 generates intermediate code for storing the object at the specified address in the main memory 2. For example, this addressing method is used when the address where the object should be stored is known in advance from the profile information 64 and the tuning hint information 94.

  When designation is performed using the compile option shown in FIG. 15D, the arrangement set information setting unit 87 arranges the objects with overlapping life intervals in different sets of the cache memory 3 based on the profile information 64. Then, an address of the object on the cache memory 3 is determined, and intermediate code is generated so as to place the object at the address.

  By the data arrangement designation process as described above, it is possible to prevent a conflicting state in which blocks with the same set number in the cache memory are competing with each other and the objects are expelled from each other. Therefore, competitive mistakes can be reduced.

(4) Memory Space Designation Processing As described above, the main memory 2 has four types of memory spaces (cashable space, weak space, sub-cache space, and uncacheable space). FIG. 19 is a diagram illustrating a designation method for arranging an object in a specific space. As described above, the processor 1 has the dedicated register 6 (dedicated register DPTEL). FIG. 20 is a diagram illustrating information stored in the dedicated register DPTEL. The dedicated register DPTEL stores a page address of the main memory 2 and an S / W flag indicating whether it is a sub-cache space or a weak space. Note that there are four dedicated registers DPTEL, numbered from 0 to 3.

  When the pragma shown in FIG. 19A is specified in the source program 72, the arrangement set information setting unit 87 sets the specified variable to the page address included in the dedicated register DPTEL with the specified number. Generate intermediate code to be deployed. Note that the type of the page address is designated by the S / W flag included in the dedicated register DPTEL as the sub-cache space or the weak space. For example, if the value of the S / W flag is 1, the sub cache space may be specified, and if it is 0, the weak space may be specified.

  When the compile option shown in FIG. 19B is specified at the time of compilation, the arrangement set information setting unit 87 determines the sub-cache space, weak space, or uncacheable space of the main memory 2 based on the profile information 64. If it is placed in, intermediate code that places valid variables in the space is generated. For example, when referring to a large array only once, the array is less frequently accessed, so an intermediate code to be placed in the sub-cache space is generated.

  When the pragma shown in FIG. 19C is designated in the source program 72, the arrangement set information setting unit 87 arranges the variable designated by the pragma in a specific space based on the profile information 64. Whether it is valid or not is checked, and if it is valid, an intermediate code for arranging the designated variable in the space is generated.

  As described above, by arranging the objects in an appropriate space, it is possible to prevent a competitive error. For example, by using the sub-cache space, objects frequently used in the cache memory 3 are not expelled. In addition, by using the weak space, it is possible to set a weak bit W on an object that is not used so much that it is expelled preferentially.

(5) Cache Command Insertion Processing In the following, a built-in function for specifying a dedicated command to be executed by the cache control unit 5 in the source program 72 is described.

  FIG. 21 is a diagram showing a list of built-in functions.

  The function shown in FIG. 21A is a process that pre-reads the area of the main memory 2 specified by the argument into the cache memory 3 (hereinafter also referred to as “fill process”) and a line that requires write back. This is a function that causes the cache control unit 5 to execute a process of writing back data (hereinafter also referred to as “writeback process”). In the argument, the area of the main memory 2 is specified by the variable name (start address of the variable) or address and the size from the address.

  The function shown in FIG. 21B is a function that causes the cache control unit 5 to execute a fill process and a process of setting 1 to the weak flag W (hereinafter also referred to as “weaken process”).

  The function shown in FIG. 21C caches a process only for securing a cache entry corresponding to the main memory 2 specified by an argument in advance (hereinafter also referred to as “touch process”) and a writeback process. This is a function to be executed by the control unit 5.

  The function shown in FIG. 21D is a function that causes the cache control unit 5 to execute a touch process and a weaken process.

  The function shown in FIG. 21E is a writeback process and a process for invalidating the cache entry in the cache memory 3 corresponding to the area of the main memory 2 specified by the argument (hereinafter also referred to as “invalidate process”). Is a function that causes the cache control unit 5 to execute.

  The function illustrated in FIG. 21F is a function that causes the cache control unit 5 to execute invalidate processing.

  The function illustrated in FIG. 21G is a function that causes the cache control unit 5 to execute the touch process.

  The function shown in FIG. 21H is a function that causes the cache control unit 5 to execute the fill process.

  When the functions shown in FIGS. 21A to 21H are included in the source program 72, the cache command insertion unit 88 generates intermediate code for causing the cache control unit 5 to execute the above-described processing. Generate.

  In order to cause the cache control unit 5 to execute a dedicated command, the start address of the target main memory 2 area is registered in the dedicated register TACSTAD of the cache control unit 5, and the size from the start address is registered in the dedicated register TACTSZ. The command may be registered in the dedicated register TACM.

  Therefore, the cache command insertion unit 88 generates an intermediate code as shown in FIG. 22, for example. This intermediate code is described assuming a processor 1 having a VLIW (Very Long Instruction Word) architecture. First, the command is once written in the general-purpose register r0 and then written in the dedicated register TACM. At the same time, the size is written to the general-purpose register r1. When the writing to the dedicated register TACM is successful, 1 is set in the flag C0 and 0 is set in the flag C1. If the writing has failed, 0 is set in the flag C0 and 1 is set in the flag C1. Therefore, when writing to the dedicated register TACM is successful, the commands on the third and fourth lines are executed, and the size and start address are set in the dedicated register TACZ and the dedicated register TACSTAD, respectively. If writing to the dedicated register TACM fails, the process on the fifth line is executed, and the process is executed again from the first line.

  As described above, by enabling the user to specify the command to be executed by the cache control unit 5, the user can specify fine control of the cache memory 3, and the initial miss, the capacity miss and the conflict. Sexual errors can be prevented.

  In the case of a built-in function that executes a fill process, a framework may be provided in which the fill process is executed before the designated cycle number or the default cycle number, as in the case of the prefetch instruction insertion process.

  Also, a built-in function may be provided to check whether the command executed by the cache control unit 5 is functioning effectively by checking the profile information 64. FIG. 23 is a diagram showing a list of built-in functions for examining whether or not the built-in functions shown in FIG. 21 are functioning effectively. That is, the built-in functions shown in FIGS. 23A to 23H execute the same processing as the built-in functions shown in FIGS. 21A to 21H, and each built-in function is effective. Is output as tuning hint information 94. In addition, the built-in functions shown in FIGS. 23A to 23H automatically delete invalid cache commands (intermediate codes to be executed by the cache control unit 5), and the intermediate code placement positions. Or may be adjusted. By referring to the output tuning hint information 94, the user can insert an optimal built-in function into the source program, and can efficiently use the cache memory 3.

  FIG. 24 is a diagram for explaining a designation method for inputting / outputting various information to / from the compiler 58 when executing the processes (1) to (5) described above. FIG. 24A shows a compile option for causing the compiler 58 to input information related to the cache memory 3, and is used by describing as shown in FIG. FIG. 24C shows an example of information related to the cache memory 3, which shows the size of the cache memory 3, the size of the line data, the number of latency cycles of the cache memory 3, and the like.

  FIG. 24D shows a compile option for specifying the file name of the profile information 64 input to the compiler 58. FIG. 24E shows compile options for designating the output file name of the tuning hint information 94 output from the compiler 58.

  As described above, according to the compiling system according to the present embodiment, it is possible to prevent the initial miss, the capacity miss, and the competitive miss in the cache memory 3 by various designation methods.

  The present invention is not limited to the embodiment described above. For example, when an instruction to the compiler by the pragma instruction described above can be made using an embedded function or a compile option, such an instruction may be given. The same applies to an instruction to the compiler by an intrinsic function or a compile option.

  The present invention can be applied to a compiler, and in particular, can be applied to a compiler that targets a processor that uses a cache memory.

DESCRIPTION OF SYMBOLS 1 Processor 2 Main memory 3 Cache memory 4 Sub cache memory 5 Cache control part 10 Computer 50 Program development system 52 Debugger 54 Simulator 56 Profiler 58 Compiler 60 Cache memory simulator 62 Execution log information 64 Profile information 68 Optimization part 72 Source program 76 Parser section 78 Intermediate code conversion section 84 Tiling section 86 Prefetch instruction insertion section 87 Placement set information setting section 88 Cache command insertion section 90 Code generation section 92 Machine language program 94 Tuning hint information

Claims (10)

A compiler device that translates a source program written in a high-level language into a machine language program,
An instruction acquisition means for acquiring an instruction to optimize the machine language program to be generated;
Parser means for analyzing the source program;
Intermediate code conversion means for converting the source program into intermediate code based on the analysis result in the parser means;
Optimization means for optimizing the intermediate code according to the instructions;
Code generation means for converting the intermediate code into the machine language program,
The processor that executes the machine language program is a processor that uses a cache memory;
Each of the plurality of cache entries included in the cache memory has a weak flag for storing a value indicating the easiness of eviction of the object stored in the cache entry,
The main memory used by the processor is stored in a weak space in which a stored object is placed in the cache memory and a value that makes it easy to drive the object out in the weak flag at the time of the placement. And a cacheable space in which a value that makes it easy to kick out the object is not set in the weak flag at the time of the placement.
The instruction acquisition unit is configured to place the specific object in the weak space or the cashier based on arrangement information indicating whether the specific object is arranged in the weak space or the cacheable space in the source program. An instruction to place in the space, the name of the specific object, and the placement information,
The optimizing unit generates an instruction for arranging a specific object in either the weak space or the cacheable space according to the arrangement information. A compiler device that translates a source program written in a high-level language into a machine language program,
An instruction acquisition means for acquiring an instruction to optimize the machine language program to be generated;
Parser means for analyzing the source program;
Intermediate code conversion means for converting the source program into intermediate code based on the analysis result in the parser means;
Optimization means for optimizing the intermediate code according to the instructions;
Code generation means for converting the intermediate code into the machine language program,
The processor that executes the machine language program is a processor that uses a cache memory;
The processor further uses a sub-cache memory having a smaller capacity than the cache memory;
Each of the plurality of cache entries included in the cache memory has a weak flag for storing a value indicating the easiness of eviction of the object stored in the cache entry,
The main memory used by the processor is stored in a weak space in which a stored object is placed in the cache memory and a value that makes it easy to drive the object out in the weak flag at the time of the placement. A cacheable space in which a value that makes it easy to drive out the object is not set in the weak flag and a stored object is placed in the sub-cache memory. Sub-cache space
The instruction acquisition unit determines a space of the main memory in which an object included in the source program is arranged based on an execution analysis result of the machine language program together with an instruction to translate the source program, Get an instruction to place the object,
The optimizing unit determines a space of the main memory in which an object included in the source program is arranged based on an execution analysis result of the machine language program, and generates an instruction for arranging the object in the space. A compiler apparatus characterized by that. A compiler device that translates a source program written in a high-level language into a machine language program,
An instruction acquisition means for acquiring an instruction to optimize the machine language program to be generated;
Parser means for analyzing the source program;
Intermediate code conversion means for converting the source program into intermediate code based on the analysis result in the parser means;
Optimization means for optimizing the intermediate code according to the instructions;
Code generation means for converting the intermediate code into the machine language program,
The processor that executes the machine language program is a processor that uses a cache memory;
The processor further uses a sub-cache memory having a smaller capacity than the cache memory;
Each of the plurality of cache entries included in the cache memory has a weak flag for storing a value indicating the easiness of eviction of the object stored in the cache entry,
The main memory used by the processor is stored in a weak space in which a stored object is placed in the cache memory and a value that makes it easy to drive the object out in the weak flag at the time of the placement. A cacheable space in which a value that makes it easy to drive out the object is not set in the weak flag and a stored object is placed in the sub-cache memory. Sub-cache space
The instruction acquisition unit determines a space of the main memory in which an object included in the source program is arranged based on an execution analysis result of the machine language program in the source program, and arranges the object in the space Get instructions to do so,
The optimizing unit determines a space of the main memory in which an object included in the source program is arranged based on an execution analysis result of the machine language program, and generates an instruction for arranging the object in the space. A compiler apparatus characterized by that. A compiler device that translates a source program written in a high-level language into a machine language program,
An instruction acquisition means for acquiring an instruction to optimize the machine language program to be generated;
Parser means for analyzing the source program;
Intermediate code conversion means for converting the source program into intermediate code based on the analysis result in the parser means;
Optimization means for optimizing the intermediate code according to the instructions;
Code generation means for converting the intermediate code into the machine language program,
The processor that executes the machine language program is a processor that uses a cache memory;
The instruction acquisition means acquires an instruction for causing the cache memory control means to execute a dedicated command of the cache memory control means for controlling the cache memory in the source program,
The optimization unit generates an instruction for causing the cache memory control unit to execute the dedicated command based on the instruction,
The dedicated command needs to pre-read a specified object from a main memory used by the processor into a predetermined cache entry of the cache memory, and write back an object stored in the cache entry to the cache memory. In some cases, the compiler apparatus is a command for writing back the object to the main memory. A compiler device that translates a source program written in a high-level language into a machine language program,
An instruction acquisition means for acquiring an instruction to optimize the machine language program to be generated;
Parser means for analyzing the source program;
Intermediate code conversion means for converting the source program into intermediate code based on the analysis result in the parser means;
Optimization means for optimizing the intermediate code according to the instructions;
Code generation means for converting the intermediate code into the machine language program,
The processor that executes the machine language program is a processor that uses a cache memory;
The instruction acquisition means acquires an instruction for causing the cache memory control means to execute a dedicated command of the cache memory control means for controlling the cache memory in the source program,
The optimization unit generates an instruction for causing the cache memory control unit to execute the dedicated command based on the instruction,
Each of the plurality of cache entries included in the cache memory has a weak flag for storing a value indicating the easiness of eviction of the object stored in the cache entry,
The dedicated command pre-reads the designated object from the main memory used by the processor to a predetermined cache entry in the cache memory, and sets a value that facilitates eviction of the object stored in the weak flag of the cache entry. A compiler device characterized by being a command. A compiler device that translates a source program written in a high-level language into a machine language program,
An instruction acquisition means for acquiring an instruction to optimize the machine language program to be generated;
Parser means for analyzing the source program;
Intermediate code conversion means for converting the source program into intermediate code based on the analysis result in the parser means;
Optimization means for optimizing the intermediate code according to the instructions;
Code generation means for converting the intermediate code into the machine language program,
The processor that executes the machine language program is a processor that uses a cache memory;
The instruction acquisition means acquires an instruction for causing the cache memory control means to execute a dedicated command of the cache memory control means for controlling the cache memory in the source program,
The optimization unit generates an instruction for causing the cache memory control unit to execute the dedicated command based on the instruction,
The dedicated command reserves a cache entry for storing a specified object in the cache memory in advance, and when the object stored in the cache entry needs to be written back to the cache memory. And a command for writing back the object to the main memory. A compiler device that translates a source program written in a high-level language into a machine language program,
An instruction acquisition means for acquiring an instruction to optimize the machine language program to be generated;
Parser means for analyzing the source program;
Intermediate code conversion means for converting the source program into intermediate code based on the analysis result in the parser means;
Optimization means for optimizing the intermediate code according to the instructions;
Code generation means for converting the intermediate code into the machine language program,
The processor that executes the machine language program is a processor that uses a cache memory;
The instruction acquisition means acquires an instruction for causing the cache memory control means to execute a dedicated command of the cache memory control means for controlling the cache memory in the source program,
The optimization unit generates an instruction for causing the cache memory control unit to execute the dedicated command based on the instruction,
Each of the plurality of cache entries included in the cache memory has a weak flag for storing a value indicating the easiness of eviction of the object stored in the cache entry,
The dedicated command is a command that secures a cache entry for storing a specified object in the cache memory in advance and sets a value that makes it easy to eject an object stored in the weak flag of the cache entry. The compiler apparatus characterized by this. A compiler device that translates a source program written in a high-level language into a machine language program,
An instruction acquisition means for acquiring an instruction to optimize the machine language program to be generated;
Parser means for analyzing the source program;
Intermediate code conversion means for converting the source program into intermediate code based on the analysis result in the parser means;
Optimization means for optimizing the intermediate code according to the instructions;
Code generation means for converting the intermediate code into the machine language program,
The processor that executes the machine language program is a processor that uses a cache memory;
The instruction acquisition means acquires an instruction for causing the cache memory control means to execute a dedicated command of the cache memory control means for controlling the cache memory in the source program,
The optimization unit generates an instruction for causing the cache memory control unit to execute the dedicated command based on the instruction,
When it is necessary to write back the object stored in the cache entry for storing the designated object to the cache memory, the dedicated command writes the object back to the main memory and A compiler device characterized by being a command for invalidating a cache entry. A compiler device that translates a source program written in a high-level language into a machine language program,
An instruction acquisition means for acquiring an instruction to optimize the machine language program to be generated;
Parser means for analyzing the source program;
Intermediate code conversion means for converting the source program into intermediate code based on the analysis result in the parser means;
Optimization means for optimizing the intermediate code according to the instructions;
Code generation means for converting the intermediate code into the machine language program,
The processor that executes the machine language program is a processor that uses a cache memory;
The instruction acquisition means acquires an instruction for causing the cache memory control means to execute a dedicated command of the cache memory control means for controlling the cache memory in the source program,
The optimization unit generates an instruction for causing the cache memory control unit to execute the dedicated command based on the instruction,
The dedicated device is a command for invalidating a cache entry for storing a specified object. A compiler device that translates a source program written in a high-level language into a machine language program,
An instruction acquisition means for acquiring an instruction to optimize the machine language program to be generated;
Parser means for analyzing the source program;
Intermediate code conversion means for converting the source program into intermediate code based on the analysis result in the parser means;
Optimization means for optimizing the intermediate code according to the instructions;
Code generation means for converting the intermediate code into the machine language program,
The processor that executes the machine language program is a processor that uses a cache memory;
The instruction acquisition means acquires an instruction for causing the cache memory control means to execute a dedicated command of the cache memory control means for controlling the cache memory in the source program,
The optimization unit generates an instruction for causing the cache memory control unit to execute the dedicated command based on the instruction,
The compiler apparatus according to claim 1, wherein the dedicated command is a command for preallocating a cache entry for storing a specified object in the cache memory.

Images