JP2002300131A - Device having circuit for analyzing delay profile of received signal of orthogonal frequency division multiplex modulation system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a device having a circuit analyzing a delay profile for a received signal of an orthogonal frequency division multiplex modulation system, that configures an arithmetic operation of the delay profile by using a small-sized inexpensive FFT. SOLUTION: The delay profile analysis circuit is provided at least with e.g. a sample point extract circuit 15 that samples is a pilot carrier having a pilot signal and decreases number of sample points at a decreased sample point interval and with a fast Fourier transform(FFT) circuit 17 that applies inverse Fourier transform to the pilot carrier with a small number of sample points from the sample point extract circuit 15.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an orthogonal frequency division multiplexing (orthogonal frequency division multiplex) modulation method for modulating a plurality of orthogonal carriers with a data code.
quency Division Multiplex
ing: hereinafter referred to as an OFDM system).

[0002]

2. Description of the Related Art In recent years, in the field of wireless devices, the OFDM system has attracted the spotlight as a modulation system that is resistant to multipath fading, and is being used in fields such as next-generation television broadcasting, FPU, and wireless LAN in various countries including Europe and Japan. Many applied researches are underway. Among them, the UHF band digital terrestrial broadcasting system is described in Journal of the Institute of Image Information and Television Engineers 1998V
ol. 52, no. 11 is described in detail.

A method of calculating a delay profile for a received signal modulated by the broadcasting method is disclosed in Japanese Patent Laid-Open No. 2000-13.
It has already been proposed in Japanese Patent No. 4176. The present invention relates to a method for calculating the delay profile. However, since the carrier structure of the UHF band terrestrial digital broadcasting system used in the description of the proposed patent is very complicated, the parts related to the present invention are described below. A case where a simpler carrier wave structure is used will be described as an example.

In the OFDM system, as shown in FIG. 10, N (N is a positive integer) orthogonal to each other, for example, about 1400 carriers (carriers) are provided within a certain transmission bandwidth, and information is provided. 64QA specified carrier by code
This is a modulation method for transmitting by modulating with a modulation method such as M.

FIG. 11 is an enlarged view of a part of the carrier structure for more detailed explanation. It can be considered that a similar structure is repeated over the entire transmission band.

In FIG. 11, "□" arranged in the horizontal direction represents one carrier 21 respectively. "□" in one row is O
One symbol constituting the FDM signal is represented, and the vertical direction represents the passage of time.

"□" written as "CP" indicates a pilot signal P used to reproduce a reference signal required for demodulation.
The position of is shown. In addition, "□" with nothing written
Represents a signal position modulated by 64QAM. In the terrestrial digital broadcasting system in the UHF band in Japan, the pilot signal P is arranged at positions scattered in the frequency direction and the time direction, such as "□" written as SP in FIG. Therefore, the pilot signal P is SP (Sca
tered Pilot). However, since the pilot signal P is continuously inserted in the time direction in the carrier structure of FIG.
P (Continuous Pilot) is shown.

FIG. 13 is a circuit diagram showing a part related to the present invention extracted from a circuit constituting an OFDM transmission apparatus. The information code input to the transmission preprocessing circuit 1 is converted into a signal of each sample clock in FIG. 11 by preprocessing such as conversion to an error correction code, modulation to 64QAM, and insertion of a CP carrier according to FIG. The signal is converted into a signal sequence of a frequency distribution image of 2048 (one of the powers of 2 11 and one of the powers of 2) representing the signals of the carriers arranged in a horizontal line. The converted signal sequence is input to an IFFT 2k circuit 2 that performs an inverse Fourier transform (IFFT) of 2048 points, and is converted into a signal sequence representing a time waveform composed of the same 2048 sample clock signal.

FIG. 14 schematically shows a time waveform transmitted from the transmitting apparatus. The IFFT 2k circuit 2 shown in FIG. 13 outputs a time waveform during the effective symbol length Ts of the OFDM signal. The guard interval insertion circuit 3 is a circuit for copying and inserting a portion b in the time waveform of the period Ts into a portion b '. The signal in the symbol period Ts' into which the guard interval has been inserted in this manner is further subjected to quadrature modulation, D / A
After being subjected to post-processing such as conversion and up-conversion, it is transmitted from the antenna 5.

In the receiving apparatus shown in FIG. 1, a signal received by the antenna 6 is subjected to pre-processing such as down-conversion, A / D conversion, and quadrature demodulation in a reception pre-processing circuit 7, and then to a signal extraction circuit 8 And Ts in FIG.
A signal sequence of 2048 samples corresponding to the period is cut out. The cut-out signal sequence is input to the FFT 2k circuit 9 which performs a Fourier transform (FFT) of 2048 points, and is returned to a horizontal signal sequence of FIG. 11 which is a signal sequence of a frequency distribution image.

In order to demodulate a signal modulated by 64QAM, as described in a general textbook,
A reference signal corresponding to a ruler in the signal space is required.
The pilot signal CP in FIG. 11 is a signal inserted to enable the reproduction of the reference signal. For example, FIG.
The reference signal for one carrier 21 is a plurality of CP signals in the same symbol arranged near this carrier.
The signal is calculated by interpolation from signals such as 1 and CP2, and 64QAM demodulation is performed using the calculated reference signal.
The post-reception processing circuit 10 shown in FIG. 15 is a circuit that performs post-processing such as demodulation of 64QAM and code error correction of a demodulated code. The code output from the post-reception processing circuit 10 is output from the receiving device as a decoded information code.

In FIG. 15, a portion surrounded by a broken line is
This is a delay profile analysis circuit unit that implements the method proposed in Japanese Patent Application Laid-Open No. 2000-134176.

The signal sequence output from the FFT 2k circuit 9 is input to a pilot carrier (hereinafter referred to as P carrier) extraction & zero insertion circuit 11. Then, the CP carrier signal is extracted from the output signal of the FFT 2k circuit 9 schematically shown in FIG. 16A, and the signal values of the remaining carriers are output as zero as shown in FIG. 16B. .

The signal sequence obtained by extracting the CP is OFD
2048 points same as FFT used in demodulation of M signal
Is input to the FFT2k circuit 12 of FIG. IF
FIG. 17 shows an example of a signal waveform output from the FT2k circuit 12.
Shown in The one-symbol signal output from the IFFT2k circuit 12 is a signal of the 048th to 2047th 2048 sample clocks, and in the carrier structure of FIG.
(A) to (h) because they are inserted every 8 carriers
The same waveform is repeatedly repeated eight times up to this point.
The position of the largest main impulse in FIG. 17 is shown in FIG.
(A), the IFFT 2k circuit 2 of the transmitting device
This is an impulse position generated when the FT Ts portion is cut out and there is a signal component input to the FFT 2 k circuit 9. In the receiving apparatus, synchronization is drawn so that the received main wave comes to the position shown in FIG. 18A, so that the main wave appears at the position of the main wave impulse.

The delayed wave impulse represents the existence of a component delayed with respect to the main wave as shown in FIG. 18B, and the preceding wave impulse represents the component preceding the main wave as shown in FIG. Represents the existence of Therefore, in the delay profile generation circuit 13 of FIG. 15, any one of the eight repeated regions, for example, the portion of FIG.
A signal in the region of three sample clocks is extracted, and the absolute value or the square of the absolute value is output as a delay profile signal as shown in FIG. By displaying this signal using an oscilloscope or the like, the delay profile of the received signal can be observed.

The delay profile signal is shown in FIG.
To detect the position of the main wave from the peak position, detect the timing shift of the signal cut out by the signal cutout circuit 8 based on the detected position data, and control the timing. . This allows
Control can be performed such that the Ts portion of the main wave is at an ideal timing position.

Since the actual time value of the delay time observable in FIG. 19, for example, a value such as ± 83 μsec, changes depending on the sample clock frequency of the FFT2k circuit, the delay time in FIG. 19 is shown by the number of sample clocks.

[0018]

By the way, in the delay profile analysis circuit unit for implementing the conventional delay profile calculation method, the F48 of 2048 points which is the same as the number of points of the FFT used in the demodulation of the OFDM signal is used.
An FFT2k circuit 12 capable of performing FT is required. However, at present, it is difficult to obtain an FFT exceeding 1024 points, and it is necessary to design and manufacture an IC having a large gate scale, which makes it an extremely expensive component.
Therefore, the use of the 2048-point FFT2k circuit 12 to obtain the delay profile has a first problem that it becomes a great obstacle to downsizing and cost reduction of the circuit of the receiving device.

The waveform of the delay profile obtained by wireless transmission usually has a waveform as shown in FIG. 19B, and the range in which the delayed waves are distributed is wider than the range in which the preceding waves are distributed. Therefore, it is necessary to observe a delayed wave in a wider range than the preceding wave. However, in the conventional delay profile analysis circuit, the observation range of the preceding wave is equal to the observation range of the delayed wave as shown in FIG. There is a second problem that an imbalance that the range is insufficient occurs.

When a signal containing only the main wave is subjected to FFT, the detailed waveform of the impulse output from the FFT 2k circuit 12 is as shown in FIG. And a non-negligible false signal appears at the position of the preceding wave. Therefore, there is a third problem that it is difficult to observe the original delayed wave and the preceding wave.

A first object of the present invention is to provide a circuit for analyzing a delay profile of a received signal of an orthogonal frequency division multiplex modulation system, which can be used to calculate a delay profile using a small and inexpensive FFT. It is to provide a device.

A second object of the present invention is to make the range in which a delayed wave can be observed wider than the range in which a preceding wave can be observed while maintaining the entire time width in which a delay profile such as ± 83 μsec can be observed. It is an object of the present invention to provide an apparatus having a circuit for analyzing a delay profile of a received signal of the orthogonal frequency division multiplex modulation method, which can display a delay profile in a well-balanced range that matches a profile distribution.

A third object of the present invention is to provide a quadrature frequency division system capable of reducing the level of a false signal appearing at the position of a delay wave or a preceding wave with a detailed waveform of an impulse and obtaining a distribution waveform of an accurate delay profile. It is an object of the present invention to provide an apparatus having a circuit for analyzing a delay profile of a multiplex modulation received signal.

[0024]

SUMMARY OF THE INVENTION The present invention relates to an orthogonal frequency division multiplexing (OFDM) system, which is a modulation system for modulating a plurality of orthogonal carriers (carriers) with an information code and a pilot signal for transmission. An apparatus having a delay profile analysis circuit for analyzing a delay profile of a modulated reception signal (OFDM signal), wherein the delay profile analysis circuit samples a pilot carrier having the pilot signal and fills a sample point to obtain a sample point. A reception signal of an orthogonal frequency division multiplex modulation system, comprising at least a sample point extraction circuit for reducing the number of signals, and an FFT circuit for performing a Fourier transform on the pilot carrier having a small number of sample points from the sample point extraction circuit. Delay profile It is a device having a circuit for analyzing.

According to the present invention, the number of sample points of the FFT circuit is smaller than the number of sample points of the inverse Fourier transform (IFFT) performed by modulating the OFDM signal or the Fourier transform (FFT) performed by demodulation. An apparatus having a circuit for analyzing a delay profile of a received signal of an orthogonal frequency division multiplex modulation method characterized by the following.

According to the present invention, the OFDM signal is an OFDM signal obtained by inserting a pilot carrier having the pilot signal between a plurality of carriers for every n (n is a positive integer), and The number of sample points Mprofile of the FFT circuit of the analysis circuit is determined by an inverse Fourier transform (IF) performed by modulating the OFDM signal.
FT) or Fourier transform (FFT) performed by demodulation
And a circuit for analyzing a delay profile of a received signal of the orthogonal frequency division multiplex modulation method, which is an integer value equal to or greater than 1 / n of the number of sample points Nofdm.

According to the present invention, there is provided an apparatus having a circuit for analyzing a delay profile of a received signal of an orthogonal frequency division multiplex modulation system, wherein the integer value is a power of 2.

The present invention is characterized in that the sample point extracting circuit changes pilot signals inserted every n lines between the OFDM signals into signals continuously arranged for each sample clock. This is an apparatus having a circuit for analyzing a delay profile of a received signal of the frequency division multiplex modulation method.

The present invention is characterized in that the sample point extracting circuit converts a pilot carrier signal calculated by interpolating the pilot signal in the time direction into a signal continuously arranged for each sample clock, or This is an apparatus having a circuit for analyzing a delay profile of a received signal of the orthogonal frequency division multiplex modulation method, which is characterized by changing to a signal arranged continuously for each clock.

According to the present invention, the sample point extracting circuit may be the same as an interval n of a carrier into which a pilot carrier having the pilot signal is inserted among reference signals obtained by interpolating the pilot signal in the frequency direction. A quadrature frequency characterized in that a signal obtained by selecting a reference signal at intervals is changed to a signal continuously arranged for each sample clock, or to a signal continuously arranged for every less than n sample clocks. This is an apparatus having a circuit for analyzing a delay profile of a received signal of the division multiplex modulation scheme.

According to the present invention, the sample point extracting circuit converts the pilot carrier signal among the reference signals calculated by further interpolating in the frequency direction the pilot carrier signal calculated by interpolating the pilot signal in the time direction. Analyzing the delay profile of a received signal of the orthogonal frequency division multiplex modulation method, wherein the signal is changed to a signal arranged continuously for each sample clock, or is changed to a signal arranged continuously for every less than n sample clocks. This is a device having a circuit for performing the above.

The present invention is characterized in that a smooth curve such as a Hamming window or a Kaiser window is provided between the sample point extraction circuit and the FFT circuit on the pilot carrier having the small number of sample points from the sample point extraction circuit. Analyzing a delay profile of a received signal of the orthogonal frequency division multiplex modulation system, further comprising a window function multiplying circuit for multiplying a window function to be attached, wherein a signal passed through the window function multiplying circuit is supplied to the FFT circuit. This is a device having a circuit for performing the above.

According to the present invention, a received signal (OFDM system) modulated by an orthogonal frequency division multiplexing modulation system (OFDM system), which is a modulation system for modulating a plurality of orthogonal carrier waves (carriers) with an information code and a pilot signal for transmission. An apparatus having a delay profile analysis circuit for analyzing a delay profile of an OFDM signal), wherein the delay profile analysis circuit samples a pilot carrier having the pilot signal and outputs a signal repeated with a period of M sample clocks An extraction circuit; an FFT circuit for performing a Fourier transform on the pilot carrier from the sample point extraction circuit; and a signal in a range preceding the impulse representing the position of the main wave in the signal of the M sample clock in time. Section of the M sample clock signal And a delay profile generation circuit that cyclically moves to a region further delayed than a signal in a range delayed from the main wave and outputs a part of the moved signal as a signal in a range indicating the presence of a delayed wave. An apparatus having a circuit for analyzing a delay profile of a received signal of the orthogonal frequency division multiplex modulation method characterized by the above-mentioned.

[0034]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a circuit configuration of a receiving apparatus and a delay profile analysis circuit according to a first embodiment of the present invention. The only difference from the conventional circuit is the configuration of the delay profile analysis circuit section surrounded by a broken line. Therefore, the following description will focus on the circuit configuration and operation of the delay profile analysis circuit section.

In the same manner as in the conventional circuit, the signal train output from the FFT 2k circuit 9 is obtained by extracting the pilot carrier (P carrier) and the P pilot carrier (P carrier) extracted in place of the zero insertion circuit 11 in FIG. & Input to the rearrangement circuit 15. This circuit 15 extracts the CP carrier signal in the same manner as the P carrier extraction & zero insertion circuit 11, but instead of replacing the signal values of the remaining carriers with zero, the signal values are packed as shown in FIG. Number 25
6, and continuously rearranged for each sample clock and output.

The next window function multiplying circuit 16 is connected to the subsequent FFT
This circuit multiplies a signal input to the 256 circuit 17 by a window function characterized by a smooth curve such as a Hamming window or a Kaiser window. The signal output from the FFT 2k circuit 9 has a waveform as shown by a solid rectangle in FIG. FIG. 16 (a) or FIG. 2 (a)
FIG. 4A is an enlarged view of a part of FIG.

The false signal described in the third problem is the one shown in FIG.
This is due to the vibration component generated because the waveform (a) is rectangular. In the frequency analysis, in such a case, the FFT is performed by multiplying the entire signal having a width of 2048 points to be subjected to the FFT by a window function such as a Hamming window or a Kaiser window formed of a smooth curve, as shown by a broken line curve, and performing the FFT. Perform the process of holding down the level.

However, in the case of the waveform shown in FIG. 3A, a rectangular waveform remains at the center of the range of the effective number of samples, so that an effective reduction effect cannot be obtained. Therefore, in the present embodiment, as shown in FIG. 3C, the A portion of the signal of FIG. 3B obtained by extracting only the CP carrier by the After eliminating the rectangular waveform by shifting to the position after the portion, the output is multiplied by a window function indicated by a broken curve. In this case, since valid signals are continuously arranged, no rectangular waveform appears inside the window function. Therefore, the level of the false signal shown in FIG. 20 can be significantly reduced, and the third problem can be solved.

However, the switching of the signal from FIG. 3B to FIG. 3C described above is based on the P carrier extraction &
The circuit is simpler to implement with the reordering circuit 15.

FIG. 4 shows an example of the internal circuit configuration of the pilot carrier extracting and rearranging circuit 15.
The signal sequence output from the FFT 2k circuit 9 in FIG. 1 is input to the switch 151. 3A is input to the FIFO 152, and the portion B is input to the FIFO 153.

In the FIFO 152, the enable pulse E
Under the control of Na 1/8, a signal of the CP carrier inserted every 8 sample clocks into the portion A is selected and F
It is stored in the IFO 152. Similarly, in the FIFO 153, under control of the enable pulse ENb1 / 8, the signal of the CP carrier of the portion B is selected and stored in the FIFO 153.

On the other hand, on the output side of the FIFO 153, under appropriate control of the enable pulse ENb 1, the CP signal stored inside is continuously read every sample clock, starting at an appropriate timing, and is output to the outside through the switch 154. Output. On the output side of the FIFO 152, under the control of the enable pulse ENa1, the CP signal of the portion A stored therein is read continuously after reading the CP signal of the portion B from the FIFO 153. Output to the outside through 154.

By this processing, the signal sequence shown in FIG. 3C is output from the P carrier extraction and rearrangement circuit 15. In the window function multiplying circuit 16, only the multiplication of the signal sequence shown in FIG.

The signal sequence of FIG. 3C multiplied by the window function by the window function multiplying circuit 16 is represented by the FFT 256 circuit 17 of FIG.
Is input to By the way, in the carrier structure of FIG.
Since P is inserted every 8 carriers, (c) in FIG.
The number of sample clocks having a significant value in the signal sequence of FIG. 3 is about 1 in the A portion and the B portion of the signal sequence of FIG.
This is only 176 points, 1/8 of 400 samples. Therefore, when the FFT of the number of sample points of a power of 2 is used, if the FFT of 256 sample points is performed, the frequency conversion of the significant signal sequence shown in FIG. 3C can be performed. The FFT 256 circuit 17 is a circuit that performs an FFT of 256 sample points, which is the minimum number of sample points that can perform this conversion. The number of sample points Mprofile = 256 is only 1/8 of the number of sample points Nofdm = 2048 of the IFFT performed by the modulation of the OFDM signal or the FFT performed by the demodulation.
The circuit can be constituted by a small and low-cost circuit that solves the above problem.

The FFT 256 circuit 17 includes (c) in FIG.
The part shown in FIG.
Output the FFT result of 6 sample points. FIG. 5A schematically shows the waveform of the signal output from the FFT 256 circuit 17, and is a waveform obtained by extracting only the portion of FIG. 17A located at both ends. This waveform is different from the case where the portion of FIG. 17B is extracted by the conventional circuit, and the time is reversed before and after the 128th sample clock. The delay profile generation circuit 18 in FIG. 1 is a circuit for changing the order, and can be realized by a circuit similar to that in FIG. As shown in FIG. 5B, when the order is changed after the 128th sample clock, the conventional FIG.
(A), the same delay profile waveform can be obtained.

The impulse 18 shown in FIG.
1 is at the position of the preceding wave with respect to the main wave. However, it can be considered that an impulse due to a delayed wave delayed by 128 sample clock periods or more with respect to the main wave is generated by being turned back by the FFT. In an OFDM signal having the carrier arrangement of FIG. 11 having a CP carrier for every eight carriers, it cannot be determined in principle whether the impulse 181 is caused by a preceding wave or a delayed wave. However, in a normal delay profile distribution, as shown in FIG. 19B, the range in which the preceding wave is distributed is wider than the range in which the delayed waves are distributed. Therefore, an impulse generated at a position that precedes the main wave like the impulse 181 in FIG. 5A is more likely to be generated by an impulse generated by a delayed wave delayed by 128 sample clock periods or more than the main wave. it is conceivable that.

Therefore, in the present embodiment, the delay profile generation circuit 18 shown in FIG. 1 uses the FFT as shown in FIG.
The order is cyclically changed with a sample clock at a position further shifted by, for example, 64 samples from the 128th sample clock which is the middle point of the range of the number of points. as a result,
As shown in FIG. 5D, the imbalance between the observation range of the preceding wave and the observation range of the delayed wave is eliminated, and the possibility that the delayed wave is mistaken for the preceding wave can be reduced. Can be solved. Note that this case corresponds to the case where the cycle M at which the signal output from the FFT circuit is repeated is equal to the number of sample points 256 of the FFT circuit.

The procedure for observing the delay profile using the signal output from the delay profile generation circuit 18 and the procedure for controlling the signal extraction circuit 8 by inputting the signal to the peak detection circuit 14 are the same as those in the related art, and thus description thereof will be omitted. .

As described above, when the delay profile analysis circuit according to the present embodiment is used, the number of sample points Nofdm = 2048 of the IFFT performed by the modulation of the OFDM signal or the FFT performed by the demodulation is reduced to 1/8 of the number of the sample points. Number of sample points Mprofile = 256
The operation is possible if there is an (<Nofdm) FFT circuit.
This eliminates the need for an FFT circuit having a large number of sample points, which is difficult to obtain and is an extremely expensive part, and solves the first problem described above to reduce the size and cost of an apparatus having a delay profile analysis circuit. Can be realized.

Further, since the above-mentioned imbalance between the observation range of the preceding wave and the observation range of the delayed wave, which is the second problem, can be eliminated, the waste of the observation range of the preceding wave can be reduced and the delayed waves in a wide range can be observed. become able to.

Further, the level of a false signal generated at the position of a delayed wave or a preceding wave can be reduced. Therefore, the third problem that makes it difficult to observe the original delayed wave and the preceding wave can be solved.

Next, FIG. 6 shows a circuit configuration of a receiving apparatus and a delay profile analyzing circuit according to a second embodiment of the present invention. In this embodiment, the present invention is applied to the case of a carrier structure similar to the terrestrial digital broadcasting system in the UHF band in Japan. That is, the pilot signal P
This is applied to the case of a carrier structure arranged in a frequency direction and a time direction like “□” written as SP of No. 2.

In the case of the carrier structure shown in FIG. 12, the received signal is demodulated by first inserting a reference signal (pilot carrier signal) of a pilot carrier indicated by oblique lines by interpolating the SP in the time direction.
Is calculated. The arrangement of the pilot carriers indicated by hatching in FIG. 12 is the same as the arrangement of the CP carriers in FIG. 11 except that the period n at which the pilot carriers are inserted is changed to three carriers. Therefore, if a pilot carrier signal obtained by interpolation in the time direction is input to the delay profile analysis circuit instead of the CP carrier signal in the first embodiment, the delay profile is calculated in the same manner as in the first embodiment. be able to.

In the circuit of FIG. 6, an SP time direction interpolation circuit 19 is a circuit for calculating a pilot carrier signal by interpolating the SP of FIG. 12 in the time direction. The output signal of this circuit is a delay surrounded by a broken line. The difference from the circuit of FIG. 1 is that the data is input to the profile analysis circuit.

In the carrier structure according to the present embodiment, since the number of pilot carriers increases from about 1400/8 = 176 to about 1400/3 = 467, the number of FFT points needs to be increased from 256 points to 512 points. . Therefore, the 256-point FFT 25 shown in FIG.
6 circuits 17 are replaced by 512-point FFT 512 circuits 17 '
Was replaced.

However, the other circuits, ie, the P carrier extraction and rearrangement circuit 15, the window function multiplication circuit 16, and the delay profile generation circuit 18, have the cycle n of the pilot carrier.
Is the same circuit except that every 8 carriers are changed every 3 carriers. Therefore, the operation of each circuit in FIG. 6 is essentially the same as that in the first embodiment, and it is obvious that the same effect as in the first embodiment can be obtained. Therefore, in this embodiment, a detailed description of the operation of the circuit will be omitted.

As described above, also in the delay profile analysis circuit according to the present embodiment, the number of points of the IFFT performed by the modulation of the OFDM signal or the FFT performed by the demodulation is only 1/4 of the number of points Nofdm = 2048. If there is an FFT circuit of the number Mprofile = 512 (<Nofdm), the operation can be performed. For this reason, FFs with a large number of points that are difficult to obtain and are extremely expensive parts
Since the T circuit is not required, the first problem described above can be solved, and the device having the delay profile analysis circuit can be reduced in size and cost. It is clear that the second and third problems described above can be solved similarly to the first embodiment.

Next, FIG. 7 shows a circuit configuration of a receiving apparatus and a delay profile analyzing circuit according to a third embodiment of the present invention. As described in FIG. 3A, the FFT2k circuit 9
Are separated and output in the order A and B, and the order of all carrier positions including the data carrier is changed as shown in FIG. 8B. If they are replaced in advance, there is an advantage that signal processing performed by the post-reception processing circuit 10 becomes easy, such as an operation of calculating a reference signal of each carrier by interpolating the CP signal in the frequency direction. The circuit shown in FIG. 7 is a circuit configuration when the present invention is applied to such a case.

In FIG. 7, an up / down switching circuit 20 is a circuit for changing the order of the carrier positions in advance. The content of the signal processing performed by the delay profile analysis circuit section surrounded by the broken line is the same as that of the first embodiment, but the P carrier extraction & rearrangement circuit 15 of FIG. The exchange of the carrier order of c) is performed by the upper / lower exchange circuit 20 and becomes unnecessary. Therefore, the processing performed by the P carrier extraction & rearrangement circuit 15 ′
Only the process of continuously rearranging and outputting carrier signals for each sample clock is required, and the configuration of the internal circuit can be simplified as shown in FIG. The other signal processing methods of the delay profile analysis circuit are the same as those of the first embodiment, and the description is omitted. As described above, in the present embodiment, the same carrier structure as that of the first embodiment, that is, the case of the carrier structure of FIG. 11 has been described as an example, but the same effect can be obtained in the case of the carrier structure of FIG. It is clear.

As described above, in the present embodiment, the first
Not only the same effects as those of the embodiment described above can be obtained, but also the effect that the circuit configuration of the P carrier extraction and rearrangement circuit 15 'can be downsized can be obtained.

The FFT of the delay profile analysis circuit
The position where the signal input to the 256 circuit 17 or the FFT 512 circuit 17 'is cut out from the signal shown in FIG. 3C does not necessarily need to start from the portion B as shown in FIG. If all the signals of the portion A are included, a slightly shifted position may be cut out as shown in FIG. In this case, the FFT 256 circuit 17 or the FFT
Although the phase angle of the signal output from the 512 circuit 17 'rotates, no problem occurs because only the amplitude component is required in the delay profile analysis.

Further, in the first embodiment, as shown in FIG. 3C, the portion B and the portion A are rearranged continuously and then multiplied by the window function of the broken line curve. (F) of FIG.
As described above, instead of changing the order of the portion B and the portion A, the window function of the dashed curve may be divided and the window functions of the portion A and the portion B may be individually multiplied. This is FF
In T, inverse Fourier transform is performed assuming that an input signal is repeated indefinitely, but a detailed description will be given to a textbook on Fourier transform.

In the above description, FFT and IFFT are all assumed to be powers of two. this is,
This is because it is difficult to configure a circuit that performs an FFT or IFFT operation on a number of sample points other than a power of two. However, it should be noted that when processing is performed by a DSP or a program, it is not necessarily required to be a power of two.

In the above description, the size of the FFT circuit of the delay profile analysis circuit is minimized.
The case where the number of sample points is set to the minimum power of 2 has been described as an example. However, the number of FFT sample points Nof
Number of sample points less than dm Mprofile (<Nofd
If the FFT circuit of m) is used, the same effect can be obtained although the effect is reduced with respect to the miniaturization and cost reduction of the circuit.

In this case, for example, a method in which the range cut out from FIG. 3C is simply increased from 256 points to 512 points to execute FFT, and FIG.
Instead of arranging CPs continuously, a method of cutting out a signal arranged continuously for every sample clock less than n, for example, a signal of 512 points of a signal formed by arranging CP signals and zero signals alternately and performing FFT. There is.

In the case of the latter method, the output waveform of the FFT is a waveform in which a waveform corresponding to the region of FIG. 17B is inserted between the waveform of FIG. 5A. Therefore, a delay profile can be obtained only by extracting the portion corresponding to (b), and the effect that the delay profile generation circuit 18 can be simplified and downsized can be obtained. On the other hand, in the former case, the effect of increasing the resolution in the time direction of the calculated delay profile can be obtained.

In the above description, an example has been described in which the delay profile analysis circuit extracts the pilot carrier signal calculated by interpolating the CP carrier signal or the SP signal in the time direction. However, a reference signal obtained by interpolation in the frequency direction calculated inside the post-reception processing circuit 10 is input, and a reference signal having the same cycle as the cycle n of the CP carrier or pilot carrier is sequentially extracted at an arbitrary timing and used. Is also good.

In the above description, FIG. 11 or FIG.
Although the case has been described in which the signals of all the inserted CP carriers or pilot carriers are extracted and input to the FFT of the delay profile analysis circuit in step 2, only a part of them may be extracted and input. However, in this case, the resolution of the delay time of the calculated delay profile is reduced. Therefore, when the OFDM signal is obtained by inserting the pilot signal P every n lines between N carriers, the number of points Mprofile of the FFT circuit included in the delay profile analysis circuit is the minimum Mprofile which is greater than or equal to Nofdm / n. (= Ceil (Nofdm / n)) or the minimum power of two.

The delay profile generation circuit 18 used in the first embodiment can be used instead of the delay profile generation circuit 13 of the conventional circuit shown in FIG. In this case, even in the conventional circuit, the unbalance between the observation range of the preceding wave and the observation range of the delayed wave, which is the second problem, can be eliminated, and the observation range of the preceding wave can be reduced. It can be made observable. In this case, the repetition period M of the signal output from the FFT circuit is 256, which is ８ of the number of points 2048 of the FFT.
This corresponds to the case of the sample clock cycle.

Although the case of the receiving apparatus has been described above as an example, it goes without saying that the same effect can be obtained in a device other than the receiving device such as a delay profile measuring device as long as the device has a delay profile measuring circuit. No.

[0071]

According to the present invention, there is provided an apparatus having a circuit for analyzing a delay profile of a received signal of an orthogonal frequency division multiplex modulation system, which can calculate a delay profile using a small and inexpensive FFT. Can be provided. Further, according to the present invention, the range in which the delayed wave can be observed can be made wider than the range in which the preceding wave can be observed while maintaining the entire time width in which the delay profile of ± 83 μsec or the like can be observed. It is possible to provide an apparatus having a circuit for analyzing a delay profile of a received signal of the orthogonal frequency division multiplexing modulation method capable of displaying a delay profile in a well-balanced range. Furthermore, according to the present invention, the reception of the orthogonal frequency division multiplexing modulation method capable of reducing the level of a false signal appearing at the position of a delay wave or a preceding wave with a detailed waveform of an impulse and obtaining a distribution waveform of an accurate delay profile An apparatus having a circuit for analyzing a delay profile of a signal can be provided.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a circuit configuration of a receiving device and a delay profile analysis circuit unit according to a first embodiment of the present invention.

FIG. 2 is a diagram for explaining the operation of a P (pilot) carrier extraction and rearrangement circuit of FIG. 1;

FIG. 3 is a diagram for explaining the operation of the delay profile analysis circuit according to the present invention.

FIG. 4 is a diagram showing an example of a circuit configuration of a P (pilot) carrier extraction and rearrangement circuit of FIG. 1;

FIG. 5 is a diagram illustrating the operation of the delay profile generation circuit of FIG. 1;

FIG. 6 is a diagram illustrating a circuit configuration of a receiving device and a delay profile analysis circuit unit according to a second embodiment of the present invention.

FIG. 7 is a diagram illustrating a circuit configuration of a receiving device and a delay profile analysis circuit unit according to a third embodiment of the present invention.

FIG. 8 is a diagram illustrating the operation of the delay profile analysis circuit unit of FIG. 7;

9 is a diagram showing a circuit configuration of a P (pilot) carrier extraction and rearrangement circuit of FIG. 7;

FIG. 10 is a diagram illustrating a carrier structure of the OFDM system.

FIG. 11 is a diagram illustrating a carrier structure in which CPs are arranged as pilot signals.

FIG. 12 is a diagram illustrating a carrier structure in which an SP is arranged as a pilot signal.

FIG. 13 is a diagram illustrating a circuit configuration of a transmission device.

FIG. 14 is a diagram illustrating a time waveform of an OFDM signal.

FIG. 15 is a diagram illustrating a circuit configuration of a conventional receiving device and a delay profile analysis circuit unit.

FIG. 16 is a diagram illustrating signal processing of a conventional delay profile analysis circuit unit.

FIG. 17 shows a conventional delay profile analysis circuit section IFF.
FIG. 4 is a diagram illustrating an output waveform of a T circuit.

FIG. 18 is a diagram illustrating a time relationship among a main wave, a delayed wave, and a preceding wave.

FIG. 19 is a diagram illustrating a delay profile waveform obtained by a conventional delay profile analysis circuit unit.

FIG. 20 is a diagram illustrating a false signal appearing in a delay profile waveform obtained by a conventional delay profile analysis circuit unit.

[Explanation of symbols]

1: pre-transmission processing circuit, 2: IFFT 2k circuit, 3: guard interval insertion circuit, 4: post-transmission processing circuit, 5,
6: antenna, 7: pre-reception processing circuit, 8: signal extraction circuit, 9: FFT2k circuit, 10: reception post-processing circuit, 1
1: P carrier extraction & zero insertion circuit, 12: FFT2k
Circuit, 13: delay profile generation circuit, 14: peak detection circuit, 15: P carrier extraction & rearrangement circuit, 1
6: window function multiplying circuit, 17: FFT 256 circuit, 1
7 ': FFT 512 circuit, 18: delay profile generation circuit, 19: SP time direction interpolation circuit, 20: vertical exchange circuit, 151, 154: switch, 152, 153: FI
FO.

Claims (10)

[Claims] 1. A received signal modulated by an orthogonal frequency division multiplexing (OFDM) system, which is a modulation system for modulating and transmitting each of a plurality of carrier waves orthogonal to each other with an information code and a pilot signal. An apparatus having a delay profile analysis circuit for analyzing a delay profile of an (OFDM signal), wherein the delay profile analysis circuit samples a pilot carrier having the pilot signal and fills sample point positions to reduce the number of sample points. Analyzing a delay profile of a received signal of an orthogonal frequency division multiplex modulation system, comprising at least a point extracting circuit and an FFT circuit for performing a Fourier transform on the pilot carrier having a small number of sample points from the sample point extracting circuit. Circuit Equipment having. 2. The method according to claim 1, wherein the number of sample points of the FFT circuit is smaller than the number of sample points of an inverse Fourier transform (IFFT) performed by modulation of the OFDM signal or a Fourier transform (FFT) performed by demodulation. An apparatus having a circuit for analyzing a delay profile of a received signal of the orthogonal frequency division multiplex modulation method, wherein the number is the number of sample points. 3. The OFDM signal according to claim 2, wherein the OFDM signal is obtained by inserting a pilot carrier having the pilot signal between N carriers every n carriers.
The FF of the delay profile analysis circuit.
The number of sample points Mprofile of the T circuit is equal to the OFD
Orthogonal frequency division multiplexing modulation characterized by an integer value equal to or greater than the number of sample points Nofdm / n of an inverse Fourier transform (IFFT) performed by modulating the M signal or a Fourier transform (FFT) performed by demodulation. An apparatus having a circuit for analyzing a delay profile of a reception signal of a system. 4. The apparatus according to claim 3, wherein said integer value is a power of two, and further comprising a circuit for analyzing a delay profile of a received signal of the orthogonal frequency division multiplexing modulation method. 5. The sample point extracting circuit according to claim 3, wherein the sample point extracting circuit changes pilot signals inserted every n lines between the OFDM signals into signals continuously arranged for each sample clock. Alternatively, there is provided an apparatus having a circuit for analyzing a delay profile of a received signal of the orthogonal frequency division multiplex modulation scheme, wherein the signal is changed to a signal arranged continuously for every less than n sample clocks. 6. The apparatus according to claim 3, wherein the sample point extracting circuit changes a pilot carrier signal calculated by interpolating the pilot signal in a time direction into a signal continuously arranged for each sample clock. n
An apparatus having a circuit for analyzing a delay profile of a received signal of the orthogonal frequency division multiplex modulation method, wherein the signal is changed to a signal arranged continuously for each less sample clock. 7. A carrier according to claim 3, wherein said sample point extracting circuit is configured to insert a pilot carrier having the pilot signal among reference signals obtained by interpolating the pilot signal in the frequency direction. The method is characterized in that a signal obtained by selecting a reference signal having the same interval as the interval n is changed to a signal arranged continuously for each sample clock, or to a signal arranged continuously for each sample clock less than n. An apparatus having a circuit for analyzing a delay profile of a received signal of the orthogonal frequency division multiplex modulation method. 8. The signal processing apparatus according to claim 3, wherein said sample point extracting circuit further comprises: a pilot carrier signal calculated by interpolating the pilot signal in the time direction; A pilot carrier signal is changed to a signal arranged continuously for each sample clock, or a pilot signal is converted to a signal arranged continuously for every less than n sample clocks. An apparatus having a circuit for analyzing a delay profile. 9. A pilot carrier having a small number of sample points from the sample point extraction circuit, such as a Hamming window or a Kaiser window, is provided between the sample point extraction circuit and the FFT circuit. Further comprising a window function multiplying circuit for multiplying a window function characterized by a simple curve, wherein a signal passed through the window function multiplying circuit is supplied to the FFT circuit. An apparatus having a circuit for analyzing a delay profile. 10. A delay of a reception signal (OFDM signal) modulated by an orthogonal frequency division multiplexing modulation (OFDM) system, which is a modulation system for modulating and transmitting N orthogonal carriers (carriers) with an information code. An apparatus having a delay profile analysis circuit for analyzing a profile, wherein the delay profile analysis circuit samples a pilot carrier having the pilot signal and outputs a signal repeated with a period of M sample clocks, and a sample point extraction circuit; An FFT circuit for performing a Fourier transform on a pilot carrier from a sample point extracting circuit; Within the range delayed from the main wave in the clock signal A delay profile generation circuit for cyclically moving to a region further delayed from the signal and outputting a part of the moved signal as a signal in a range representing the presence of a delayed wave. An apparatus having a delay profile analysis circuit for analyzing a delay profile of a modulation scheme received signal.