JP2002299397A - System and method for evaluating semiconductor wafer - Google Patents

System and method for evaluating semiconductor wafer

Info

Publication number
JP2002299397A
JP2002299397A JP2001094159A JP2001094159A JP2002299397A JP 2002299397 A JP2002299397 A JP 2002299397A JP 2001094159 A JP2001094159 A JP 2001094159A JP 2001094159 A JP2001094159 A JP 2001094159A JP 2002299397 A JP2002299397 A JP 2002299397A
Authority
JP
Japan
Prior art keywords
semiconductor wafer
oxide film
capacitance
evaluating
surface oxide
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
JP2001094159A
Other languages
Japanese (ja)
Inventor
Sumitaka Kawamura
純孝 河村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP2001094159A priority Critical patent/JP2002299397A/en
Publication of JP2002299397A publication Critical patent/JP2002299397A/en
Abandoned legal-status Critical Current

Links

Abstract

PROBLEM TO BE SOLVED: To provide a system and method for evaluating the state of a semiconductor wafer with high reliability regardless of the environmental variation. SOLUTION: The system for evaluating the state of a semiconductor wafer comprises a means for removing a surface oxide film from a specified region of the semiconductor wafer, and a means for measuring the capacitance by applying a DC bias voltage to the specified region from which the surface oxide film is removed.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、半導体ウエーハの
評価方法に係り、特に半導体ウエーハの容量−電圧特性
を測定する方法に関する。
The present invention relates to a method for evaluating a semiconductor wafer, and more particularly to a method for measuring a capacitance-voltage characteristic of a semiconductor wafer.

【0002】[0002]

【従来の技術】半導体装置の製造工程において、近年特
にそのパターンの微細化に伴い、ウエーハに注入される
不純物の濃度及びその分布をより厳密に制御することが
要求されている。
2. Description of the Related Art In the process of manufacturing a semiconductor device, in recent years, in particular, as the pattern becomes finer, it is required to more strictly control the concentration and distribution of impurities implanted into a wafer.

【0003】そのためにはウエーハの状態を正確に評価
する必要があるが、これまでは図4に示すような評価装
置を用いて容量−電圧測定を行うことで評価を行ってい
た。即ち、まず半導体ウエーハ1を、ステージ2上に載
置する。このウエーハ1上に容量測定プローブ4を配置
し、測定位置調整モータ3により高さ・位置を制御す
る。ウエーハ−プローブ間の距離を距離測定センサー
5、6と調整モータ7により所定の値とした後、その容
量測定プローブ4の両端にDCバイアス電圧を印加してゆ
き、同時にその容量を測定してゆくことにより、容量−
電圧特性、即ちC−Vカーブを得ることができる。そして
このC−Vカーブを解析することにより不純物濃度やその
深さ方向のプロファイル、ライフタイム、イオン注入に
よるダメージ等を求めることができる。
For this purpose, it is necessary to accurately evaluate the state of the wafer. Until now, the evaluation has been performed by measuring the capacitance-voltage using an evaluation apparatus as shown in FIG. That is, first, the semiconductor wafer 1 is placed on the stage 2. A capacitance measuring probe 4 is arranged on the wafer 1, and the height and position are controlled by a measuring position adjusting motor 3. After the distance between the wafer and the probe is set to a predetermined value by the distance measuring sensors 5 and 6 and the adjusting motor 7, a DC bias voltage is applied to both ends of the capacitance measuring probe 4 and the capacitance is measured at the same time. The capacity-
Voltage characteristics, that is, a CV curve can be obtained. By analyzing the CV curve, the impurity concentration, the profile in the depth direction, the lifetime, the damage due to ion implantation, and the like can be obtained.

【0004】しかしながら、このような従来の半導体ウ
エーハの評価装置においては、あくまでも図5に示す等
価回路が成り立つとして、その特性を求めているが、実
際は同一試料であっても半導体ウエーハの表面を覆って
いる自然酸化膜の厚さによりC oxideが変化し、測定値
として得られるトータルの容量Cが変化してしまう。例
えば、エピタキシャル層のn型若しくはp型不純物濃度
を求める際には、エピタキシャル成長炉から取出す半導
体ウエーハの温度、環境が変わることにより、自然酸化
膜の厚さが変化し、C oxideも変化するため、C oxide
を固定値とした等価回路が成立しなくなり、不純物濃度
を正確に求めることができない、といった問題があっ
た。
However, in such a conventional semiconductor wafer evaluation apparatus, the characteristics are required assuming that the equivalent circuit shown in FIG. 5 is established. C oxide changes depending on the thickness of the natural oxide film, and the total capacitance C obtained as a measured value changes. For example, when determining the n-type or p-type impurity concentration of the epitaxial layer, the temperature and environment of the semiconductor wafer taken out of the epitaxial growth furnace change, the thickness of the natural oxide film changes, and the C oxide also changes. C oxide
There is a problem that an equivalent circuit with a fixed value is not established, and the impurity concentration cannot be obtained accurately.

【0005】[0005]

【発明が解決しようとする課題】この様に、従来は、同
一試料においても測定値が環境により変化してしまうた
め、容量―電圧測定の精度が低下し、不純物濃度分布
等、ウエーハ状態の評価が正確にできないといった問題
があった。
As described above, in the prior art, since the measurement value changes depending on the environment even in the same sample, the accuracy of the capacitance-voltage measurement is reduced, and the evaluation of the wafer state such as the impurity concentration distribution is performed. There was a problem that can not be accurately.

【0006】従って本発明は、このような従来の半導体
ウエーハの評価装置及び評価方法の欠点を取り除き、環
境の変化に因らず信頼性の高いウエーハ状態の評価を行
うことができる半導体ウエーハの評価装置及び評価方法
を提供することを目的とするものである。
Accordingly, the present invention eliminates the drawbacks of the conventional semiconductor wafer evaluation apparatus and the conventional evaluation method, and makes it possible to evaluate a semiconductor wafer with high reliability regardless of environmental changes. It is an object of the present invention to provide an apparatus and an evaluation method.

【0007】[0007]

【課題を解決するための手段】本発明の半導体ウエーハ
の評価装置は、半導体ウエーハの所定領域の表面酸化膜
を除去する手段と、前記表面酸化膜の除去された前記所
定領域に、DCバイアス電圧を印加し、その容量を測定す
る容量測定プローブとを具備することを特徴とする。
According to the present invention, there is provided an apparatus for evaluating a semiconductor wafer, comprising: means for removing a surface oxide film in a predetermined area of the semiconductor wafer; and a DC bias voltage applied to the predetermined area from which the surface oxide film has been removed. And a capacitance measuring probe for measuring the capacitance.

【0008】また、本発明の半導体ウエーハの評価装置
においては、前記表面酸化膜を除去する手段は、半導体
ウエーハの所定領域に薬液を供給し、薬液により表面酸
化膜をエッチングする手段と、その廃液を排出する手段
とを備えることを特徴とする。
In the apparatus for evaluating a semiconductor wafer according to the present invention, the means for removing the surface oxide film includes a means for supplying a chemical solution to a predetermined region of the semiconductor wafer and etching the surface oxide film with the chemical solution, Discharging means.

【0009】さらに、本発明の半導体ウエーハの評価方
法は、半導体ウエーハの所定領域の表面酸化膜を除去し
た後、前記表面酸化膜の除去された前記所定の領域に、
容量測定プローブにより、DCバイアス電圧を印加して、
その容量を測定することを特徴とする。
Further, in the method for evaluating a semiconductor wafer according to the present invention, after removing a surface oxide film in a predetermined region of the semiconductor wafer, the method may further include:
Apply a DC bias voltage with the capacitance measurement probe,
It is characterized in that its capacity is measured.

【0010】[0010]

【発明の実施の形態】以下本発明の実施形態について、
図1乃至3を参照して説明する。
DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below.
This will be described with reference to FIGS.

【0011】図1に示すように、被測定半導体ウエーハ
1を載置するためのステージ2が、測定室内に設けられ
ている。このステージ2は測定位置調整モータ3により
高さ・位置を制御することができる。半導体ウエーハ1
表面に対向するように容量測定プローブ4が配置され、
この容量測定プローブ4には、電極とともに半導体ウエ
ーハ1と容量測定プローブ4との距離を測定するための
距離測定センサー5、6と、その距離を調整するための
距離調整モータ7、及び半導体ウエーハ1表面の酸化膜
を除去するための薬液8を供給するための供給口9及び
酸化膜除去後にその薬液を排出する排出口10が備えら
れている。
As shown in FIG. 1, a stage 2 for mounting a semiconductor wafer 1 to be measured is provided in a measurement chamber. The height and position of the stage 2 can be controlled by a measuring position adjusting motor 3. Semiconductor wafer 1
A capacitance measuring probe 4 is arranged so as to face the surface,
The capacitance measuring probe 4 includes distance measuring sensors 5 and 6 for measuring the distance between the semiconductor wafer 1 and the capacitance measuring probe 4 together with the electrodes, a distance adjusting motor 7 for adjusting the distance, and the semiconductor wafer 1. A supply port 9 for supplying a chemical 8 for removing an oxide film on the surface and an outlet 10 for discharging the chemical after removing the oxide film are provided.

【0012】このような装置において、先ず、粉塵の制
御された測定室を窒素雰囲気とし、数リットル/分の置
換量で窒素を流しておく。そこでステージ2上に表面酸
化膜11の形成されたシリコンウエーハ1を載置し、測
定位置調整モータ3により、位置を調整する。そしてウ
エーハ1と容量測定プローブ4との距離を距離測定セン
サー5、6により測定し、距離調整モータ7により所定
の値とした後、供給口9より薬液8(例えばHF20wt
%溶液)を供給し、5mmφの領域における表面酸化膜
11をエッチングし、シリコンの表面張力を利用して除
去、その廃液を排出口10より吸引することにより排出
する。そして、この酸化膜を除去した領域12上部に設
けられた容量測定プローブ4内の電極よりDCバイアス電
圧を印加し、その容量を測定する。
In such an apparatus, first, a measurement chamber in which dust is controlled is set to a nitrogen atmosphere, and nitrogen is supplied at a replacement rate of several liters / minute. Then, the silicon wafer 1 on which the surface oxide film 11 is formed is placed on the stage 2, and the position is adjusted by the measuring position adjusting motor 3. Then, the distance between the wafer 1 and the capacity measuring probe 4 is measured by the distance measuring sensors 5 and 6, the distance is adjusted to a predetermined value by the distance adjusting motor 7, and the chemical solution 8 (for example, HF 20 wt.
% Solution), the surface oxide film 11 in the region of 5 mmφ is etched, removed using the surface tension of silicon, and the waste liquid is discharged by suction through the discharge port 10. Then, a DC bias voltage is applied from an electrode in the capacitance measurement probe 4 provided above the region 12 from which the oxide film has been removed, and the capacitance is measured.

【0013】このようにして測定された容量より、環境
により変動してしまう酸化膜を含まないサンプルのみの
正確な容量−電圧特性、即ちC−Vカーブを得ることがで
きる。そしてこのC−Vカーブを解析することにより、不
純物濃度その深さ方向のプロファイル、ライフタイム、
イオン注入によるダメージといった半導体ウエーハの状
態の評価を正確に行うことができる。
From the capacitance measured in this way, it is possible to obtain an accurate capacitance-voltage characteristic, that is, a CV curve, of only a sample that does not contain an oxide film and fluctuates due to the environment. By analyzing this C-V curve, the impurity concentration profile in the depth direction, lifetime,
The state of the semiconductor wafer, such as damage due to ion implantation, can be accurately evaluated.

【0014】本実施形態において、酸化膜を除去する薬
液8にHF20wt%溶液を用いたが、特に限定されるも
のではなく、例えば0.5〜50wt%のHF溶液、5〜
50wt%のNH4F溶液等を用いることができる。また、
液体に限定されるものではなく、酸化膜のみを除去する
ことができるものであればよい。例えば、チャンバー内
において、F2やClF3、無水弗酸といった生ガスを吹
き付ける等、気体を用いることも可能である。
In this embodiment, a 20 wt% HF solution is used as the chemical solution 8 for removing the oxide film. However, the present invention is not limited to this. For example, a 0.5 to 50 wt% HF solution,
A 50 wt% NH4F solution or the like can be used. Also,
The material is not limited to a liquid, and may be any material that can remove only an oxide film. For example, it is possible to use a gas such as spraying a raw gas such as F2, ClF3, or hydrofluoric acid in the chamber.

【0015】また、薬液を供給(塗布)して酸化膜を除
去した領域12は、測定が可能となる領域であれば特に
限定されない。通常1〜10mmφ程度で、任意の形状
でよい。
The region 12 from which the oxide film is removed by supplying (applying) the chemical solution is not particularly limited as long as the region can be measured. Usually, it is about 1 to 10 mmφ and may have any shape.

【0016】また、薬液の供給口9と排出口10を分離
して設けているが、図2に示すように供給・排出口13
を用いてもよい。また、図3に示すように、必ずしも容
量測定プローブ内に設ける必要はなく、別系統に設置し
ても良い。
Although the supply port 9 and the discharge port 10 for the chemical solution are provided separately, as shown in FIG.
May be used. Further, as shown in FIG. 3, it is not always necessary to provide the probe in the capacitance measuring probe, and it may be provided in another system.

【0017】[0017]

【発明の効果】本発明によれば、環境の変化に因らず信
頼性の高いウエーハ状態の評価を行うことができる半導
体ウエーハの評価装置及び評価方法を提供することがで
きる。
According to the present invention, it is possible to provide a semiconductor wafer evaluation apparatus and an evaluation method capable of performing a highly reliable evaluation of a wafer state irrespective of environmental changes.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の半導体ウエーハの評価装置を示す図。FIG. 1 is a view showing an apparatus for evaluating a semiconductor wafer according to the present invention.

【図2】本発明の半導体ウエーハの評価装置を示す図。FIG. 2 is a view showing an apparatus for evaluating a semiconductor wafer according to the present invention.

【図3】本発明の半導体ウエーハの評価装置を示す図。FIG. 3 is a view showing an apparatus for evaluating a semiconductor wafer according to the present invention.

【図4】従来の半導体ウエーハの評価装置を示す図。FIG. 4 is a diagram showing a conventional semiconductor wafer evaluation apparatus.

【図5】従来の半導体ウエーハの評価時の等価回路を示
す図。
FIG. 5 is a diagram showing an equivalent circuit at the time of evaluation of a conventional semiconductor wafer.

【符号の説明】[Explanation of symbols]

1 ウエーハ 2 ステージ 3 測定位置調整モータ 4 容量測定プローブ 5、6 距離測定センサ 7 距離調整モータ 8 薬液 9 供給口 10 排出口 11 表面酸化膜 12 酸化膜を除去した領域 13 供給・排出口 Reference Signs List 1 wafer 2 stage 3 measuring position adjusting motor 4 capacity measuring probe 5, 6 distance measuring sensor 7 distance adjusting motor 8 chemical solution 9 supply port 10 discharge port 11 surface oxide film 12 area where oxide film is removed 13 supply / discharge port

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 半導体ウエーハの所定領域の表面酸化膜
を除去する手段と、前記表面酸化膜の除去された前記所
定領域に、DCバイアス電圧を印加し、その容量を測定す
る容量測定プローブとを具備することを特徴とする半導
体ウエーハの評価装置。
1. A means for removing a surface oxide film in a predetermined region of a semiconductor wafer, and a capacitance measuring probe for applying a DC bias voltage to the predetermined region where the surface oxide film has been removed and measuring a capacitance thereof. An apparatus for evaluating a semiconductor wafer, comprising:
【請求項2】 前記表面酸化膜を除去する手段は、半導
体ウエーハの所定領域に薬液を供給し、薬液により表面
酸化膜をエッチングする手段と、その廃液を排出する手
段とを備えることを特徴とする請求項1記載の半導体ウ
エーハの評価装置。
2. The method according to claim 1, wherein the means for removing the surface oxide film includes a means for supplying a chemical solution to a predetermined region of the semiconductor wafer, etching the surface oxide film with the chemical solution, and a means for discharging the waste liquid. 2. The apparatus for evaluating a semiconductor wafer according to claim 1, wherein:
【請求項3】 半導体ウエーハの所定領域の表面酸化膜
を除去した後、前記表面酸化膜の除去された前記所定領
域に、容量測定プローブにより、DCバイアス電圧を印加
して、その容量を測定することを特徴とする半導体ウエ
ーハの評価方法。
3. After removing a surface oxide film in a predetermined region of the semiconductor wafer, a DC bias voltage is applied to the predetermined region from which the surface oxide film has been removed by a capacitance measuring probe to measure the capacitance. A method for evaluating a semiconductor wafer, comprising:
JP2001094159A 2001-03-28 2001-03-28 System and method for evaluating semiconductor wafer Abandoned JP2002299397A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2001094159A JP2002299397A (en) 2001-03-28 2001-03-28 System and method for evaluating semiconductor wafer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2001094159A JP2002299397A (en) 2001-03-28 2001-03-28 System and method for evaluating semiconductor wafer

Publications (1)

Publication Number Publication Date
JP2002299397A true JP2002299397A (en) 2002-10-11

Family

ID=18948399

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2001094159A Abandoned JP2002299397A (en) 2001-03-28 2001-03-28 System and method for evaluating semiconductor wafer

Country Status (1)

Country Link
JP (1) JP2002299397A (en)

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