JP2002297566A - Passing circuit for vector gathering command - Google Patents

Abstract

PROBLEM TO BE SOLVED: To efficiently process memory access request with eliminating waste idle time in a generating circuit for memory access request. SOLUTION: In a passing circuit for vector gathering command, registers 400-403 form a command buffer. A decoder 500 judges an inputted command to be a vector gathering command, and a decoder 501 judges the inputted command to be a vector loading command. A judgment circuit 502 for issue of vector gathering command judges whether a situation for an issue of the gathering command is allowed or not. A generating circuit 503 for select signal judges whether a passing of the gathering command is allowed or not with referring to a variety of information flags 100-1 to 103-1, 200-1 to 203-1, 300-1 to 303-1 to generate a select signal 503-1 for selecting a command to send to the generating circuit for memory access request. A selector 504 sends a command corresponding to the signal 503-1 to the generating circuit for memory access request.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a vector gather instruction overtaking circuit, and more particularly to a vector gather instruction overtaking circuit in a vector processing apparatus having a scalar unit, a vector unit and a memory access request generating circuit.

[0002]

2. Description of the Related Art In recent years, CPUs (Central Pro
Although the processing capability of the processor unit has been remarkably improved as represented by an Intel chip, the same can be said for the CPU of the vector processing device. Since vector data cannot be stored in the cache in the CPU due to the amount of data, it is necessary to always access the memory, and the weight of the memory access performance is high. That is, in the vector processing device, CP
It is important to balance not only the U performance but also the transfer rate of data supplied to the CPU, and it is desired to efficiently transfer data between the CPU and the memory.

Conventionally, there have been proposed many techniques relating to overtaking of a vector store instruction (a wait time is required to supply data for writing to a main memory to a memory access request generation circuit).

[0004] For example, as such a prior art, there is an "instruction overtaking processing circuit" disclosed in Japanese Patent Laid-Open No. Hei 10-269199. This circuit compares the access area of the preceding main storage access instruction with the access area of the following main storage access instruction, and, if the two areas do not overlap, the main storage access instruction that precedes the preceding main storage access instruction. The storage access instruction is executed.

As another prior art, Japanese Patent Application Laid-Open No.
There is a “vector store overtaking control circuit” disclosed in Japanese Patent No. 231203. This circuit can accept a subsequent memory request without waiting for the result of an overtake check on memory access of a subsequent load instruction to a vector store instruction.

However, in the above two prior arts, in order for the succeeding instruction to overtake the vector store instruction, it is necessary to determine whether or not the access area of the main memory is duplicated. It took a lot of time and time to judge whether to pass.

On the other hand, as a prior art relating to overtaking of a vector load instruction, there is a "vector processing apparatus" disclosed in Japanese Patent No. 2741717. This apparatus stores vector load data in a vector register of a vector unit via a scalar unit, and calculates an address of a vector load instruction using an adder of the scalar unit. is there.

In the vector processing apparatus, a vector load instruction for indirect addressing, in other words, an instruction that can specify an arbitrary address for each element of vector data using the contents of a vector register as a load address (hereinafter referred to as a vector gather instruction). Instructions) are used.

Here, with reference to FIGS. 10 (a) and 10 (b), the difference in the processing path between a normal load instruction and a vector gather instruction will be described. FIG. 10A illustrates a processing path of a normal load instruction, and FIG. 10B illustrates a processing path of a vector gather instruction. A normal load instruction is
As shown in FIG. 10A, since the contents or immediate value of the scalar register is used as the address, an address can be generated in the scalar unit SU, and an instruction can be sent to the memory access request generation circuit MA therefrom. On the other hand, since the vector gather instruction uses the contents of the vector register as an address as shown in FIG. 10B, it is necessary to read the address from the vector register as data and send it to the memory access request generation circuit MA. It can be seen that extra time is spent here until the addresses are aligned in the memory access request generation circuit MA.

In view of this, a vector processing apparatus capable of succeeding a vector gather instruction, which is a vector load instruction of indirect addressing, by a subsequent load instruction is desired. However, the vector processing apparatus disclosed in the above-mentioned Japanese Patent No. 2741717 does not. could not. This is because the address of the vector gather instruction is a random address for each element and is stored in the vector register, and thus cannot be obtained using the adder of the scalar unit SU.

[0011]

In the above-described conventional vector processing apparatus, memory access processing is performed at high speed, and C
There has been a problem that data transfer between the PU and the memory cannot be performed efficiently. The reason is that the subsequent load instruction cannot overtake the vector gather instruction which is the vector load instruction of the indirect addressing.

It is an object of the present invention to provide a vector gather instruction overtaking circuit in which a preceding load instruction can overtake a preceding vector gather instruction.

Another object of the present invention is to provide a vector processing apparatus having a vector gather instruction overtaking circuit in which a preceding load instruction can overtake a preceding vector gather instruction.

[0014]

A vector gather instruction overtaking circuit according to the present invention receives an instruction from a scalar unit, inputs a vector gather instruction issuance permission from a vector unit, and outputs the vector gather instruction when the vector gather instruction is input. If there is no instruction issue permission for the gather instruction, the vector gather instruction is held, and if the load instruction is input and the vector gather instruction preceding the load instruction is held, the vector gather instruction preceding the load instruction is held. The overwriting is issued to the memory access request generation circuit.

According to another aspect of the present invention, there is provided a vector processing apparatus including a scalar unit, a vector unit, and a memory access request generating circuit, wherein the vector gather instruction and the address of the vector gather instruction are aligned in the vector unit. An instruction buffer for waiting for subsequent instructions, and valid / invalid instructions stored in each stage of the instruction buffer.
A first flip-flop group that holds an instruction valid flag indicating invalidity, a first decoder that determines whether an instruction input from the scalar unit is a vector gather instruction, and an output signal of the first decoder A second flip-flop group that holds a vector gather instruction flag indicating whether the instruction stored in each stage of the instruction buffer is a vector gather instruction, and a load instruction that is an instruction input from the scalar unit. And a load instruction flag indicating whether an instruction stored in each stage of the instruction buffer is a load instruction based on an output signal of the second decoder. Counting a third flip-flop group and a vector gather instruction issuance permission from the vector unit; A vector gather instruction issuance determination circuit for determining whether the vector gather instruction issuable or not stored in the instruction buffer is issued, an output signal of the vector gather instruction issuance determination circuit, the instruction valid flag, the vector gather instruction flag, and the load instruction Determining whether or not a preceding load instruction can be overtaken by a subsequent load instruction based on a flag, and selecting an instruction to be sent to the memory access request generation circuit from the input instruction and the instruction stored in the instruction buffer; A select signal generating circuit for generating a select signal, and selecting an instruction to be transmitted to the memory access request generating circuit from an instruction input based on the select signal from the select signal generating circuit and an instruction stored in the instruction buffer. Selector and Characterized in that it has.

Further, the vector gather instruction passing circuit of the present invention is a vector processing apparatus comprising a scalar unit, a vector unit, and a memory access request generation circuit, wherein the vector gather instruction and the address of the vector gather instruction are aligned in the vector unit. An instruction buffer for waiting for subsequent instructions, and valid / invalid instructions stored in each stage of the instruction buffer.
A first flip-flop group that holds an instruction valid flag indicating invalidity, a first decoder that determines whether an instruction input from the scalar unit is a vector gather instruction, and an output signal of the first decoder A second flip-flop group that holds a vector gather instruction flag indicating whether the instruction stored in each stage of the instruction buffer is a vector gather instruction, and a load instruction that is an instruction input from the scalar unit. And a load instruction flag indicating whether an instruction stored in each stage of the instruction buffer is a load instruction based on an output signal of the second decoder. Counting a third flip-flop group and a vector gather instruction issuance permission from the vector unit; A vector gather instruction issuance determination circuit for determining whether or not the vector gather instruction stored in the instruction buffer can be issued; an output signal of the vector gather instruction issuance determination circuit; the instruction valid flag; the vector gather instruction flag; It is determined whether or not the preceding vector gather instruction can be overtaken by the subsequent load instruction based on the output signal of the decoder and the load instruction flag, and the memory access request generation is performed from the input instruction and the instruction stored in the instruction buffer. A select signal generation circuit for generating a select signal for selecting an instruction to be sent to the circuit; and a memory access from an instruction input based on a select signal from the select signal generation circuit and an instruction stored in the instruction buffer. Send to request generation circuit And having a selector for selecting an instruction to be.

Further, in the vector gather instruction overtaking circuit of the present invention, the instruction buffer comprises a plurality of stages of registers.

In the vector gather instruction overtaking circuit according to the present invention, the instruction buffer is a RAM.

On the other hand, a vector processing apparatus according to the present invention comprises a scalar unit for outputting an instruction, a vector unit for inputting an instruction from the scalar unit and outputting a vector gather instruction issuance permission and an address, and an When a vector gather instruction is issued from the vector unit and the instruction is not issued for the vector gather instruction when the vector gather instruction is input, the vector gather instruction is held and the load instruction is input. A vector gather instruction overtaking circuit that issues the load instruction overtaking the preceding vector gather instruction if the vector gather instruction preceding the load instruction is held;
A memory access request generating circuit for generating a memory access request by inputting an instruction from the vector gather instruction overtaking circuit and inputting an address of the vector gather instruction from the vector unit.

[0020]

Embodiments of the present invention will be described below in detail with reference to the drawings.

(1) First Embodiment FIG. 2 shows a method for eliminating a useless waiting time of a subsequent load instruction when there is a load instruction following a vector gather instruction which waits for the alignment of addresses. FIG. 10 is a block diagram illustrating an arrangement relationship in a vector processing device when a vector gather instruction overtaking circuit VG is provided.
In a normal load instruction, the start address of vector data and the distance between data (distance between elements) are obtained from the scalar unit SU, and the address of each element is created by the memory access request generation circuit MA from these. On the other hand, the vector gather instruction has a random address for each element and is stored in a vector register in the vector unit VU.
Enter the address from. Also, the vector unit VU
Input the permission to issue a vector gather instruction to the vector gather instruction passing circuit VG.

Referring to FIG. 3A, the format of a vector load instruction (excluding a vector gather instruction), which is an example of a normal load instruction, includes an instruction code OP, a vector register number X for writing data, and a It is composed of a scalar register number Y storing the distance and a scalar register number Z storing the address of the head element of the vector data.

Referring to FIG. 3B, the format of the vector gather instruction comprises an instruction code OP, a vector register number X for writing data, and a vector register number Y in which the address of the vector data is stored. ing.

When there is a preceding vector gather instruction and a subsequent load instruction, since the program has been compiled in advance by the compiler, register duplication between the preceding vector gather instruction and the subsequent load instruction is performed. Use has been excluded in advance. Therefore, when the succeeding load instruction overtakes the preceding vector gather instruction, it is not necessary to check the register to be used.

FIG. 1 is a circuit block diagram showing a configuration of a vector gather instruction overtaking circuit according to the first embodiment of the present invention. The vector gather instruction overtaking circuit according to the present embodiment requires registers 400 to 403 (4 words in this example) forming an instruction buffer for waiting until the address of the vector gather instruction is aligned, and is necessary for overtaking the vector gather instruction. Flip-flops (hereinafter abbreviated as FFs) 100 to 103, 200 to 203, and 300 to
303, a decoder 500 for determining that the input instruction is a vector gather instruction, and a decoder 50 for determining that the input instruction is a vector load instruction
1; a vector gather instruction issuance determination circuit 502 for determining whether the vector gather instruction can be issued; and a select signal 503 for determining whether to pass the vector gather instruction and selecting an instruction to be sent to the memory access request generation circuit MA. A select signal generation circuit 503 for generating -1 and an instruction to be transmitted to the memory access request generation circuit MA from instructions input based on the select signal from the select signal generation circuit 503 and instructions stored in the instruction buffer are selected. Selector 5 for selecting an instruction to be sent to memory access request generation circuit MA
04.

The FFs 100 to 103 correspond to the instruction valid flags 100-1 to 103 corresponding to the register 403 as the word 3 from the register 400 as the word 0 in the instruction buffer.
Holds -1. For example, when the instruction valid flag 100-1 held by the FF 100 is “1”, the instruction in the corresponding register 400 is regarded as valid. FF100-103,
An instruction valid flag corresponding to the registers 400 to 403, that is, a flag indicating in which word (registers 400 to 403) a valid instruction exists. Instruction 000-
When 1 is valid and an instruction cannot be sent to the memory access request generation circuit MA for some reason, an instruction is temporarily stored in an instruction buffer including the registers 400 to 403. There are three causes for this. The first is that if instruction 000-1 is a vector gather instruction, the second is that the instruction preceding input 000-1 is stored in an instruction buffer consisting of registers 400 to 403. If there,
The third is a case where the preceding instruction does not exist in the instruction buffer including the registers 400 to 403, but the memory access request generation circuit MA cannot accept the instruction. In these cases, the instruction 000-1 is It is temporarily stored in an instruction buffer including registers 400 to 403.

Next, instructions are stored in the instruction buffer consisting of the registers 400 to 403 in the same manner as in a normal FIFO buffer. The first instruction is stored in the register 400, and the next instruction is stored in the register 401. The next instruction is in register 402 and the next instruction is in register 403.
Are stored in order. When the instruction of the register 400 is sent to the memory access request generation circuit MA, the instruction of the register 401 is stored in the register 400,
The second instruction is moved to the register 401 and the instruction of the register 403 is moved to the register 402 in order. However, only the overtaking timing of the vector gather instruction changes the order of the instructions. In response to the movement of these instructions,
Instruction valid flags 100-1 to 100-3
3-1 and the like are also controlled.

The FFs 200 to 203 include registers 400 to
403 holds vector gather instruction flags 200-1 to 203-1 indicating whether the instructions stored in the registers 400 to 403 are vector gather instructions.

The selectors 210 to 212 are connected to the FF 200 to
Vector gather instruction flag 200-
This is a circuit for selectively switching between Nos. 1 and 202-1. The output signal 500-1 of the decoder 500 or the vector gather instruction flags 201-1 to 203- of the preceding stage according to the instruction valid flags 101-1 to 103-1. 1 to FF2
Output to 00-202.

The FFs 300 to 303 are registers 400 to
A load instruction flag 300 corresponding to 403 and indicating whether the instruction stored in the registers 400 to 403 is a load instruction or not.
-1 to 303-1 are held.

The selectors 310 to 312 are connected to the FFs 300 to
Load instruction flags 300-1 to 302 held in 302
-1 is a circuit for selectively switching -1 and the decoder 501 according to the instruction valid flags 101-1 to 103-1.
Output signal 501-1 or the preceding stage load instruction flag 3
01-1 to 303-1 are output to the FFs 300 to 302.

Registers 400 to 403 are registers for holding instructions, and correspond to words 0 to 3.

The selectors 410 to 412 are connected to the register 40
This is a circuit for selectively switching the instructions held in 0 to 402, and is stored in the instruction code 000-1 input according to the instruction valid flags 101-1 to 103-1 or the registers 401 to 403 in the preceding stage. The instruction is output to registers 400 to 402 at the subsequent stage.

The decoder 500 determines whether or not the instruction 000-1 input from the scalar unit SU is a vector gather instruction.
An output signal 500-1 which becomes "1" when 1 is a vector gather instruction is output.

The decoder 501 is a decoder for determining whether or not the instruction 000-1 input from the scalar unit SU is a load instruction. The output signal 501 becomes "1" when the instruction 000-1 is a load instruction. Outputs -1.

Vector gather instruction issue determination circuit 502
Is a circuit that determines whether or not the value of a counter that counts up when the address of the vector gather instruction is aligned with the memory access request generating circuit MA (hereinafter, referred to as a vector gather instruction issuable number counter) is “0”. . When the output signal 502-1 of the vector gather instruction issuance determination circuit 502 is "0", it is determined that the head vector gather instruction can be issued. Only the vector unit VU can control the permission to issue the vector gather instruction. The vector gather instruction detects the condition of whether the data of the vector register used as the address is determined, and starts the processing of the vector gather instruction. Determine if you can. When an instruction preceding a vector gather instruction attempts to update a vector register used as an address by a subsequent vector gather instruction, it must wait for the preceding instruction to finish. As described above, it is determined whether or not the data of the vector register used by the vector gather instruction is determined in the vector unit VU, and is sent to the vector gather instruction issuance determination circuit 502 in a form of permitting the issuance. The instruction issue permission counter is counted up. When the vector gather instruction is sent to the memory access request generation circuit MA, the value of the vector gather instruction issuance permitted counter is counted down by one. As a result, when there is no vector gather instruction awaiting execution, the vector gather instruction issuance permitted number counter in the vector gather instruction issuance determination circuit 502 is "0".

The select signal generation circuit 503 is connected to the FF 10
Instruction valid flags 100-1 to 103-1, 0 to 103
Vector gather instruction flag 20 of FFs 200 to 203
0-1 to 203-1, the load instruction flags 300-1 to 303-1 of the FFs 300 to 303, and the output signal 502-1 of the vector gather instruction issuance determination circuit 502 from the instruction buffer or the vector gather instruction composed of registers 400 to 403. Instruction 000 input to the overtaking circuit
Select signal 503 for selecting any one of
1 is a circuit for generating the “1.

The selector 504, based on the select signal 503-1 from the select signal generation circuit 503, converts the instruction 000-1 input from the scalar unit SU and the instruction stored in the instruction buffer consisting of the registers 400 to 403 into a memory. This is a circuit for selecting an instruction to be sent to the access request generation circuit MA.

FIG. 4 is a table showing the logic of the select signal generation circuit 503. This table stores the output signals 502-1 and 502-1 of the vector gather instruction issuance determination circuit 502.
Instruction valid flags 100-1 to 100-3
3-1, vector gather instruction flags 200-1 to 203-1 of FFs 200 to 203, and FFs 300 to 30
3, the instruction to be sent to the memory access request generation circuit MA is determined using the values of the load instruction flags 300-1 to 303-1. If an instruction other than the vector gather instruction exists between the vector gather instruction and the subsequent load instruction, it indicates that no overtaking is performed, but two or three consecutive vector gather instructions are performed. In this case, the subsequent load instruction also indicates that the two or three vector gather instructions can pass in one machine cycle.

FIG. 5 is a diagram showing a time chart when the vector load instruction of the register 401 overtakes the vector gather instruction of the register 400 in comparison with a similar case according to the prior art.

FIG. 6 is a diagram showing a time chart when the vector load instruction of the register 402 overtakes the vector gather instruction of the registers 400 and 401 in comparison with a similar case according to the prior art.

FIG. 7 is a diagram showing a time chart when the vector load instruction of the register 403 overtakes the vector gather instruction of the registers 400, 401 and 402 in comparison with a similar case according to the prior art.

Next, the operation of the vector gather instruction overtaking circuit according to the first embodiment thus configured will be described with reference to FIGS.

First, the operation when there is no instruction in the instruction buffer including the registers 400 to 403 will be described.

When there is no other instruction in the instruction buffer including the registers 400 to 403, instructions other than the vector gather instruction do not need to wait until the addresses are aligned.
The input instruction 000-1 is stored in registers 400 to 403.
Through the selector 504 without being stored in the memory access request generation circuit MA.

Next, the operation when an instruction other than the vector gather instruction is present in the instruction buffer including the registers 400 to 403 will be described.

When at least one instruction other than the vector gather instruction exists in the instruction buffer including the registers 400 to 403, the instruction buffer including the registers 400 to 403 operates in the same manner as a normal FIFO buffer. 000-1 is written to the next word of the preceding last instruction, and is moved to the preceding word every time the preceding instruction is sent to the memory access request generation circuit MA. At this time, the instruction valid flags 100-1 to 103-1 of the FFs 100 to 103, the vector gather instruction flags 200-1 to 203-1 of the FFs 200 to 203, and the load instruction flags 300-1 to 300-1 of the FFs 300 to 303.
303-1 is also moved in synchronization with the instruction.

For example, if there is an instruction preceding registers 400 and 401, input instruction 000-1
Are stored in the register 402, and at the timing when the instruction of the register 400 is sent to the memory access request generation circuit MA, the instruction of the register 401 is
The instruction in register 402 is moved to register 401. At the timing when the instruction of the register 400 is sent to the memory access request generation circuit MA, the register 40
One instruction is moved to register 400. Register 40
When the instruction of 0 is sent to the memory access request generation circuit MA, the instruction buffer including the registers 400 to 403 becomes empty and enters a standby state until the next instruction 000-1 is input.

Next, the overtaking operation of the vector gather instruction will be described.

Even if a vector gather instruction exists in the instruction buffer consisting of the registers 400 to 403, until the vector gather instruction is stored in the register 400,
Since the same operation as that of the above-mentioned ordinary FIFO buffer is performed, the description is omitted.

In the vector gather instruction overtaking circuit according to the first embodiment, there are three patterns for overtaking the vector gather instruction. Hereinafter, three patterns in which a vector load instruction (excluding the vector gather instruction), which is an example of the load instruction, overtakes the vector gather instruction will be described.

FIG. 5 shows a first overtaking pattern. FIG. 5A is a time chart when passing is performed according to the present invention, and FIG. 5B is a time chart according to the related art.

In FIG. 5A, the vector gather instruction VGT0 is already stored in the register 400 in the machine cycle 0.
Exists, and the vector load instruction VLD0 is stored in the register 401 in the machine cycle 1. Then, the instruction valid flags 100-1 and 101-1 become "1" and "1", and the vector gather instruction flag 20
0-1 and 201-1 are "1" and "0", and the load instruction flags 300-1 and 301-1 are "0" and "1". At this time, assuming that the vector gather instruction VGT0 cannot be issued yet, the output signal 502-1 of the vector gather instruction issuance determination circuit 502 is output because the value of the vector gather instruction issuance permitted counter is "0". It becomes “1”. Therefore, the select signal generation circuit 503 outputs a select signal 503-1 for selecting the output of the register 401 to the selector 504 (see FIG. 4). The selector 504 selects the vector load instruction VLD0 stored in the register 401 and sends it to the memory access request generation circuit MA.

When it becomes possible to issue the vector gather instruction VGT0 and the value of the vector gather instruction issuable number counter becomes "1" in machine cycle 4,
Output signal 5 of vector gather instruction issue determination circuit 502
02-1 is "0". Therefore, the select signal generation circuit 503 outputs a select signal 503-1 for selecting the output of the register 400 to the selector 504 (see FIG. 4). The selector 504 selects the vector gather instruction VGT0 stored in the register 400 and sends it to the memory access request generation circuit MA.

When comparing FIG. 5A and FIG. 5B, the time chart in the case where the overtaking according to the present invention is performed is larger than the time chart according to the prior art in that the vector load instruction VLD0 has a memory access request. The timing of transmission to the generation circuit MA is earlier by four machine cycles. This difference spreads as the timing at which the issue of the vector gather instruction becomes possible becomes later.

FIG. 6 shows a second overtaking pattern. FIG. 6A is a time chart when passing is performed according to the present invention, and FIG. 6B is a time chart according to a conventional technique.

In FIG. 6A, vector gather instructions VGT0 and VGT1 already exist in registers 400 and 401 respectively in machine cycle 0, and vector load instruction VGT in register 402 in machine cycle 1.
It is assumed that LD0 is stored. Then, the instruction valid flags 100-1, 101-1 and 102-1 become "1",
“1” and “1”, vector gather instruction flag 20
0-1, 201-1 and 202-1 are "1", "1"
And "0", the load instruction flags 300-1, 301-
1 and 302-1 become "0", "0" and "1". At this point, the vector gather instruction VGT0 is still
Assuming that VGT1 and VGT1 cannot be issued, the output signal 502-1 of the vector gather instruction issue determination circuit 502 becomes "1" because the value of the vector gather instruction issue permitted number counter is "0". Therefore, the select signal generation circuit 503 outputs a select signal 503-1 for selecting the output of the register 402 to the selector 504 (see FIG. 4). The selector 504 selects the vector load instruction VLD0 stored in the register 402,
It is sent to the memory access request generation circuit MA.

When it becomes possible to issue the vector gather instruction VGT0 and the value of the vector gather instruction issuable number counter becomes "1" in machine cycle 4,
Output signal 5 of vector gather instruction issue determination circuit 502
02-1 is "0". Therefore, the select signal generation circuit 503 outputs a select signal 503-1 for selecting the output of the register 400 to the selector 504 (see FIG. 4). The selector 504 selects the vector gather instruction VGT0 stored in the register 400 and sends it to the memory access request generation circuit MA. At this time, the vector gather instruction VGT1 stored in the register 401 is moved to the register 400, and the value of the vector gather instruction issuance permitted number counter is counted down to “0”.

When it becomes possible to issue the vector gather instruction VGT 1 and the value of the vector gather instruction issue number counter becomes “1” in machine cycle 9,
Output signal 5 of vector gather instruction issue determination circuit 502
02-1 is "0". Therefore, the select signal generation circuit 503 outputs a select signal 503-1 for selecting the output of the register 400 to the selector 504 (see FIG. 4). The selector 504 selects the vector gather instruction VGT1 stored in the register 400 and sends it to the memory access request generation circuit MA. At this time, the value of the vector gather instruction issue permitted number counter is counted down to “0”.

Compared with FIGS. 6A and 6B, the time chart in the case where the overtaking is performed according to the present invention is different from the time chart according to the conventional technique in that the vector load instruction VLD0 generates the memory access request. The timing of sending to the circuit MA is 9 machine cycles earlier. This difference spreads as the timing at which the issue of the vector gather instruction becomes possible becomes later.

FIG. 7 shows a third overtaking pattern. FIG. 7A is a time chart when passing is performed according to the present invention, and FIG. 7B is a time chart according to a conventional technique.

In FIG. 7A, in machine cycle 0, vector gather instructions VGT0, VGT1 and VG are already stored in registers 400, 401 and 402, respectively.
It is assumed that T2 exists and the vector load instruction VLD0 is stored in the register 403 in the machine cycle 1. Then, the instruction valid flags 100-1, 101-1, and 102
-1 and 103-1 are "1", "1", "1" and "1", and the vector gather instruction flags 200-1, 20
1-1, 202-1 and 203-1 are "1",
“1”, “1” and “0”, load instruction flag 300
-1, 301-1, 302-1 and 303-1 become "0", "0", "0" and "1". At this point, assuming that the vector gather instructions VGT0, VGT1 and VGT2 cannot be issued yet, since the value of the vector gather instruction issuance permitted counter is "0", the output signal 502-of the vector gather instruction issuance determination circuit 502 is determined. 1 becomes “1”. Therefore, the select signal generation circuit 503 outputs a select signal 503-1 for selecting the output of the register 403 to the selector 504 (see FIG. 4). The selector 504 selects the vector load instruction VLD0 stored in the register 403,
It is sent to the memory access request generation circuit MA.

When it becomes possible to issue the vector gather instruction VGT 0 and the value of the vector gather instruction issue permitted number counter becomes “1” in machine cycle 4,
Output signal 5 of vector gather instruction issue determination circuit 502
02-1 is "0". Therefore, the select signal generation circuit 503 outputs a select signal 503-1 for selecting the output of the register 400 to the selector 504. The selector 504 selects the vector gather instruction VGT0 stored in the register 400 and sends it to the memory access request generation circuit MA (see FIG. 4). At this time,
The vector gather instruction VGT1 stored in the register 401 is stored in the register 400, and the vector gather instruction VGT2 stored in the register 402 is stored in the register 40.
The number is moved to 1, and the value of the vector gather instruction issue permitted number counter is counted down to “0”.

When it becomes possible to issue the vector gather instruction VGT 1 and the value of the vector gather instruction issuable number counter becomes “1” in machine cycle 9,
Output signal 5 of vector gather instruction issue determination circuit 502
02-1 is "0". Therefore, the select signal generation circuit 503 outputs a select signal 503-1 for selecting the output of the register 400 to the selector 504. The selector 504 selects the vector gather instruction VGT1 stored in the register 400 and sends it to the memory access request generation circuit MA (see FIG. 4). At this time,
The vector gather instruction VGT2 stored in the register 401 is moved to the register 400, and the value of the vector gather instruction issuable number counter is counted down to “0”.

When it becomes possible to issue the vector gather instruction VGT2 and the value of the vector gather instruction issuance permitted counter becomes "1" in the machine cycle 15, the output signal 502-1 of the vector gather instruction issuance determination circuit 502 becomes It becomes “0”. Therefore, the select signal generation circuit 503 outputs a select signal 503-1 for selecting the output of the register 400 to the selector 504. The selector 504 selects the vector gather instruction VGT2 stored in the register 400 and sends it to the memory access request generation circuit MA. At this time, the value of the vector gather instruction issue permitted number counter is counted down to “0”.

When comparing FIG. 7A and FIG. 7B, the time chart in the case where the overtaking according to the present invention is performed is larger than the time chart according to the prior art in that the vector load instruction VLD0 has a memory access request. The timing of sending to the generation circuit MA is earlier by 14 machine cycles. This difference spreads as the timing at which the issue of the vector gather instruction becomes possible becomes later.

(2) Second Embodiment In the vector gather instruction overtaking circuit according to the first embodiment, a load instruction following a preceding vector gather instruction is always stored in an instruction buffer including registers 401 to 403. Although passing is performed after storing once, the selector 504 is not stored in the instruction buffer.
Memory access request generation circuit MA
Can also be sent to

FIG. 8 is a circuit block diagram showing the configuration of the vector gather instruction passing circuit according to the second embodiment of the present invention. The vector gather instruction overtaking circuit according to this embodiment is the first gathering circuit shown in FIG.
The difference is that the output signal 501-1 of the decoder 501 is directly input to the select signal generation circuit 503 with respect to the vector gather instruction overtaking circuit according to the embodiment. Therefore, the other parts are denoted by the same reference numerals and detailed description is omitted.

FIG. 9 is a table showing the logic of the select signal generation circuit 503 in the vector gather instruction overtaking circuit according to the second embodiment. This table corresponds to the select signal generation circuit 5 in the vector gather instruction overtaking circuit according to the first embodiment shown in FIG.
The difference is that the output signal 501-1 of the decoder 501 is added to the table representing the logic of 03 as one element of the judgment.

In the vector gather instruction overtaking circuit according to the second embodiment configured as described above, the output signal 501-1 of the decoder 501 is output to the select signal generation circuit 5
By directly inputting the data to the instruction 03, the select signal generation circuit 503 can immediately determine whether the input instruction 000-1 is a load instruction. The select signal generation circuit 503 can determine from which vector gather instruction flag exists the vector gather instruction flags 200-1 to 203-1 of the FFs 200 to 203. It can also be determined from the output signal 502-1 whether issuance of the vector gather instruction has been permitted. Therefore, if the instruction 000-1 is a load instruction and can overtake the preceding vector gather instruction, the selector 504 sets the instruction 000
By controlling to select “−1”, it is possible to directly input the subsequent load instruction to the sector 504 without storing it in the instruction buffer, and to transmit it to the memory access request generation circuit MA.

In the above embodiments, the instruction buffer has four words. However, the number of words in the instruction buffer can be set arbitrarily.

In the above embodiments, the instruction buffer is constituted by the registers 400 to 403.
RAM (Random Access Memory)
It is also possible to configure with. The RAM referred to here is a storage circuit used for a cache or the like in a general CPU, and its capacity does not need to be so large. It is sufficient if the width is equal to the instruction and the word is several words.

[0073]

The first effect is that with a small amount of hardware,
It is possible to efficiently process a memory access request. The reason is that when the vector gather instruction cannot be sent to the memory access request generation circuit, the subsequent load instruction is sent to the memory access request generation circuit prior to the vector gather instruction, so that the memory access request generation circuit is wasted. This is because idle time can be eliminated.

The second effect is that since the subsequent load instruction overtakes the vector gather instruction, there is no need to check the memory access area, the amount of hardware is small, and the time for determining whether or not overtaking is possible is short. The reason is that because the program has been pre-compiled by the compiler, there is no need to check for duplicate register usage between the preceding vector gather instruction and the subsequent load instruction.

[Brief description of the drawings]

FIG. 1 is a circuit block diagram showing a configuration of a vector gather instruction overtaking circuit according to a first embodiment of the present invention.

FIG. 2 is a block diagram illustrating an arrangement relationship of a vector gather instruction overtaking circuit according to the present invention.

3A is a diagram illustrating a format of a vector load instruction, and FIG. 3B is a diagram illustrating a format of a vector gather instruction.

FIG. 4 is a table showing logic of a select signal generation circuit in FIG. 1;

FIG. 5A is a time chart in a case where a vector load instruction overtakes a vector gather instruction, and FIG. 5B is a time chart in a similar case according to a conventional technique.

6A is a time chart when a vector load instruction overtakes two vector gather instructions, and FIG.
Is a time chart in a similar case according to the prior art.

7A is a time chart when a vector load instruction overtakes three vector gather instructions, and FIG.
Is a time chart in a similar case according to the prior art.

FIG. 8 is a circuit block diagram illustrating a configuration of a vector gather instruction overtaking circuit according to a second embodiment of the present invention.

FIG. 9 is a table showing logic of a select signal generation circuit in FIG. 8;

FIG. 10A shows a processing path of a normal load instruction,
FIG. 2B is a block diagram illustrating a processing path of a conventional vector gather instruction.

[Explanation of symbols]

 100 to 103 flip-flops 100-1 to 103-1 instruction valid flags 200 to 203 flip-flops 200-1 to 203-1 vector gather instruction flags 210 to 212 selectors 300 to 303 flip-flops 300-1 to 303-1 load instruction flags 310 to 312 selector 400 to 403 register 410 to 413 selector 500 decoder 500-1 output signal 501 decoder 501-1 output signal 502 vector gather instruction issue determination circuit 502-1 output signal 503 select signal generation circuit 503-1 select signal 504 selector MA Memory access request generation circuit SU Scalar unit VG Vector gather instruction overtaking circuit VU vector unit

Claims (6)

[Claims] An instruction is input from a scalar unit and a permission to issue a vector gather instruction is input from a vector unit. If the instruction to issue a vector gather instruction is not granted when the vector gather instruction is input, the vector gather instruction is issued. When the load instruction is input, if the vector gather instruction preceding the load instruction is held, the load instruction is issued to the memory access request generation circuit overtaking the preceding vector gather instruction. Characteristic vector gather instruction overtaking circuit. 2. A vector processing apparatus comprising a scalar unit, a vector unit, and a memory access request generation circuit, comprising: an instruction buffer for waiting the vector gather instruction and a subsequent instruction until the vector gather instruction addresses are aligned in the vector unit. The validity of the instruction stored in each stage of the instruction buffer /
A first flip-flop group that holds an instruction valid flag indicating invalidity, a first decoder that determines whether an instruction input from the scalar unit is a vector gather instruction, and an output signal of the first decoder A second flip-flop group that holds a vector gather instruction flag indicating whether the instruction stored in each stage of the instruction buffer is a vector gather instruction, and a load instruction that is an instruction input from the scalar unit. And a load instruction flag indicating whether an instruction stored in each stage of the instruction buffer is a load instruction based on an output signal of the second decoder. Counting a third flip-flop group and a vector gather instruction issuance permission from the vector unit; A vector gather instruction issuance determination circuit for determining whether the vector gather instruction issuable or not stored in the instruction buffer is issued, an output signal of the vector gather instruction issuance determination circuit, the instruction valid flag, the vector gather instruction flag, and the load instruction Determining whether or not a preceding load instruction can be overtaken by a subsequent load instruction based on a flag, and selecting an instruction to be sent to the memory access request generation circuit from the input instruction and the instruction stored in the instruction buffer; A select signal generating circuit for generating a select signal, and selecting an instruction to be transmitted to the memory access request generating circuit from an instruction input based on the select signal from the select signal generating circuit and an instruction stored in the instruction buffer. Selector and Vector gather instruction overtaking circuit, characterized in that it comprises. 3. A vector processing apparatus comprising a scalar unit, a vector unit, and a memory access request generation circuit, comprising: an instruction buffer for waiting the vector gather instruction and a subsequent instruction until addresses of the vector gather instruction are aligned in the vector unit. The validity of the instruction stored in each stage of the instruction buffer /
A first flip-flop group that holds an instruction valid flag indicating invalidity, a first decoder that determines whether an instruction input from the scalar unit is a vector gather instruction, and an output signal of the first decoder A second group of flip-flops that hold a vector gather instruction flag indicating whether the instruction stored in each stage of the instruction buffer is a vector gather instruction, and a load instruction that is input from the scalar unit. And a load instruction flag indicating whether an instruction stored in each stage of the instruction buffer is a load instruction based on an output signal of the second decoder. Counting the permission of issuing a vector gather instruction from the third flip-flop group and the vector unit; A vector gather instruction issuance determination circuit for determining whether or not the vector gather instruction stored in the instruction buffer can be issued; an output signal of the vector gather instruction issuance determination circuit; the instruction valid flag; the vector gather instruction flag; It is determined whether or not the preceding vector gather instruction can be overtaken by the subsequent load instruction based on the output signal of the decoder and the load instruction flag. A select signal generation circuit for generating a select signal for selecting an instruction to be sent to the circuit; and a memory access from an instruction input based on a select signal from the select signal generation circuit and an instruction stored in the instruction buffer. Send to request generation circuit Vector gather instruction overtaking circuit, characterized in that a selector for selecting an instruction to be. 4. The vector gather instruction overtaking circuit according to claim 2, wherein the instruction buffer comprises a plurality of stages of registers. 5. The vector gather instruction passing circuit according to claim 2, wherein the instruction buffer is a RAM. 6. A scalar unit for outputting an instruction, a vector unit for receiving an instruction from the scalar unit and outputting a vector gather instruction issuance permission and an address, and receiving an instruction from the scalar unit and receiving a vector from the vector unit. A gather instruction issuance permission is input, and if there is no instruction issue permission for the vector gather instruction when the vector gather instruction is input, the vector gather instruction is held, and when the load instruction is input, the load instruction precedes the load instruction. If a vector gather instruction is held, a vector gather instruction overtaking circuit that issues the load instruction overtaking a preceding vector gather instruction, an instruction is input from the vector gather instruction overtaking circuit, and the vector gather is issued from the vector unit. And a memory access request generation circuit for generating a memory access request by inputting an address of a user instruction.