JP2002297441A - Memory access device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a memory access device that can modify the capability of a bus driver according to the setting of the access speed and the number of wait for a memory and halts unnecessary bus signal output at the instant of access termination for realizing optimal power consumption. SOLUTION: In the memory access device, as its constitution, a wait control part 101, output drivers 120 to 135 and an output driver control part 102 are provided, and the output drivers 120 to 135 are individually controlled by output driver control signals 150 to 153 from the output driver control part 102.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory access device, and more particularly to a bus signal output time in reading from or writing to a memory, the capability of a driver for outputting a bus signal, and occupation of a bus to be used. The present invention relates to a memory access device that individually varies time.

[0002]

2. Description of the Related Art Conventionally, when reading data from or writing data to a memory, the output driver of a bus signal connected to the memory has a constant capability. A configuration has been adopted in which the output time of a bus signal (address signal in the following example) to be connected is variably controlled.

FIG. 14 is a block diagram showing a configuration of a conventional memory access device. In FIG. 14, 140
Reference numeral 3 denotes a memory. The memory access device 1400 includes a weight control unit 1401, an output driver control unit 1402,
An output driver 1404, and a weight controller 14
Address outputs 1410 to 1413 output from 01 indicate each bit of the address, and are input to output drivers 1420 to 1423 of the output driver unit 1404. The output driver unit 1404 stores the output driver control signal 1450 output from the output driver control unit 1402 in the memory 140.
3, the output period of the driver output addresses 1440 to 1443 is controlled.

[0004] The operation of the conventional memory access device configured as described above will be described with reference to FIG. The weight control unit 1401 and the output driver control unit 1402 control the time to output the addresses 1410 to 1413 as the number of waits according to the access time required by the memory 1403. The output drivers 1420 to 1423 of the output driver unit 1404 have addresses 1410 to 1410, respectively.
1413, and outputs driver output addresses 1440 to 1443 under the control of an output driver control signal 1450. The number of waits is determined by how many times the basic access time is repeated, and the output time to the bus is adjusted by arbitrarily setting the number of accesses (not shown). The number of waits is determined by the access speed of the connected memory 1403, but the output capability of the output drivers 1420 to 1423 is constant even if the number of waits changes.

FIG. 15 is an operation timing chart of the conventional memory access device. In FIG. 15, time t1 to t9
Are the basic times of the minimum unit of access, and if an access time longer than the basic time is required, the time t1
The memory access is executed using a plurality of subsequent cycles in succession. In the example of FIG. 15, access to the memory 1403 requires time t1 to t6 depending on the access speed. Time t0 indicates the initial state. From the memory access device 1400 to the driver output address 1440-1
443, the address 1410 (address 1
411 to 1413 are not shown) from time t1 to time t6.
Output up to Similarly, an output driver control signal 1450 for controlling the outputs of the output drivers 1420 to 1423 is output from time t1 to time t6. Output driver 1420
Is the address 1410 and the output driver control signal 145
In response to the input of 0, driver output address 1440 is output between time t1 and time t6. Address 1
410, the output driver control signal 1450 can be set at any time, but since it is not configured to be set independently, the address 1410 and the output driver control signal 14
The output of 50 and the driver output address 1440 have the same output period (between time t1 and time t6 in this example).

As described above, in the conventional memory access device, the number of waits can be arbitrarily set in accordance with the access speed of the memory, but the output capability to the bus cannot be changed. There has been a problem that optimal power consumption cannot be realized according to the setting of the access speed and the number of waits.

Conventionally, when reading from or writing to a memory, control is performed in which the output time of the bus signal and the occupation time of the bus to be used are arbitrarily set in the same cycle in accordance with the access speed of the memory. Was performed.

FIG. 16 is a block diagram showing a configuration of such a conventional memory access device. In FIG. 16, the memory access device 1600 includes a weight control unit 16
01 and an output driver unit 1604, and address outputs 1610 to 16 output from the weight control unit 1601.
13 is an output driver 1620 of the output driver unit 1604
To 1623, buffered and output as driver output addresses 1640 to 1643. At the same time, the bus occupation signal 1660 is also output while the address outputs 1610 to 1613 are output.

The operation of the conventional memory access device configured as described above will be described with reference to FIG. The weight control unit 1601 controls the addresses 1610 to 161 according to the access time required by the memory 1603.
3 and the time for outputting the bus occupation signal 1660 are controlled as the number of waits. Output drivers 1620 to 1623 of the output driver unit 1604 have addresses 1610 to 161.
3 is input, buffering is performed, and driver output addresses 1640 to 1643 are output. The number of waits is determined by how many times the basic access time is repeated, and the number of waits can be set arbitrarily (not shown). The number of waits is determined by the access speed of the connected memory 1603, but the addresses 1610 to 1613 and the bus occupation signal 1660 cannot be set individually.

FIG. 17 is a diagram showing the operation timing of the conventional memory access device. In FIG. 17, each time from time t1 to t9 is the basic time of the minimum unit of access, and when an access time longer than the basic time is required, a series of accesses is continuously performed using a plurality of cycles after time t1. It is established. Here, the memory 1 requiring the time from time t1 to time t5 according to the access speed
603 will be described as an example. Memory access device 160
When outputting the driver output addresses 1640 to 1643 from 0, the wait control unit 1601 first outputs the address 1
610, address 1611, address 1612, and address 1613 are output from time t1 to time t5. The output drivers 1620 to 1621 receive the address signal as input, and output a driver output address 1640, a driver output address 1641, a driver output address 1642, and a driver output address 1643 between time t1 and time t5. In the same cycle, the bus occupancy signal 1660
Is also output between time t1 and time t5.

Therefore, in the conventional memory access device as described above, when the occupation time of the bus is made longer than the access time of the memory, it can be realized by setting the number of waits longer. During that time, it is necessary to output a bus signal, so that power consumption increases and the bus cannot be used effectively.

[0012]

As described above, in the conventional memory access device, the number of waits can be arbitrarily set according to the access speed of the memory, but the output capability to the bus is changed. Therefore, there has been a problem that optimal power consumption cannot be realized according to the setting of the memory access speed and the number of waits.

Although the output time of the bus signal and the occupation time of the bus to be used can be set arbitrarily at the same time, the bus occupation time cannot be set longer than the memory access time because they cannot be set individually. In this case, the output of the bus signal needs to be continued for longer than the access time.

The present invention has been made in order to solve such a problem, and has been made in order to realize optimum power consumption.
Enables change of bus driver capacity according to memory access speed and wait number settings, reduces power consumption, stops unnecessary bus signal output when access is completed, and uses buses effectively Therefore, an object of the present invention is to provide a memory access device capable of individually setting a bus signal output time and a bus occupation time to be used.

[0015]

According to a first aspect of the present invention, there is provided a memory access device, comprising:
A first means for variably setting an output time of a bus signal connected to the CPU in a read operation from the CPU or a write operation from the CPU; and a second means for variably setting an output driver capability for the bus signal. Means for arbitrarily setting the output time of the bus signal by the first means and the capability of the output driver by the second means according to the read or write time.

According to a second aspect of the present invention, there is provided a memory access device for variably setting an output time of a bus signal connected to the memory by a read operation from the memory or a write operation to the memory. Means, and second means for variably setting the capability of the output driver to the bus signal, and according to the access speed to the memory,
The access time by the first means and the capability of the output driver by the second means are arbitrarily set.

Further, in the memory access device according to the third aspect of the present invention, the memory access device may read out data from a CPU, or
In a write operation from a PU, a first means for variably setting an output time of a bus signal connected to the CPU and a second means for variably setting the capability of an output driver for the bus signal are provided. (1) The first operation is performed for reading from the CPU or writing operation from the CPU with respect to a second arrangement case formed of the same chip as a first arrangement case formed of another chip. The access time in the case and the access time in the second arrangement case are set to be the same, or (2) the read operation from the CPU or the write operation from the CPU is performed by the first operation.
The access time in the third arrangement case is different from the access time in the third arrangement case with respect to the third arrangement case constituted by another chip of the second delay component and the fourth arrangement case constituted by another chip of the second delay component. And setting the same access time in the arrangement case of No. 4 and the output time of the bus signal by the first means and the output driver of the second means by the second means according to the read or write time. The ability is set arbitrarily.

In the memory access device according to a fourth aspect of the present invention, the memory access device reads data from a CPU or stores
A first means for variably setting an output time of a bus signal connected to the CPU in a write operation from a PU; and a second means for variably setting an occupation time of the used bus, The output time of the bus signal by the first means and the occupation time of the bus by the second means are arbitrarily set.

According to a fifth aspect of the present invention, there is provided a memory access device for variably setting an output time of a bus signal connected to the memory by a read operation from the memory or a write operation to the memory. Means, and second means for variably setting the occupation time of the used bus, wherein the output time of the bus signal by the first means and the bus occupation time by the second means are arbitrarily set. To set.

A memory access device according to a sixth aspect of the present invention is the memory access device according to the fifth aspect, wherein the second means keeps reading from the memory or writing to the memory even after the end of the operation. Even when the occupation of the bus is maintained and memories having different access times are connected, the bus occupation time of each memory is made the same.

According to a seventh aspect of the present invention, in the memory access device, the first means for variably setting the output time of the bus signal connected to the memory in the operation of reading from or writing to the memory. A second means for variably setting the occupation time of the used bus; and a command decoder of a CPU for decoding data read from the memory, wherein the first means is set by the first means. Even after reading from the memory or writing to the memory is completed within the output time, while the occupation of the bus is maintained by the second means, the result of decoding from the instruction decoder of the CPU To the bus.

[0022]

DESCRIPTION OF THE PREFERRED EMBODIMENTS (Embodiment 1) A memory access device according to a second embodiment of the present invention will be described as a first embodiment with reference to FIGS.
FIG. 1 is a block diagram showing a configuration of the memory access device according to the first embodiment. In FIG. 1, addresses 110 to 113 output from the weight control unit 101 indicate each bit of the address, and output drivers 120 to 135
, Are buffered as driver output addresses 140 to 143 and output to the memory 103. The outputs of the output drivers 120 to 135 are controlled by output driver control signals 150 to 153 of the output driver control unit 102. The output driver control signal 150 is for the output drivers 120, 124, 128, 132, and the output driver control signal 151 is for the output drivers 121, 125, 12.
9, 133, the output driver control signal 152 corresponds to the output drivers 122, 126, 130, and 134, and the output driver control signal 153 corresponds to the output drivers 123, 127, 13
1, 135 are controlled.

Hereinafter, the operation of the memory access device configured as described above will be described by taking the address signal 110 as an example.
explain. The address 110 is generated by the weight control unit 101 according to a preset number of weights (not shown), and is input to the output drivers 120 to 123.
The output driver control unit 102 includes output drivers 120 to 12
3, the output driver control signals 150 to 153 are made valid or invalid according to the setting (not shown) of which to use. Similarly, the addresses 111 to 113 are also input to the output drivers 124 to 135,
Through 135. The case where the setting of the number of weights in weight control section 101 is performed using a 4-bit register (not shown) will be described as an example.

Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 Weight 0 (basic cycle) 0 0 0 1 Weight 1 0 0 1 0 Weight 2 · · · · · · · · · · · · · · · 1 1 0 1 weight 13 1 11 0 weight 14 1 1 1 1 1 weight 15 is defined, and the weight control unit 101 determines the output period of the addresses 110 to 113 according to the weight. Further, as an example of setting which of the output driver control signals 150 to 153 is to be enabled by a 4-bit register (not shown), bit 0 corresponds to output driver control signal 150, and bit 1 corresponds to output driver control. Bit 2 corresponds to output driver control signal 152, bit 3 corresponds to signal 151, bit 3
In response to the output driver control signal 153, bit 3 bit 2 bit 1 bit 0 0 0 0 0 unused 0 0 0 1 output drivers 120, 124, 128, 132 are valid 0 0 1 0 output drivers 121, 125, 129, 133 are effective ........ 1101 Output driver 120, 122, 123, 124, 126, 127, 128, 130, 131, 132, 134, 135 Valid 1 1 1 0 Output drivers 121, 122, 123, 125, 126, 127, 129, 130, 131, 133, 134, 135 are valid 1 1 1 1 Output drivers 120, 121, 122, 123, 124, 125, 126, 127, 128, 129, 130, 131, 132, 133, 134 and 135 are valid. According to this setting, the output drivers 120 to 13
5 is selected and the driver output addresses 140 to 143 are output. Output driver 120 to 123, or output driver 124 to 127, or output driver 128
131 to 131 or the output drivers 132 to 135 are output drivers having the same drive capability or output drivers having different drive capabilities, but the output driver 120 controlled by the output driver control signal 150;
124, 128, 132, or the output drivers 121, 125, 1 controlled by the output driver control signal 151.
29, 133, or output drivers 122, 126, 130, 13 controlled by the output driver control signal 152.
4 or the output drivers 123, 127, 131, and 135 controlled by the output driver control signal 153 are constituted by output drivers having the same drive capability.

The operation of the memory access device configured as described above will be described below with reference to the drawings. 2 to 5 are timing charts of the operation of the memory access device according to the first embodiment. In FIG.
A description will be given of a case where the memory 103 requires time from time t1 to time t6 to realize access. Each of the times t1 to t9 is a basic time of a minimum unit of access. When an access time longer than the basic time is required, a series of accesses is established by continuously using a plurality of cycles after the time t1.

Time t0 is an initial state. At time t1, the address 110 is output from the weight control unit 101, and at the same time t1, the output driver control unit 150 outputs the output driver control signal 150 and the output driver control signal 15
1. An output driver control signal 152 and an output driver control signal 153 are output. In this example, only the output driver control signal 150 is valid, and the output driver control signal 151,
Output driver control signal 152, output driver control signal 1
53 is invalid. When only the output driver control signal 150 is valid, of the output drivers 120 to 123 that drive the address 110, only the output driver 120 is valid, and the output drivers 121 to 123 are not driven. The driver output address 140 is output from the output driver 120 to the memory 103 at time t1. Since the address 110 and the output driver control signal 150 are output between the time t1 and the time t6, the driver output address 1
40 is also output between time t1 and time t6.

FIG. 3 shows the operation timing of the memory 103 in the case where the access from the memory 103 requires time from time t1 to time t5. FIG. 3 shows the time t1
Each time from t9 to t9 is a basic time of a minimum unit of access, and when an access time longer than the basic time is required,
A series of accesses is established by continuously using a plurality of cycles after time t1. Time t0 is the initial state.
At time t1, the address 110 becomes the wait control unit 1
01 and output driver control unit 1 at the same time t1.
02 outputs an output driver control signal 150, an output driver control signal 151, an output driver control signal 152, and an output driver control signal 153. In this example, only the output driver control signal 150 and the output driver control signal 151 are valid, and the output driver control signal 152 and the output driver control signal 153 are invalid. Output driver control signal 1
50, since only the output driver control signal 151 is valid, the output driver 120 that drives the address 110
Of the output drivers 123 to 123, only the output drivers 120 and 121 are valid, and the output drivers 122 to 123 are not driven. The driver output address 140 is output from the output drivers 120 and 121 to the memory 103 at time t1.
Since the address 110, the output driver control signal 150, and the output driver control signal 151 are output between the time t1 and the time t5, the driver output address 140 is also changed to the time t1.
From time t5 to time t5.

FIG. 4 shows the operation timing when the memory 103 requires time from time t1 to time t4 to realize the access. FIG.
Each time of t9 is a basic time of a minimum unit of access,
When an access time longer than the basic time is required, a series of accesses is established by continuously using a plurality of cycles after time t1. Time t0 is the initial state. At time t1, the address 110 becomes the weight control unit 101
From the output driver control unit 102 at the same time t1.
Output driver control signal 150, output driver control signal 151, output driver control signal 152, and output driver control signal 153. In this example, the output driver control signal 150, the output driver control signal 151, and the output driver control signal 152 are valid, and the output driver control signal 153 is invalid. Output driver control signal 150, output driver control signal 151, output driver control signal 15
2 is valid, the output driver 12 out of the output drivers 120 to 123 driving the address 110
0, 121 and 122 are enabled, and the output driver 123
Only is not driven. Driver output address 140
Are output from the output drivers 120, 121, 122 to the memory 103 at time t1. Address 110, output driver control signal 150, output driver control signal 151, and output driver control signal 152 are output from time t1 to time t4.
Therefore, the driver output address 140 is also output between time t1 and time t4.

FIG. 5 shows the operation timing when the memory 103 requires the time from time t1 to time t2 to realize the access. Times t1 to t in FIG.
9 is the basic time of the minimum unit of access, and if an access time longer than the basic time is required, the time t
A series of accesses is established by using a plurality of cycles after 1 consecutively. Time t0 is the initial state. Time t
At 1, the address 110 is output from the weight control unit 101, and at the same time t1, the output driver control signal 150, the output driver control signal 151, the output driver control signal 152, and the output driver control signal 153 are output from the output driver control unit 102. You. In this example, the output driver control signal 150, the output driver control signal 151, the output driver control signal 152, and the output driver control signal 153 are all valid. Output driver control signal 150, output driver control signal 151, output driver control signal 152,
Since the output driver control signals 153 are all valid, the output drivers 120 to 12 driving the address 110 are output.
3 are all enabled and driven. The driver output address 140 is changed to the output drivers 120 to 123 at time t1.
Is output to the memory 103. Address 110, output driver control signal 150, output driver control signal 15
1, since the output driver control signal 152 and the output driver control signal 153 are output between the time t1 and the time t2, the driver output address 140 is also output between the time t1 and the time t2.

As described above, the memory access device according to the first embodiment can shorten the bus signal output time by making the driver capability for the bus signal variable, thereby realizing an optimum power consumption. it can.

(Embodiment 2) Hereinafter, a memory access device according to a third embodiment of the present invention will be described as a second embodiment with reference to FIGS. 6, 7, and 8. FIG.
6, addresses 110 to 113 output from the weight control unit 101 indicate each bit of the address, and are buffered as driver output addresses 140 to 143 via output drivers 120 to 135 and stored in the memory 105 or the memory 106. Is output. The outputs of the output drivers 120 to 135 are controlled by output driver control signals 150 to 153 of the output driver control unit 102. The output driver control signal 150 is for the output drivers 120, 124, 128, 132, and the output driver control signal 151 is for the output drivers 121, 125, 129, 1
33, and the output driver control signal 152 is the output driver 1
22, 126, 130, and 134, and the output driver control signal 153 is the output driver 123, 127, 131, 13
5 is controlled.

Hereinafter, the operation of the memory access device configured as described above will be described with reference to the address signal 110 as an example.
This will be described with reference to FIGS. The address 110 is generated by the weight control unit according to a preset number of weights (not shown),
123 is input. The output driver control section outputs the output driver control signals 150 to 150 according to the setting (not shown) of which of the output drivers 120 to 123 to use for output.
Enable 153. Similarly, the addresses 111 to 113 are input to the output drivers 124 to 135 and output via the output drivers 124 to 135. Hereinafter, the setting of the number of weights in the weight control unit will be described with reference to an example in which the setting is performed using a 4-bit register (not shown).

Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 Weight 0 (basic cycle) 0 0 0 1 Weight 1 0 0 1 0 Weight 2 · · · · · · · · · · · · · · · 1 1 0 1 weight 13 1 11 0 weight 14 1 1 1 1 1 weight 15 is defined, and the weight control unit 101 determines the output period of the addresses 110 to 113 according to this. Further, taking as an example a case where the setting of which of the output driver control signals 150 to 153 is to be made effective is performed by a 4-bit register (not shown), bit 0 is output driver control signal 1
50, bit 1 corresponds to the output driver control signal 151, bit 2 corresponds to the output driver control signal 152,
Assuming that bit 3 corresponds to the output driver control signal 153,

Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 Not used 0 0 0 1 Output drivers 120, 124, 128, 132 are valid 0 0 1 0 Output drivers 121, 125, 129, 133 are valid ... ..... 1 1 0 1 Output driver 120, 122, 123, 124, 126, 127, 128, 130, 131, 132, 134, 135 enabled 1 1 1 0 Output driver 121 , 122, 123, 125, 126, 127, 129, 130, 131, 133, 134, 135 are valid. 130, 131, 132, 133, 134, 135 are valid. According to this setting, the output drivers 120 to 13
5 is selected and the driver output addresses 140 to 143 are output. Output driver 120 to 123, or output driver 124 to 127, or output driver 128
131 to 131 or the output drivers 132 to 135 are output drivers having the same drive capability or output drivers having different drive capabilities, but the output driver 120 controlled by the output driver control signal 150;
124, 128, 132, or the output drivers 121, 125, 1 controlled by the output driver control signal 151.
29, 133, or output drivers 122, 126, 130, 13 controlled by the output driver control signal 152.
4 or the output drivers 123, 127, 131, and 135 controlled by the output driver control signal 153 are constituted by output drivers having the same drive capability.

FIGS. 7 and 8 both show the operation timing of the memory access device.
No. 5 requires time from time t1 to t6 for access, whereas the memory 106 can be accessed within time from time t1 to t2. In FIG. 7, times t1 to t
9 is the basic time of the minimum unit of access, and the time t
0 is an initial state. At time t1, address 11
0 is output from the weight control unit 101, and the output driver control unit 102 outputs the output driver control signal 1 at the same time t1.
50, an output driver control signal 151, an output driver control signal 152, and an output driver control signal 153 are output. The memory 105 needs time t1 to t6 for access, and (time t1 to t6 for access to the memory 105).
6)> (time t1 to t2 or less for access to memory 106), so that memory 106 is accessed in accordance with the access time to memory 105. The output driver control signal 150, the output driver control signal 151, the output driver control signal 152, and the output driver control signal 153 are all valid. Therefore, all the output drivers 120 to 123 that drive the address 110 are enabled and driven. Driver output address 140 is output from output driver 120 to memory 105 at time t1. Since the address 110, the output driver control signal 150, the output driver control signal 151, the output driver control signal 152, and the output driver control signal 153 are output from the time t1 to the time t6, the driver output address 140 is also changed from the time t1 to the time t6. And the memory 105 outputs data at the timing of the time t6.

In FIG. 8, time t0 is an initial state. At time t1, the address 110 is output from the weight control unit 101, and at the same time t1, the output driver control unit outputs an output driver control signal 150, an output driver control signal 151, an output driver control signal 152,
An output driver control signal 153 is output. Memory 10
6 requires time t1 to t2 for access, and (time t1 to t6 for access to memory 105)> (memory 1
In this example, the memory 106 is accessed in accordance with the access time to the memory 105.

Only the output driver control signal 150 is made valid, and the output driver control signal 151, the output driver control signal 152, and the output driver control signal 153 are made invalid.
Therefore, only the output driver 120 that drives the address 110 becomes valid, and the output drivers 121 to 123 are activated.
Becomes invalid. When the driver output address 140 is at time t1
Is output from the output driver 120 to the memory 106.
Address 110 and output driver control signal 150 are at time t
Since it is output between 1 and time t6, the driver output address 140 is also output between time t1 and time t6,
The output of the memory 106 outputs data from the timing of the time t2.

As described above, in the memory access device according to the second embodiment, when memories having different access times are connected, the same access time can be set by changing the driver capability.

(Embodiment 3) Hereinafter, claim 5 of the present invention will be described.
Third Embodiment A memory access device corresponding to the invention corresponding to the third embodiment will be described as a third embodiment with reference to FIGS. 9, 10, and 11. FIG. FIG. 9 is a block diagram showing one configuration of the memory access device according to the third embodiment. In FIG. 9, a weight control unit 901 controls the timing of outputting addresses 910 to 913. Addresses 910 to 913 output from the weight control unit 901 indicate each bit of the address, are buffered as driver output addresses 940 to 943 via output drivers 920 to 923, and output to the memory 903. Further, a bus occupation signal 960 required for accessing the memory 903 is output from the bus occupation control unit 905.

The operation of the memory access device configured as described above will be described below. Addresses 910 to 913 are generated by a weight control unit according to a preset number of weights (not shown), and output drivers 920 to 913 are output.
923. As an example, when setting the number of weights in the weight control unit using a 4-bit register (not shown), bit 3 bit 2 bit 1 bit 0 0 0 0 0 weight 0 (basic cycle) 0 0 0 1 weight 1 0 0 1 0 Weight 2 ··································································· 11 1 1 1 Determines the output period of addresses 910-913. When the valid period of the bus occupation signal 960 as an example is set by a 4-bit register (not shown), bit 3 bit 2 bit 1 bit 0 0 0 0 0 1 cycle occupation (basic cycle) 0 0 0 1 2 Occupied 0 0 1 0 3 Occupied 3 Cycles ・ ・ ・ ・ ・ １ １ １ １ １ １ Set. According to this setting, a bus occupation signal 960 is output, and the bus is occupied. The setting of the number of waits and the setting of the valid period of the bus occupation signal 960 can be performed independently, provided that (wait period) ≦ (bus occupation period).

FIG. 10 is an operation timing chart of the memory access device according to the third embodiment. In FIG. 10, the memory 9 which requires time from time t1 to time t5 for access
03 will be described as an example. Each of the times t1 to t9 is a basic time of a minimum unit of access, and the time t0 is an initial state. At time t1, address 910, address 9
11, an address 912 and an address 913 are output from the weight control unit 901, and driver output addresses 940 to 943 are output via output drivers 920 to 923. Since the memory 903 requires time from time t1 to time t5 for access, the memory 903 occupies the bus between time t1 and time t5.
60 is output between times t1 and t5. Therefore, the number of waits for outputting the address 910, the address 911, the address 912, and the address 913 (= output period: time t
1 to t5) and the output period of the bus occupation signal 960 (time t1
To t5) are identical.

FIG. 11 shows another example of the operation timing of the memory access device according to the third embodiment. In this example, similarly, the memory 903 performs access from time t1 to time t5.
, But the bus occupation time is longer. In FIG. 11, each of the times t1 to t9 is the basic time of the minimum unit of access, and the time t0 is an initial state. At time t1, address 910, address 91
1, an address 912 and an address 913 are output from the weight control unit 901, and driver output addresses 940 to 943 are output via output drivers 920 to 923. The memory 903 occupies the bus for outputting the address 910, the address 911, the address 912, and the address 913 during the time t1 to t5 because the memory 903 requires time from the time t1 to t5 for access. Therefore, bus occupation control section 905 outputs bus occupation signal 960 during times t1 to t5. However, in this example, address 910, address 9
Even after outputting the address 11, the address 912, and the address 913, the bus is occupied, so that it is necessary to continuously output the bus occupation signal 960 during the time t6 to t8. For this reason,
The output period (time t1 to t8) of the bus occupation signal 960 is longer than the number of waits (= output period: time t1 to t5) for outputting the address 910, the address 911, the address 912, and the address 913.

As described above, in the memory access device according to the third embodiment, the access time and the bus occupation time can be set individually, so that it is not necessary to output the bus signal more than necessary, and power can be saved. Becomes

(Embodiment 4) Hereinafter, claim 7 of the present invention will be described.
A memory access device corresponding to the invention described in (4) will be described as a fourth embodiment with reference to FIGS. FIG.
FIG. 9 is a block diagram showing a configuration of a memory access device according to a fourth embodiment. 12, a weight control unit 901 controls the timing of outputting addresses 910 to 913. Addresses 910 to 913 output from the weight control unit 901 indicate each bit of the address, are buffered as driver output addresses 940 to 943 via output drivers 920 to 923, and output to the memory 903. Further, a bus occupation signal 960 required for accessing the memory 903 is output from the bus occupation control unit 905. The driver output addresses 940 to 943 are input to the memory 1203, and the memory output 1250 is
U (not shown) is input to the command decoder 1204. Also, the command decryption unit 1204 outputs a command decryption result 1251.

The operation of the memory access device configured as described above will be described below. Address 910-9
13 is generated by the weight control unit in accordance with a preset number of weights (not shown),
It is input to 0-923. Here, as an example, when setting the number of waits in the weight control unit using a 4-bit register (not shown), bit 3 bit 2 bit 1 bit 0 0 0 0 0 0 weight 0 (basic cycle) 0 0 0 1 Weight 1 0 0 1 0 Weight 2 1 1 1 1 1 1 0 1 1 1 1 0 Weight 1 1 1 1 1 1 Weight 15 is defined, and weight control is performed accordingly. The unit 901 determines the output period of the addresses 910 to 913. Further, assuming that the valid period of bus occupation signal 960 is set by a 4-bit register (not shown), bit 3 bit 2 bit 1 bit 0 0 0 0 0 1 cycle occupation (basic cycle) 0 0 0 1 2 cycles occupied 0 0 1 0 3 cycles occupied ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ 110 1 14 cycles occupied 1 1 1 0 15 cycles occupied 1 1 1 1 16 cycles occupied Settings. According to this setting, a bus occupation signal 960 is output, and the bus is occupied. The setting of the number of waits and the setting of the valid period of the bus occupation signal 960 can be performed independently, and it is possible to satisfy (wait period) ≦ (bus occupation period).

On the other hand, driver output addresses 940 to 94
3 is input to the memory 1203, and the memory output 1250 is output. When the content of the memory output 1250 is command data of a CPU (not shown), it is input to the command decoder 1204. In the instruction decoder 1204, a control signal of the CPU necessary for execution of the CPU is output as an instruction decoder output 1251.

FIG. 13 is an operation timing chart of the memory access device according to the fourth embodiment. In this figure,
The memory 1203 will need to be accessed at times t1 to t2, and the instruction decoder output 1251 will be output at times t3 to t4.

In FIG. 13, each time from time t1 to time t9 is the basic time of the minimum unit of access, and time t0 is an initial state. At time t1, an address 910, an address 911, an address 912, and an address 913 are output from the wait control unit 901 and output drivers 920 to 92
3, the driver output addresses 940 to 943 are output. The memory 1203 is accessed at times t1 to t2.
, The bus is occupied between time t1 and t2. Therefore, the bus occupation control unit 905 outputs the bus occupation signal 960 during the time t1 to t2.

The memory 1203 stores the driver output address 9
40 to 943, the memory output 1250 is set at time t2
Output to The memory output 1250 at the time t2 is input to the instruction decoder 1204, and later, a result 1251 obtained by decoding from the instruction decoder is output. This command decoding result 12
Further, the time required to output 51 is t3 to t4.
The bus occupation control unit 905 also continuously outputs the bus occupation signal 960 during the period of.

As described above, the memory access device according to the fourth embodiment separately sets the access time and the bus occupation time, thereby increasing the decoding result from the instruction decoder of the CPU without extending the memory access time. Can be output to the bus. Therefore, power saving is achieved.

In each of the above embodiments, a description has been given of a configuration in which a memory is accessed as an example of an object to be accessed. However, the present invention can be similarly applied to a circuit configured with random logic. The effect can be obtained.

Further, in the case where a system in which the memory access device and the memory of the present invention are formed of semiconductors of different chips is changed to a system formed of semiconductors of the same chip,
(Access time of another chip system) ≧ (Access time of the same chip system) is assumed, and by making the operation time of the system constituted by the same chip as that of the system constituted by another chip the same, Similar operation results can be guaranteed. In addition, it is also possible to guarantee the same operation result by making the operations between systems constituted by different chips having different wiring delays the same access time.

[0053]

As described above, according to the memory access device of the first aspect of the present invention, reading from the CPU,
Alternatively, in the write operation from the CPU, the C
A first means for variably setting an output time of a bus signal connected to the PU; and a second means for variably setting the capability of an output driver for the bus signal, wherein the second means is responsive to the read or write time. Since the output time of the bus signal by the first means and the ability of the output driver by the second means are arbitrarily set, the optimum performance can be obtained by changing the ability of the bus driver according to the access speed. The advantage is that power consumption can be achieved.

According to the memory access device of the second aspect of the present invention, the output time of the bus signal connected to the memory is variably set by a read operation from the memory or a write operation to the memory. First means, and second means for variably setting an output driver capability for the bus signal.
Means for arbitrarily setting the access time of the first means and the capability of the output driver by the second means according to the access speed to the memory. Therefore, there is an effect that optimum power consumption can be realized by changing the capability of the bus driver according to the setting of the number of waits.

According to the memory access device of the third aspect of the present invention, reading from the CPU or the C
In a write operation from a PU, a first means for variably setting an output time of a bus signal connected to the CPU and a second means for variably setting the capability of an output driver for the bus signal are provided. (1) The first operation is performed for reading from the CPU or writing operation from the CPU with respect to a second arrangement case formed of the same chip as a first arrangement case formed of another chip. The access time in the case and the access time in the second arrangement case are set to be the same, or (2) the read operation from the CPU or the write operation from the CPU is performed by the first operation.
The access time in the third arrangement case is different from the access time in the third arrangement case with respect to the third arrangement case constituted by another chip of the second delay component and the fourth arrangement case constituted by another chip of the second delay component. And setting the same access time in the arrangement case of No. 4 and the output time of the bus signal by the first means and the output driver of the second means by the second means according to the read or write time. Since the capacity is set arbitrarily, even in the above-described various arrangement cases, by setting the access time to be the same, the optimum consumption can be achieved by changing the bus driver capacity according to the setting of the memory access speed and the number of waits. There is an effect that electric power can be realized.

According to the memory access device of the present invention, the output time of the bus signal connected to the CPU is variably set in the read operation from the CPU or the write operation from the CPU. First means and second means for variably setting the occupation time of the used bus, wherein the bus signal output time by the first means and the bus occupation time by the second means The optimal power consumption and unnecessary bus signal output at the end of the access can be stopped by individually setting the bus signal output time and the bus occupation time to be used. Is obtained.

According to the memory access device of the fifth aspect of the present invention, the first operation for variably setting the output time of the bus signal connected to the memory by a read operation from the memory or a write operation to the memory. Means, and second means for variably setting the occupation time of the used bus, wherein the output time of the bus signal by the first means and the bus occupation time by the second means are arbitrarily set. Since the setting is performed, optimal power consumption and unnecessary output of the bus signal at the end of the access can be stopped by individually setting the output time of the bus signal and the bus occupation time to be used. Has a significant effect.

According to the memory access device described in claim 6 of the present invention, in the memory access device described in claim 5, even after the read operation from the memory or the write operation to the memory is completed, the second Even when memories having different access times are connected by the means, even when memories having different access times are connected, the bus occupation times of the above memories are made the same, so that an access operation not required within the bus occupation times can be performed. So that optimal power consumption can be realized.

According to the memory access device of the present invention, in the operation of reading from or writing to the memory, the output time of the bus signal connected to the memory is variably set. Means, a second means for variably setting the occupation time of the used bus, and a CP for decoding data read from the memory.
U, and a command decoder of U is provided. Even after reading from the memory or writing to the memory is completed within the output time set by the first means, the bus of the bus is controlled by the second means. While the occupancy is maintained, the third means for outputting the decoded result from the instruction decoder of the CPU to the bus is provided, so that unnecessary bus signal output at the time when access is completed is provided. , It is possible to obtain an advantageous effect that the occupied bus can be used for another purpose.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one configuration of a memory access device according to a first embodiment.

FIG. 2 is a diagram showing a first example of operation timing of the memory access device according to the first embodiment;

FIG. 3 is a diagram showing a second example of the operation timing of the memory access device according to the first embodiment.

FIG. 4 is a diagram showing a third example of the operation timing of the memory access device according to the first embodiment;

FIG. 5 is a diagram showing a fourth example of the operation timing of the memory access device according to the first embodiment;

FIG. 6 is a block diagram showing a configuration of a memory access device according to a second embodiment.

FIG. 7 is a diagram showing a first example of operation timing of the memory access device according to the second embodiment;

FIG. 8 is a diagram showing a second example of the operation timing of the memory access device according to the second embodiment.

FIG. 9 is a block diagram showing one configuration of a memory access device according to a third embodiment.

FIG. 10 is a diagram showing a first example of operation timing of the memory access device according to the third embodiment.

FIG. 11 is a diagram showing a second example of the operation timing of the memory access device according to the third embodiment.

FIG. 12 is a block diagram showing one configuration of a memory access device according to a fourth embodiment.

FIG. 13 is a diagram showing operation timings of the memory access device according to the fourth embodiment.

FIG. 14 is a block diagram showing, as an example of a conventional technique, a configuration of a memory access device in which the capability of an output driver for an access signal to a memory is constant and the output time of a bus signal can be set arbitrarily.

FIG. 15 is a diagram showing operation timings of the conventional memory access device of FIG. 14;

FIG. 16 is a block diagram showing, as an example of a conventional technique, a configuration of a memory access device in which an accessing side can arbitrarily set an output time of a bus signal and an occupation time of a bus to be used in the same cycle in accordance with a memory access speed. It is.

17 is a diagram showing operation timings of the conventional memory access device of FIG. 16;

[Explanation of symbols]

 REFERENCE SIGNS LIST 100 memory access device 101 weight control unit 102 output driver control unit 103 memory 104 output driver unit 105 memory 106 memory 110 to 113 address 120 to 135 output driver 140 to 143 driver output address 150 to 153 output driver control signal 900 memory access device 901 Wait controller 903 Memory 904 Output driver 905 Bus occupancy controller 910-913 Address 920-923 Output driver 940-943 Driver output address 960 Bus occupancy signal 1203 Memory 1204 Instruction decoder 1250 Memory output 1251 Instruction decoder output 1400 Memory access Device 1401 Weight control unit 1402 Output driver control unit 1403 Memory 1404 Output driver unit 1410 1413 address 1420-1423 output driver 1440-1443 driver output address 1450 output driver control signal 1600 memory access unit 1601 weight control unit 1603 memory 1604 output driver unit 1610-1613 address 1620-1623 output driver 1640-1643 driver output address 1660 bus occupation signal

Claims (7)

[Claims] Reading from a CPU or the C
In a write operation from a PU, a first means for variably setting an output time of a bus signal connected to the CPU, and a second means for variably setting the capability of an output driver for the bus signal are provided. A memory access device for arbitrarily setting an output time of a bus signal by the first means and a capability of an output driver by the second means according to the read or write time. A first means for variably setting an output time of a bus signal connected to the memory in a read operation from the memory or a write operation to the memory; and a capability of an output driver for the bus signal. Variably setting second means, and arbitrarily setting an access time by the first means and a capability of an output driver by the second means according to an access speed to the memory. Characteristic memory access device. Reading from the CPU or the C
In a write operation from a PU, a first means for variably setting an output time of a bus signal connected to the CPU, and a second means for variably setting the capability of an output driver for the bus signal are provided. (1) reading from the CPU or the CPU
The write operation from the first layout case and the second layout case configured by the same chip are performed in the same manner as the first layout case configured by another chip and the access time in the first layout case by the second layout case.
The same access time as in the above arrangement case, or (2) reading from the CPU or the CPU
The write operation from the third arrangement case is performed in the third arrangement case constituted by another chip of the first delay component and the fourth arrangement case constituted by another chip of the second delay component. And the access time in the fourth arrangement case can be set to be the same, and the output time of the bus signal by the first means and the second access time can be set in accordance with the read or write time. 2. The memory access device according to claim 2, wherein the capability of the output driver is arbitrarily set. 4. Reading from a CPU or the C
In the write operation from the PU, the first means for variably setting the output time of the bus signal connected to the CPU, and the second means for variably setting the occupation time of the used bus, A memory access device, wherein the output time of the bus signal by the first means and the occupation time of the bus by the second means are arbitrarily set. 5. A first means for variably setting an output time of a bus signal connected to the memory in a read operation from the memory or a write operation to the memory, and variably setting an occupation time of the used bus. And a second means for setting, wherein the output time of the bus signal by the first means and the bus occupation time by the second means are arbitrarily set. 6. The memory access device according to claim 5, wherein the occupation of the bus is maintained by the second means even after the operation of reading from or writing to the memory is completed, and the access time is different. A memory access device, wherein the bus occupancy time of each memory is the same even when the memories are connected. 7. A first means for variably setting an output time of a bus signal connected to the memory in a read operation from a memory or a write operation to a memory; And a command decoder of a CPU for decoding data read from the memory, and reading from the memory or memory within the output time set by the first means. A third means for outputting a result of decoding from the instruction decoder of the CPU to the bus while the occupation of the bus is maintained by the second means even after the writing to the bus is completed. A memory access device, comprising: