JP2002290365A - Orthogonal frequency division multiplex modulation circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an orthogonal frequency division multiplex modulation circuit that suppresses production of harmonies by using interpolators 5, 6 whose interpolation degree is 2 and connected in cascade as interpolation means and including infinite impulse response digital full band pass filters 51 , 53 , 61 and 63 so as to prevent a circuit scale of a logic circuit section from being increased. SOLUTION: The orthogonal frequency division multiplex modulation circuit comprises an inverse Fourier transform means 3 that maps a digital modulation signal with a plurality of subcarriers around a half of a sampling frequency fs, applies inverse Fourier transform to the mapped signals and outputs a plurality of inverse Fourier transform signals, an interpolation means comprising one or more interpolators 5, 6 that interpolate in-phase and quadrature signals separately and sequentially by an interpolation degree of 2 and are connected in cascade, and orthogonal modulation means 7I, 7Q, 8 and 9 that apply orthogonal modulation to the in-phase interpolation signal and the quadrature interpolation signal outputted from the interpolation means.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an orthogonal frequency division multiplexing modulation circuit, and more particularly to digital terrestrial broadcasting and MMA.
It is used in digital wireless systems such as high-speed wireless LAN (local area network) of C (Multimedia Mobile Access Communication), and even when the interpolation order is relatively large when a modulated signal is interpolated and output, The present invention relates to an orthogonal frequency division multiplexing modulation circuit in which generation of harmonics is suppressed and the circuit scale of an interpolator does not increase.

[0002]

2. Description of the Related Art Recently, in the field of broadcasting, digital terrestrial broadcasting, which has good broadcast quality and enables transmission of many broadcast channels, has been spotlighted in place of conventional analog terrestrial broadcasting. It has become. Although the main broadcast has already begun in Europe and the United States, practical use is expected soon in Japan.

[0003] In terrestrial digital broadcasting in Europe and Japan, orthogonal frequency division multiplexing (OFDM) is applied to broadcast signals.
A modulation system is adopted, and a terrestrial digital broadcast transmitter for transmitting terrestrial digital broadcasting uses an orthogonal frequency division multiplex modulation circuit for forming an orthogonal frequency division multiplex modulation signal.

Conventionally, an orthogonal frequency division multiplexing modulation circuit used in a terrestrial digital broadcast transmitter has an inverse Fourier transform for mapping a digitally modulated signal to a plurality of subcarriers and performing a plurality of (N) points of inverse Fourier transform. Fourier transform (IF
FT) circuit, and an interpolation circuit section for interpolating the output signal of the inverse Fourier transform circuit at a sampling frequency that is an integral multiple of the sampling frequency.

FIG. 15 is a block diagram showing an example of the configuration of such a known orthogonal frequency division multiplex modulation circuit, which is provided with an interpolation circuit section for interpolating at four times the sampling frequency.

FIG. 16 is a diagram showing a signal waveform (frequency spectrum) obtained in each section of the orthogonal frequency division multiplexing modulation circuit shown in FIG.

As shown in FIG. 15, this orthogonal frequency division multiplex modulation circuit comprises a digital modulator 41, a serial-parallel converter (S / P) 42, an inverse Fourier transformer (IFFT) 43, and a parallel modulator. -Serial converter (P /
S) 44, an in-phase signal interpolator 45I comprising a finite impulse response (FIR) low-pass filter (LPF),
Finite impulse response (FIR) low-pass filter (L
PF), an in-phase signal multiplier 46I, a quadrature signal multiplier 46Q, and a local oscillator 47Q.
, A 90 ° phase shifter 48, an adder 49, and a digital-to-analog converter (D / A) 50. The in-phase signal interpolator 45I, the quadrature signal interpolator 45Q, and the in-phase signal multiplier 46
I, the quadrature signal multiplier 46Q, the local oscillator 47, and the 90 ° phase shifter 48 constitute an interpolation circuit. Further, a circuit portion including the in-phase signal multiplier 46I, the in-phase signal multiplier 46I, the local oscillator 47, the 90 ° phase shifter 48, and the adder 49 constitutes a quadrature modulation circuit.

The digital modulator 41 has an input connected to the digital data input terminal 51 and an output connected to the input of the serial-parallel converter 42. The inverse Fourier transformer 43 has an input connected to the output of the serial-parallel converter 42, and an output connected to the parallel-serial converter 44.
Connected to the input of The in-phase signal interpolator 45I has an input connected to the in-phase output of the parallel-serial converter 44,
The output is connected to a first input of the in-phase signal multiplier 46I.
The orthogonal signal interpolator 45Q has an input connected to the orthogonal output of the parallel-serial converter 44, and an output connected to a first input of the orthogonal signal multiplier 46Q. In-phase signal multiplier 46I
Has a second input connected to the output of local oscillator 47 and an output connected to a first input of adder 49. The quadrature signal interpolator 45Q has a second input connected to the output of the local oscillator 47 through the 90 ° phase shifter 48, and an output connected to a second input of the adder 49. The digital-analog converter 50 has an input connected to the output of the adder 49 and an output connected to the analog signal output terminal 52.

The operation of the orthogonal frequency division multiplex modulation circuit having the above configuration will be described with reference to a signal waveform diagram shown in FIG.

When digital data is output from a data source (not shown in FIG. 15), the digital data is supplied to a digital modulator 41 through a digital data input terminal 51, and the digital modulator 41 samples the sampling frequency fs'. Performs digital modulation such as quadrature phase shift keying (QPSK), and outputs from the digital modulator 41 an in-phase digital modulation signal (I) in phase with the input digital data and a quadrature digital modulation signal having a phase difference of 90 ° with the input digital data. (Q) is output. next,
The in-phase digital modulation signal and the quadrature digital modulation signal are subjected to serial-parallel conversion in the serial-parallel converter 42, respectively, and supplied to the inverse Fourier transformer 43 as an in-phase parallel signal and a quadrature parallel signal. The inverse Fourier transformer 43 maps the supplied in-phase parallel signal and quadrature parallel signal to a plurality of subcarriers, and adds a plurality of null (0) carriers to perform an inverse Fourier transform of a plurality (N) points. To output N in-phase inverse Fourier transform signals and orthogonal inverse Fourier transform signals. Next, each of the N in-phase inverse Fourier transform signals and the quadrature inverse Fourier transform signals are subjected to parallel-serial conversion in the parallel-serial converter 44, respectively, to generate a signal spectrum waveform A as shown in the first stage of FIG. The signals are supplied to the in-phase signal interpolator 45I and the quadrature signal interpolator 45Q at the sampling frequency fs as the in-phase serial signal (I) and the quadrature serial signal (Q).

In this case, the in-phase signal interpolator 45I and the quadrature signal interpolator 45Q are each composed of a finite impulse response digital filter, and have a sampling frequency f
Interpolation is performed at a sampling frequency 4fs obtained by multiplying s by an interpolation order n (an integer, 4 in this example).
Frequency spectrum waveform B as shown in the second row of
Is formed. After that, these interpolated signals are converted into signals having three frequency spectra in the middle of the signal band by the low-pass characteristics of the finite impulse response digital low-pass filter as shown in the second stage of FIG. Only the signals having the two frequency spectra at both ends are removed and extracted, and supplied to the in-phase signal multiplier 46I and the quadrature signal multiplier 46Q, respectively.

The in-phase signal multiplier 46I is supplied with a local oscillation signal of the sampling frequency fs from the local oscillator 47 together with the output signal of the in-phase signal interpolator 45I and multiplies the signals by a quadrature signal multiplier. 46Q is a local oscillator 47 together with the output signal of the quadrature signal multiplier 46Q.
The local oscillation signal obtained by shifting the local oscillation signal of the sampling frequency fs by 90 ° by the 90 ° phase shifter 48 is supplied and multiplied by the signals. As shown in the fourth stage of FIG. A signal having a frequency spectrum waveform D is obtained. After these signals are added by the adder 49, they are supplied to a digital-analog converter 50, where they are subjected to digital-analog conversion, and supplied to the analog signal output terminal 52 as analog signals.

FIG. 17 shows an in-phase signal interpolator 45I.
FIG. 9 is a circuit diagram showing a basic circuit example of a finite impulse response (FIR) digital filter used in a quadrature signal interpolator 45Q.

As shown in FIG. 17, this finite impulse response (FIR) digital low-pass filter 45I
(45Q) includes an input terminal 53, an output terminal 54, and eight of the delay unit 55 ₁ to 55 _8, and nine multipliers 56 ₁ to 56 _9, nine multiplier coefficient generating unit 57 ₁ to 57 ₉ and
And an adder 58, which are interconnected as shown in FIG.

Although the finite impulse response (FIR) digital low-pass filter shown in FIG. 17 has nine taps (signal stages), the second stage in FIG. Low pass characteristics as shown, for example, a pass band where the amplitude is 0 dB is 0 to 0.09 fs
, The stop band at which the amplitude is −60 dB or less is within the range of 0.16 to 0.5 fs, and the amplitude falling region between the pass band and the stop band is 0.09 to 0.
In order to obtain a characteristic within the range of 16 fs, 50 or more taps are required as the actual number of taps.

[0016]

The known quadrature frequency division multiplexing modulation circuit uses the interpolation order n of the finite impulse response digital low-pass filter used for the in-phase signal interpolator 45I and the quadrature signal interpolator 45Q. In the case of a large order such as 4, harmonics are generated over a wide band, and it is necessary to suppress the harmonics. Further, it is necessary to sharpen the cutoff characteristics of the finite impulse response digital low-pass filter according to the magnitude of the interpolation order.
A finite impulse response digital low-pass filter having such a wide bandwidth and a sharp cutoff characteristic has a tap number of 50 taps or more as described above, and a logic of a quadrature frequency division multiplex modulation circuit. The circuit scale of the circuit unit becomes large, and the power consumption of the orthogonal frequency division multiplex modulation circuit increases.

The present invention has been made in view of such a technical background, and has as its object to use a cascade-connected interpolator of interpolation order 2 as an interpolating means, and to provide the interpolator with an infinite impulse response digital full range. An object of the present invention is to provide a quadrature frequency division multiplexing modulation circuit that includes a pass filter so as to suppress generation of harmonics and prevent an increase in the circuit scale of a logic circuit unit.

[0018]

In order to achieve the above object, an orthogonal frequency division multiplexing modulation circuit according to the present invention converts a digital modulation signal to a plurality of subcarriers centered on a half of a sampling frequency. Inverse Fourier transform means for performing inverse Fourier transform by mapping and outputting a plurality of inverse Fourier transform signals, and a cascade connection for sequentially interpolating the plurality of inverse Fourier transform signals by an interpolation degree 2 for each of the in-phase signal and the quadrature signal And interpolating means comprising one or more interpolators, and orthogonal means for orthogonally modulating the inter-complementary signal and the orthogonal interpolation signal output from the interpolating means.

According to the first means, the interpolating means is formed by one or more interpolators interpolating at the interpolation order 2.
Since the waveform is interpolated by one or more interpolators so as to smoothly change the waveform between the sample signals temporally discrete,
In one or more interpolators, harmonics do not occur in a signal band centered on a frequency three times the center frequency of the modulation signal, and the generation of harmonics can be suppressed effectively.

In order to achieve the above object, an orthogonal frequency division multiplex modulation circuit according to the present invention maps a digitally modulated signal to a plurality of subcarriers centered on a half of a sampling frequency and performs inverse mapping. An inverse Fourier transform means for performing a Fourier transform and outputting a plurality of inverse Fourier transform signals, and one or more cascade connections for interpolating the plurality of inverse Fourier transform signals in order of an in-phase signal and a quadrature signal in order of interpolation order 2 And an orthogonal modulator for orthogonally modulating the inter-complementary signal and the orthogonal interpolation signal output from the interpolator. Each interpolator shifts the in-phase signal or the orthogonal signal by 90 °. The infinite impulse response digital all-pass filter and the quadrature signal or the in-phase signal are signal delays of the infinite impulse response digital all-pass filter. It comprises a second means and a digital delay circuit for delaying.

According to the second means, in addition to the function obtained by the first means, an infinite impulse response digital all-pass filter and its infinite Since a digital delay circuit that delays the signal by the signal delay of the impulse response digital all-pass filter is used, the number of tap stages of the infinite impulse response digital all-pass filter is determined by the finite impulse response used in the known interpolator. The number of tap stages of the digital low-pass filter can be significantly reduced, and an increase in power consumption of the orthogonal frequency division multiplex modulation circuit can be avoided without increasing the circuit scale of the logic circuit unit.

In this case, in the infinite impulse response digital all-pass filter in the second means, the signal processing section includes only an even-numbered signal processing section from the output side, and has a frequency of 動作 of the operating frequency. It is preferable to operate with.

According to this configuration, the number of taps of the infinite impulse response digital all-pass filter is compared with the number of taps of the signal processing unit used in the second means. The number of tap stages of the filter can be further reduced, the configuration of the infinite impulse response digital all-pass filter can be simplified, and the orthogonal frequency division multiplex modulation circuit can be used without increasing the circuit size of the logic circuit section. Power consumption can be reliably prevented from increasing.

[0024]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of an orthogonal frequency division multiplex modulation circuit according to the present invention, showing a main part of the circuit, in which two interpolators of interpolation order 2 are connected in cascade. This shows an example in which signal interpolation of interpolation order 4 is performed.

As shown in FIG. 1, the orthogonal frequency division multiplexing modulation circuit of the first embodiment includes a digital modulator 1
A serial-parallel converter (S / P) 2, an inverse Fourier transformer (IFFT) 3, a parallel-serial converter (P / S) 4, a first-stage interpolator 5, and a next-stage interpolator 6. ,
In-phase signal multiplier 7I, quadrature signal multiplier 7Q, local oscillator 8, 90 ° phase shifter 9, adder 10, digital-analog converter (D / A) 11, digital data input terminal 12 and an analog signal output terminal 13. Then, the in-phase signal multiplier 7I and the quadrature signal multiplier 7Q
The circuit portion including the local oscillator 8 and the 90 ° phase shifter 9 constitutes a quadrature modulation circuit (quadrature modulation means).

[0027] In this case, the first-stage interpolator 5, first infinite impulse response and (IIR) digital all pass filter (graphical symbol 90 °) 5 _1, first infinite impulse response digital whole constituting a 90 ° phase shifter the first digital delay device which gives the same signal delay as the signal delay-pass filter 5 ₁ (graphical symbol DL) 5 ₂ and, 90 ° second infinite impulse response digital all pass filter constituting the phase shifter (90 °)
5 _3, and the second digital delay device (DL) 5 ₄ give the same signal delay as the signal delay of the second infinite impulse response digital all pass filter 5 _3, 180 ° phase shifter (graphical symbol 180 °) 5 ₅ If consists of a first one-circuit two-contact switch 5 ₆ and the second one-circuit two-contact switch 5 _7. The next-stage interpolator 6 includes a first infinite impulse response (IIR) digital all-pass filter (90 °) 6 constituting a 90 ° phase shifter.
_1, a first digital delay device (DL) 6 ₂ give the same signal delay as the first infinite impulse response digital all pass filter ₆₁ of the signal delay, the constituting 90 ° phase shifter 2
Infinite impulse response digital all-pass filter (90
°) and 6 _3, the give the same signal delay as the signal delay of the second infinite impulse response digital all pass filter 6 ₃ 2
Digital delay device (DL) and 6 _4, 180 ° phase shifter (18
And 0 °) 6 _5, a first one-circuit two-contact switch 6 ₆ second
Consisting of one-circuit two-contact switch 6 ₇ for the.

The digital modulator 1 has an input connected to the digital data input terminal 12 and an output connected to the input of the serial-parallel converter 2. The inverse Fourier transformer 3 is
The input is connected to the output of the serial-parallel converter 2,
The output is connected to the input of the parallel-serial converter 4.

[0029] In the first stage interpolator 5, first infinite impulse response digital all pass filter 5 _1, input parallel - connected to the I output of the serial converter 4, the output is connected to one fixed contact of the switch 5 ₆ Is done. The first digital delay device 5 _2, input parallel - connected to the Q output of the serial converter 4, the output is connected to the other fixed contact of the switch 5 _6. The second infinite impulse response digital all pass filter 5 ₃ has an input parallel - connected to the Q output of the serial converter 4, the output is connected to an input of 180 ° phase shifter 5 _5. 180 ° phase shifter 5 ₅ output is connected to one fixed contact of the switch 5 _7. Second digital delay device 5 ₄ has an input parallel - serial converter 4 I
Connected to the output, the output is connected to the other fixed contact of the switch 5 _7. Further, in the next stage interpolator 6, first infinite impulse response digital all pass filter ₆₁ has an input connected to the movable contact of the switch 5 _7, and its output is connected to one fixed contact of the switch 6 _6. The first digital delay device 5 ₂ has an input connected to the movable contact of the switch 5 _6, the output is connected to the other fixed contact of the switch 5 _6. The second infinite impulse response digital all pass filter 5 ₃ has an input connected to the movable contact of the switch 5 _6,
An output connected to an input of 180 ° phase shifter 6 _5. 180
° phase shifter 6 _5, and its output is connected to one fixed contact of the switch 6 _7. Second digital delay device 6 ₄ has an input connected to the movable contact of the switch 5 _7, the output is connected to the other fixed contact of the switch 6 _7.

The in-phase signal multiplier. 7I, first input connected to the movable contact of the switch 6 _7, the second input is the local oscillator 8
, And the output is connected to the first input of the adder 10. The quadrature signal multiplier 7Q has a first input
₆ is connected to the movable contact of the second input connected to the output of the 90 ° phase shifter 9, the output is connected to a second input of the adder 10. The 90 ° phase shifter 9 has an input connected to the output of the local oscillator 8. The output of the adder 10 is connected to the input of the digital-analog converter 11. The output of the digital-analog converter 11 is connected to the analog signal output terminal 13.

Next, FIG. 2 is a signal waveform (frequency spectrum) diagram obtained in each section of the orthogonal frequency division multiplex modulation circuit shown in FIG.

The operation of the orthogonal frequency division multiplexing modulation circuit of the first embodiment having the above configuration will be described with reference to the signal waveform diagram shown in FIG.

When digital data output from a data source (not shown) is applied to a digital data input terminal 12, the digital data is applied to the digital modulator 1
Supplied to The digital modulator 1 performs digital modulation such as four-phase phase shift keying (QPSK) on the supplied digital data at a sampling frequency fs ′, and outputs an in-phase digital modulation signal (I) having the same phase as input digital data from its I output. And outputs a quadrature digital modulation signal (Q) having a phase difference of 90 ° with the input digital data from the Q output. Next, the in-phase digital modulation signal and the quadrature digital modulation signal are subjected to serial-parallel conversion in the serial-parallel converter 2 and supplied to the inverse Fourier transformer 3 as an in-phase parallel signal and a quadrature parallel signal, respectively. The inverse Fourier transformer 3 maps the supplied in-phase parallel signal and quadrature parallel signal to a plurality of subcarriers, and also adds a plurality of null (0) subcarriers. Inverse Fourier transform is performed, and N in-phase inverse Fourier transform signals and orthogonal inverse Fourier transform signals are output. Next, the N in-phase inverse Fourier transform signals and the quadrature inverse Fourier transform signals are subjected to parallel-serial conversion in the parallel-serial converter 4, respectively, and the center frequency is the first of the sampling frequency fs in FIG.
An in-phase serial signal and a quadrature serial signal (modulated signal) having a signal spectrum as shown at the top are output.
The in-phase serial signal and the quadrature serial signal are supplied to the first-stage interpolator 5.
Supplied to

The first-stage interpolator 5 has a sampling frequency fs
In-phase serial signal and quadrature serial signal (modulated signal)
, And performs signal interpolation on the in-phase serial signal and the quadrature serial signal, outputs an in-phase serial interpolation signal and a quadrature serial interpolation signal having a frequency 2fs which is twice the sampling frequency fs, and is supplied to the next-stage interpolator 6. You. At this time, in the first-stage interpolator 5, signal interpolation is performed so that the signal change becomes smooth. Therefore, as shown by the waveform of the frequency spectrum F shown in FIG. , No harmonics are generated in a frequency band centered at a frequency of 1.5 fs.

Next, when the in-phase serial signal and the quadrature serial signal having the sampling frequency of 2 fs are supplied, the next-stage interpolator 6 performs signal interpolation on the in-phase serial signal and the quadrature serial signal, and outputs the sampling frequency of 2 fs.
And outputs an in-phase serial interpolation signal and a quadrature serial interpolation signal having a frequency of 4 fs, which are twice as high as the above, and are supplied to the in-phase signal multiplier 7I and the quadrature signal multiplier 7Q. Also at this time, in the next-stage interpolator 6, signal interpolation is performed so that the signal change becomes smooth, so that the frequency spectrum G shown in FIG.
As shown in the waveform of FIG.
Even if the output is performed at the double frequency of 4 fs, no harmonic is generated in the frequency band centered on the frequency of 2.5 fs.

Next, the in-phase signal multiplier 7I multiplies the in-phase serial interpolation signal having a sampling frequency of 4fs by the in-phase signal having a frequency fs / 2 which is half the sampling frequency fs. The orthogonal signal multiplier 7Q multiplies the orthogonal serial interpolation signal having a sampling frequency of 4fs by an orthogonal signal having a frequency fs / 2, which is half the sampling frequency fs. As a result of this multiplication, the in-phase serial interpolation signal and the quadrature serial interpolation signal have a frequency fs in which the center frequency of the OFDM modulation signal is shifted to a higher frequency side by fs / 2,
It is output at a sampling frequency of 4 fs.

Subsequently, the adder 10 adds the obtained in-phase serial interpolation signal and quadrature serial interpolation signal, and outputs the added serial interpolation signal to the digital-analog converter 11.
Supplied to The digital-analog converter 11 converts the added serial interpolation signal into an analog signal and supplies the analog signal to an analog signal output terminal 13. As a result, the analog signal output terminal 13 outputs a serial interpolation signal having a signal component that has been subjected to OFDM modulation and signal interpolation of degree 4.

Next, the first-stage interpolator 5, the first infinite impulse response digital all pass filter 5 ₁ constituting the 90 ° phase shifter, a first digital delay unit 5 _2, the first one-circuit two contact the switch 5 _6, the interpolation signal to the quadrature serial signals, that is, the operation history of generating quadrature serial interpolation signal will be described.

As is well known, a quadrature modulated signal has a phase delay of 90 ° with respect to an in-phase modulated signal. Therefore, if the phase of the in-phase modulated signal is delayed by 90 °, the signal becomes The phase is the same as that of the quadrature modulation signal. Therefore, in this first embodiment, it delays the phase by 90 ° by passing the in-phase serial signal a first infinite impulse response digital all pass filter 5 _1, at the same time, a quadrature serial signal first digital delay device 5 ₂ the first infinite impulse response digital all pass filter 5 ₁
The in-phase serial signal is in the same phase state as the quadrature serial signal by delaying by the group delay time generated in step (1). At this time, if the first infinite impulse response digital all pass filter 5 ₁ to the configuration as described below, the first infinite impulse response digital all pass filter 5 ₁
Is output from the first digital delay unit 5
Producing a signal subjected to time interpolation of the serial signal output from the _2, the output signal of the first infinite impulse response digital all pass filter 5 ₁ and the first output signal of the digital delay unit 5 ₂ to the signal of the sampling frequency fs Become. Supplying these signals to the first one-circuit two-contact switch 5 _6, twice the the movable contact sampling frequency fs frequency 2
When switched fs, quadrature serial interpolation signal interpolated from the first one-circuit two-contact switch 5 ₆ degree 2 is output.

[0040] Then, in the first-stage interpolator 5, the second infinite impulse response digital all pass filter 5 ₃ constituting the 90 ° phase shifter, a second digital delay device 5 _4, 18
A 0 ° phase shifter 5 _5, by a second one-circuit two-contact switch 5 _7, interpolation signals for the in-phase serial signals, that is, the operation history to obtain an in-phase serial interpolation signal will be described.

As is well known, the in-phase modulation signal is a signal having a phase lead of 90 ° with respect to the quadrature modulation signal and a signal having a phase delay of 270 ° with respect to the quadrature modulation signal. Therefore, the phase of the in-phase modulated signal is 2
If delayed by 70 °, the in-phase modulated signal will be in the same phase state as the quadrature modulated signal. Therefore, this in the first embodiment, the passage of the quadrature serial signal second infinite impulse response digital all pass filter 5 ₃ 90
° only delay the phase, further, 270 in total delays the phase by 180 ° by passing through a 180 ° phase shifter 5 ₅
° The phase is delayed. Note that delaying the phase 180 ° are the equivalent to inverting the signal polarity (sign), the 180 ° phase shifter 5 _5, be constituted by an inverter for inverting the polarity (sign) of the digital signal Is possible.

On the other hand, for the in-phase serial signal, the second
Only the group delay time period which through a digital delay device 5 ₄ occurs in the second infinite impulse response digital all pass filter 5 ₃ delays, and a phase serial signal in phase state and quadrature serial signal. At this time, if the second infinite impulse response digital all pass filter 5 ₃ to the configuration as described later, the serial signal outputted from the second infinite impulse response digital all pass filter 5 _3, second digital delay output from the vessel 5 ₄ would signal subjected to time interpolation of the serial signal. Supplying these signals to the second one-circuit two-contact switch 5 _7, when switches its movable contact at a frequency twice 2fs of the sampling frequency fs,
Phase serial interpolation signal interpolated from the second one-circuit two-contact switch 5 ₇ degree 2 is output.

As described above, the first-stage interpolator 5 outputs the in-phase serial interpolation signal and the quadrature serial interpolation signal interpolated by the interpolation order 2.

Thereafter, the operation of the next-stage interpolator 6 is such that the sampling frequency is equal to the sampling frequency f of the first-stage interpolator 5.
The other operation is the same as the operation of the first-stage interpolator 5, except that the frequency is 2fs, which is twice the frequency s. Therefore, the operation of the next-stage interpolator 6 will not be described further.

FIG. 3 is a circuit diagram showing an example of a specific configuration of the infinite impulse response digital all-pass filter shown in FIG. 1. FIG. 4 is a diagram showing the phase of the infinite impulse response digital all-pass filter. FIG. 9 is an explanatory diagram for explaining a change state of the slash. FIG. 5 is a characteristic diagram showing a phase change state when the number of phase gradients generated in the frequency pass band is changed in the infinite impulse response digital all-pass filter, and FIG. 6 is shown in FIG. FIG. 7 is a characteristic diagram showing a change state of a phase difference in a frequency pass band in an infinite impulse response digital all-pass filter. FIG. 7 is a characteristic diagram showing a change state of the group delay when the number of phase gradients is used as a parameter in the infinite impulse response digital all-pass filter. FIG. 7 is a table showing an example of coefficient values set in a multiplication coefficient generator when the number of phase gradients to be performed and the number of tap stages in a signal processing stage are determined. FIG. 9 is a table showing the coefficient values set in the multiplication coefficient generator when the number obtained by adding 1 to the number of phase gradients is used as the number of coefficients. FIG. 10 shows a specific example of the infinite impulse response digital all-pass filter in which the odd-numbered tap stages are omitted from the infinite impulse response digital all-pass filter shown in FIG. 3 when the phase gradient m has m + 1 coefficients. FIG. 3 is a circuit diagram showing an example of a dynamic configuration together with a thinning unit.

The infinite impulse response digital all-pass filter used in the 90 ° phase shifters 5 ₁ , 5 ₃ , 6 ₁ , 6 ₃ of the present invention will be described with reference to FIGS.

As shown in FIG. 3, this infinite impulse
The response digital filter 14 has an input terminal Sin and an output terminal.
Input terminal S from the output terminal Sout and the output terminal Sout side.
Eight tap stages 14 connected in order to the in side₁Or 1
4₈And the common adder 14₉And in this case,
Each tap stage 14₁To 14₈Are the first delay units, respectively.
14₁₁To 14₈₁And the second delay unit 14₁₂To 14₈₂When,
Adder 14₁₃To 14 ₈₃And the multiplier 14₁₄To 14
₈₄And the multiplication coefficient generator 14₁₅To 14₈₅Consisting of
Tap stage 14₁To 14₈At the first
Extension 14₁₁To 14 ₈₁, The second delay unit 14₁₂To 14₈₂,
Adder 14₁₃To 14₈₃, Multiplier 14₁₄To 14₈₄, Squared
Arithmetic coefficient generator 14₁₅To 14₈₅Is illustrated in FIG.
Interconnected.

Next, FIG. 4 shows a change state of the output phase of the infinite impulse response digital all-pass filter 14 together with a change state of the output phase of the digital signal delay unit.

In FIG. 4, the vertical axis represents the phase, the horizontal axis represents the frequency, the solid line represents the change of the phase of the infinite impulse response digital all-pass filter 14, and the dashed line represents the change of the phase of the digital signal delay unit. It is.

As shown in FIG. 4, in a signal band (range indicated by a dotted line) centered on a frequency fs / 4 which is 1/4 of the sampling frequency fs, the phase change state of the digital signal delayer is determined by the signal The phase value changes linearly from the lower limit frequency value to the upper limit frequency value of the band, and when the phase value reaches -2π, the phase value jumps to 0, and the phase value linearly increases again toward the upper limit frequency value. Changes to
On the other hand, the infinite impulse response digital filter 14
Changes from the lower limit frequency value to the upper limit frequency value of the signal band, the phase value changes linearly with the same phase gradient as that of the digital signal delay circuit, and when the phase value reaches -2π, the phase value becomes zero. And the phase value changes linearly again toward the upper limit frequency value. The phase difference between the phase value of the infinite impulse response digital all-pass filter 14 and the phase value of the digital signal delay device is as follows: -(Π / 2), that is, -90 °, is always maintained in the signal band.

In this case, the phase gradient represents the ratio of the phase change to the frequency change, and is defined by the number of times a phase change occurs every −2π between the frequency 0 and fs. For example, if the accumulated phase between the frequencies 0 and fs is −6π, the phase gradient is 3.

The phase gradient is also defined as a group delay time by its definition, and is a delay time in units of a sampling time. For example, if the phase gradient is 3, the group delay is 3 clocks.

Next, FIG. 5 shows a phase change state when the number of phase gradients generated in a frequency band is changed in the infinite impulse response digital all-pass filter 14.

In FIG. 5, the vertical axis represents the phase in degrees (deg), and the horizontal axis represents the frequency (2) in radians (rad).
π radians corresponds to the sampling frequency),
The solid line indicates the phase change when the number of phase gradients of the infinite impulse response digital filter 14 is 5, and the dotted line indicates the phase change when the number of phase gradients of the infinite impulse response digital all-pass filter 14 is 7. .

As shown in FIG. 5, an infinite impulse response
Each first delay constituting the digital all-pass filter 14
Extension 14₁₁To 14₈₁And the second delay unit 14₁₂To 14₈₂
The delay constant z of^-1, Each multiplication coefficient generator 14₁₅No
To 14₈₅Each coefficient C ₁Or C₈Select as appropriate
Infinite impulse response digital all-pass
The changing state of the phase of the filter 14 depends on the frequency of the digital signal.
Substantially linear state within the band (0.1π to 0.9π radian)
And the phase gradient over the entire frequency band (0 to 2π radians)
The change state is such that the number of arrangements is 5 or 7.

FIG. 6 shows a change in the phase difference representing the difference between the phase of the infinite impulse response digital all-pass filter 14 and the phase of the digital signal delay unit within the signal band of the infinite impulse response digital all-pass filter 14. It is a characteristic view showing a state.

In FIG. 6, the vertical axis represents the phase difference expressed in degrees (deg), the horizontal axis represents the frequency expressed in radians (rad), and curve A represents the number of phase gradients of the infinite impulse response digital all-pass filter 14. Is the change state of the phase difference when is set to 5, and the curve B is the change state of the phase difference when the number of phase gradients of the infinite impulse response digital all-pass filter is set to 7.

As shown by the curves A and B shown in FIG. 6, the frequency band of the digital signal (from 0.1π to 0.
Within 9π radians), the infinite impulse response digital all-pass filter 14 has five or seven phase difference changing portions, but their phase differences fall within a range near −90 °.

FIG. 7 is a characteristic diagram showing a change state of the group delay in the infinite impulse response digital all-pass filter 14 when the number of phase gradients is used as a parameter.

In FIG. 7, the vertical axis represents the number of samples (sam
ple), and the horizontal axis represents the frequency expressed in radians (rad). Curves A3 to A8 are obtained when the number of phase gradients of the infinite impulse response digital all-pass filter 14 is 3 to 8, respectively. Is a change state of the group delay.

As shown by the curves A3 to A8 shown in FIG. 7, the group delay of the infinite impulse response digital all-pass filter 14 in the frequency band (0.1π to 0.9π radian) of the digital signal. The change state is
Although the change state gradually decreases as the number of phase gradients increases from 3 to 8, the change state is generally within a limited range.

Infinite impulse response having such characteristics
As the digital all-pass filter 14, its phase gradient
The first delay unit 14 is set so that the number becomes, for example, three or more.₁₁Or
14 ₈₁And the second delay unit 14₁₂To 14₈₂Each slow
Extension constant z^-1, Each multiplication coefficient generator 14₁₅To 14₈₅That of
Each coefficient C₁Or C₈If you select
Infinite impulse response digital within the frequency band of the signal
Quadrature (Q) signal output from all-pass filter 14
And the in-phase (I) signal output from the digital signal delay
Can be made almost 90 °, and the quadrature (Q) signal
The signal and the in-phase (I) signal have almost the same group delay.

FIG. 8 is a table showing an example of coefficient values set in the multiplication coefficient generator when the number of generated phase gradients and the number of tap stages are determined in the infinite impulse response digital all-pass filter 14. It is a table.

In FIG. 8, the leftmost column is the number of phase gradients.
(Indicated as phase gradient in the table), the next column is the tap stage
Number (shown as the number of coefficients in the table), the next column is the power
The coefficient values set in the arithmetic coefficient generator (in the table, the multiplication factor shown in FIG. 2)
Coefficient C shown in number generator ₁, C_Two………, C₈When
9 and 10 not shown and not shown in FIG.
The coefficient of each multiplication coefficient generator of the th tap stage is C₉, C_Ten
Is written).

As shown in FIG. 8, in the configuration example at the uppermost stage, when the phase gradient is 4 and the number of coefficients is 5, the coefficient C ₁ is 2.5 × 10 ⁻⁷ and the coefficient C ₂ is −0. .4 × 10 ⁻¹ , coefficient C ₃ to −9.1 × 10 ⁻⁷ , coefficient C ₄ to −9.3 × 1
The coefficient C ₅ is set to −3.2 × 10 ⁻⁶ , respectively, at 0 ⁻² . Similarly, in the configuration of the second and subsequent stages, the phase gradient, depending on the number of coefficients, each coefficient C ₁ to C ₁₀ number that matches the number of coefficients is set to a value shown respectively.

Incidentally, each coefficient C shown in FIG.₁Or
C_TenLooking at the coefficient values of, the phase gradient is 4 and the number of coefficients is 5.
When the phase gradient is 6 and the number of coefficients is 7, the phase gradient is
In each of the cases where the coefficient number is 9 and the odd number is 8,
Coefficient C₁, C_Three, C_Five, C ₇, C₉Is the exponent
Is 10 including^-6, 10^-7, 10^-8, 10^-9So
And each coefficient including these numbers when the effective digit is 5 digits
The value will be substantially zero.

FIG. 9 is a table showing the coefficient values set in the multiplication coefficient generator when the number of coefficients is obtained by adding 1 to the number of phase gradients shown in FIG.

In FIG. 9, the leftmost column is the phase gradient,
The number of the next column is the coefficient, the next column is the coefficient C _1, C _2, ...
..., a C _9, between the number of phase slope and the coefficient, the phase gradient when it is m, the coefficient C ₁ of the combination number of coefficients is _{m + 1, C 2, ......} , a C ₉ It shows a coefficient value.

As shown in FIG. 9, when the phase gradient is m,
A combination in which the number of coefficients is one more m + 1,
In the case where the phase gradient is 2 to 8 and the number of the corresponding coefficients is 3 to 9, the odd-numbered coefficients C ₁ , C ₃ , C
_5, C _7, any of the coefficient values of C ₉ also figures 10 ^-5 including exponential, ^{10-6, 10-7, 10-8,} a 10 ^-9, each coefficient values including these numerical values Becomes substantially zero.

The relationship between the phase gradient and the number of coefficients
Therefore, if the coefficient of the multiplication coefficient generator becomes 0,
Multiplication by the coefficient 0 output from the multiplication coefficient generator of
Multiplier output data becomes 0 and input to multiplier
The output data of the adder is also unnecessary, and the coefficient becomes zero.
Tap stage having a multiplication coefficient generator, ie, a point shown in FIG.
Odd-numbered tap stage 14 indicated by line₁, 14
_Three, 14_Five, 14₇Etc., respectively, adder 1
4₁₃, 14₃₃, 14₅₃, 14₇₃Multiplier 14 ₁₄, 14
₃₄, 14₅₄, 14₇₄Multiplication coefficient generator 14₁₅, 1
4₃₅, 14₅₅, 14 ₇₅It is not necessary to provide
It can be omitted.

Here, FIG. 10 shows that when the phase gradient is m and the number of coefficients is m + 1, the odd-numbered tap stages 14 ₁ , 14 ₁ in the infinite impulse response digital all-pass filter 14 shown in FIG. Adders 14 ₁₃ , 14 ₃₃ , 14 ₅₃ , 14 _{73 of} 14 ₃ , 14 ₅ , 14 ₇ , a multiplier 14 ₁₄ ,
14 ₃₄ , 14 ₅₄ , 14 ₇₄ and multiplication coefficient generators 14 ₁₅ , 1
The infinite impulse response digital all-band-pass filter 14 'in which 4 ₃₅ , 14 ₅₅ , and 14 ₇₅ are omitted, and the common adder 1
4 ₉ a thinning unit 15 inserted between the output terminal Sout
FIG. 9 is a circuit diagram showing an example of a configuration of an infinite impulse response digital all-band pass filter configured using the above.

The decimation section 15 shown in FIG.
In this method, every other data supplied from the infinite impulse response digital all-band-pass filter 14 'is decimated, and output data at a data rate of 1/2 is supplied to the output terminal Sout. At this time, each coefficient value C of the multiplication coefficient generators 14 ₂₅ , 14 ₄₅ , 1 ₆₅ , and 1 _85
2 , C ₄ , C ₆ and C ₈ are respectively C ₂ = −4.8 ×
10 ⁻¹ , C ₄ = −1.0 × 10 ⁻¹ , C ₆ = −3.6 × 1
0 ^-2 and C ₈ = -1.3 × 10 ^-2 . In this case, if the sampling frequency of the infinite impulse response digital all-bandpass filter 14 'is fi, the frequency band is 0.05 to 0.45fi, and the phase ripple within the frequency band is within ± 1.5 °. It has a frequency characteristic that falls within the range.

An infinite impulse response digital all-bandpass filter 14 'having a thinning section 15 shown in FIG.
The phase characteristic and the group delay characteristic at the input end of the thinning unit 15 are the same as the characteristics shown in FIGS. That is, the infinite impulse response digital all-bandpass filter 14 'has its sampling frequency (data rate) f
It has a predetermined phase / group delay characteristic in a pass band around a frequency fi / 4 which is 1/4 of i. When the data passes through the thinning section 15, the output terminal Sou
The sampling frequency (data rate) fo of t is の of the sampling frequency (data rate) fi of the infinite impulse response digital all-pass filter 14 ′.
Since i / 2 (= fo), the above-mentioned characteristics are converted in terms of data rate and become characteristics in a pass band centered on fo / 2. However, when fi is considered as a reference, centered on fi / 4. It has the characteristics.

As described above, the infinite in-line shown in FIG.
Pulse response digital all-pass filter shown in Figure 1
Digital infinite impulse response digital all-pass filter
TA5 ₁, 5_Three, 6₁, 6_ThreeIt is suitable for use in

By the way, since the sampling frequency (data rate) of the infinite impulse response digital all-band-pass filters 5 ₁ and 5 ₃ shown in FIG. 1 is fs, the infinite impulse response digital all band-pass filter 5 ₁ shown in FIG. In the band-pass filter 14 ′, the sampling frequency (data rate) f ₀ of the thinning unit 15 is fs, and except for the thinning unit 15, the sampling frequency (data rate) is twice the sampling frequency (data rate) (fi = 2 fs). . In addition, since the sampling frequency (data rate) of the infinite impulse response digital all-pass filters 6 ₁ and 6 ₃ shown in FIG. 1 is 2 fs, the infinite impulse response digital all-band filter shown in FIG. At 14 ′, the sampling frequency (data rate) f ₀ of the thinning unit 15 becomes 2fs, and the thinning unit 15
The operation is performed at a sampling frequency (data rate) twice as large as that of 4 fs (fi = 2 fs).

FIG. 11 is a circuit diagram showing another example of the configuration of the infinite impulse response digital all-band-pass filter 14 ″ together with the infinite impulse response digital all-band-pass filter 14 ′ shown in FIG. each infinite impulse response digital all-pass filter 5 ₁ illustrated in FIG. 1, 5 _3, 6 _1, 6 used in ₃ is suitable.

The infinite impulse response data shown in FIG.
The digital all-pass filter 14 "is illustrated in FIG.
Infinite impulse response digital all-pass filter
In addition to omitting the thinning unit 15 that has been used, FIG.
Illustrated infinite impulse response digital all-bandpass filter
Odd-numbered tap stage 14 of luta 14₁, 14_Three, 1
4 _Five, 14₇Are all omitted. Soshi
This infinite impulse response digital all bandpass filter
FIG. 1 shows the sampling frequency (data rate) of the
Infinite impulse response digital all-pass illustrated at 0
Sampling at output terminal Sout of filter 14 '
The same frequency as the data frequency (data rate), that is, FIG.
Infinite impulse response digital all-pass illustrated at 0
Sampling frequency (data rate) of filter 14 '
Are operated at half the frequency of

The infinite impulse response digital all-pass filter 14 ″ shown in FIG. 11 is replaced with the infinite impulse response digital all-pass filter 5 ₁ shown in FIG.
When used in 5 _3, the output sampling frequency (data rate). Therefore fs, infinite impulse response digital sampling frequency of the all-pass filter 14 "(data rate) fi also operate with fs (fi = fs). Also, the infinite impulse response digital all-pass filter 14 ″ shown in FIG. 11 is replaced with the infinite impulse response digital all-pass filter 6 ₁ , 6 shown in FIG.
_When used for ₃ , the output sampling frequency (data rate) becomes 2 fs, so that the sampling frequency (data rate) fi of the infinite impulse response digital all-bandpass filter 14 ″ is also operated at 2fs (fi = 2fs).

Here, when comparing the infinite impulse response digital all-pass filter 14 shown in FIG. 3 with the infinite impulse response digital all-pass filter 14 ′ shown in FIG. The latter is
Since the number of circuit elements is reduced, and the sampling frequency of the infinite impulse response digital all-band-pass filter 14 'is half that of the infinite impulse response digital all-band-pass filter 14, lower power consumption can be achieved. The same applies to the infinite impulse response digital all-bandpass filter 14 "shown in FIG.

As described above, according to the orthogonal frequency division multiplexing modulation circuit of the first embodiment, the first and second infinite impulse response digital all-pass filters 5 are used as interpolators.
Performing signal interpolation of interpolation order 4 using a first-stage interpolator 5 having ₁ , 5 and ₃ and a second-stage interpolator 6 having first and second infinite impulse response digital all-pass filters 6 ₁ and 6 _3. Can be. And these infinite impulse response digital all-pass filters 5 ₁ , 5 ₃ , 6 ₁ , 6 ₃
Since the number of tap stages is only about 4 tap stages, the circuit scale of the logic circuit section can be significantly reduced as a whole compared with the known logic circuit section, and the orthogonal frequency division The power consumption of the multiplex modulation circuit can be greatly reduced as compared with the known one.

Incidentally, in the first embodiment,
The first and second stages used in the first stage interpolator 5 and the next stage interpolator 6
2 infinite impulse response digital all-pass filter
5₁, 5 _Three, 6₁, 6_ThreeAs the number of taps (signal stages)
Has been described using an example using a four-tap stage.
First and second infinite impulse response digital used in the invention
Tall all-pass filter 5₁, 5_Three, 6₁, 6_ThreeTouch
The number of steps is not limited to 4 taps.
And second infinite impulse response digital all-pass filter
5₁, 5_Three, 6₁, 6_ThreePhase characteristics required in
The number of tap stages can be changed as appropriate.

For example, the first and second infinite impulse response digital all-pass filters 5 ₁ , 5 ₃ , 6 ₁ , 6 ₃ have a frequency band of 0.05 to 0.45 fs.
If it is necessary to have a frequency selection characteristic having a phase ripple within ± 0.5 ° within the frequency band, the number of tap stages is set to five, and the coefficients C ₂ , C ₄ ,
C ₆ , C ₈ , C ₁₀ are, for example, C ₂ = −4.9 × 1
0 ⁻¹ , C ₄ = −1.1 × 10 ⁻¹ , C ₆ = −4.0 × 10
⁻² , C ₈ = −1.7 × 10 ⁻² , C ₁₀ = −6.1 × 10 ⁻³
Set to.

On the other hand, the first and second infinite impulse
Response digital all-pass filter 5₁, 5_Three, 6₁,
6_ThreeAs a result, the frequency band is slightly narrower from 0.1 to 0.1.
4 fs, and the phase ripple in the frequency band is ± 1.
When it is sufficient to have a frequency selection characteristic within 5 °
Sets the number of tap stages to three and sets each coefficient C
_Two, C_Four, C₆For example, C_Two= −4.6 × 10^-1,
C_Four= −7.1 × 10 ^-2, C₆= −1.3 × 10^-2Set in
It should be set.

Next, FIG. 12 shows a second embodiment of the orthogonal frequency division multiplex modulation circuit according to the present invention, and is a block diagram showing a main part of the circuit. This shows an example in which the frequency interpolation of the interpolation order 8 is performed by using the frequency interpolation.

As shown in FIG. 12, in the second embodiment, another next-stage interpolator 15 is connected between the next-stage interpolator 6 and the quadrature modulation circuit in the first embodiment. The oscillation frequency of the local oscillator 9 in the quadrature modulation circuit is 3 fs / 2
It has been changed to.

In this case, another next-stage interpolator 15 outputs 90 °
First infinite impulse response (IIR) digital all-pass filter (illustrated symbol 90 °) constituting a phase shifter 15
_1, the first digital delay device which gives the same signal delay as the first infinite impulse response signal delay of the digital all pass filter 15 ₁ and (graphical symbol DL) 15 _2, second infinite impulse constituting the 90 ° phase shifter and response digital all pass filter (90 °) 15 _3, a second infinite impulse response digital all pass filter 15 ₃ second digital delay device which gives the same signal delay as the signal delay (DL) 15 _4, 1
80 ° phase shifter (the graphical symbol 180 °) 15 _5, first 1
The circuit two-contact switch 15 ₆ has the second one-circuit two-contact switch 15 _7. The connection state of these components 15 ₁ to 15 ₇ are identical to the connection state of the corresponding components 6 ₁ to 6 ₇ to the next stage interpolator 6.
In FIG. 12, the same reference numerals are given to the same components as those shown in FIG.

FIG. 13 is a signal waveform (frequency spectrum) diagram obtained at the output circuit portion of the orthogonal frequency division multiplex modulation circuit shown in FIG.

The operation of another interpolator 15 in the second embodiment is basically such that the sampling frequency is 4 fs, which is twice the sampling frequency 2 fs of the interpolator 6. The other operation is the same as the operation of the next-stage interpolator 6 except that That is, when an in-phase serial signal and a quadrature serial signal having a sampling frequency of 2 fs are supplied, signal interpolation is performed on the in-phase serial signal and the quadrature serial signal, and an in-phase serial interpolated signal having a frequency of 4 fs twice as high as the sampling frequency of 2 fs. The quadrature serial interpolation signal is output and supplied to the in-phase signal multiplier 7I and the quadrature signal multiplier 7Q.
Also at this time, in another next-stage interpolator 15,
Since signal interpolation is performed so that the signal change becomes smooth, as shown in the waveform of the frequency spectrum I shown in FIG. 13, the frequency 8 which is eight times the sampling frequency fs is used.
Even if output at fs, no harmonics are generated in the frequency band centered at the frequency 4.5 fs.

Next, the in-phase signal multiplier 7I multiplies the in-phase serial interpolation signal of the sampling frequency 8fs by the in-phase signal of the frequency 3fs / 2, which is 3/2 times the sampling frequency fs. Similarly, the quadrature signal multiplier 7Q
A quadrature serial interpolation signal with a sampling frequency of 8 fs,
Frequency 3fs / 2, which is 3/2 times the sampling frequency fs
Is multiplied by the orthogonal signal. As a result of this multiplication, the in-phase serial interpolation signal and the quadrature serial interpolation signal become OF OF waves as shown in the waveform of the frequency spectrum J shown in FIG.
The center frequency of the DM modulation signal is shifted to a higher frequency side by 3 fs / 2, and becomes 2 fs, which is output at a sampling frequency of 4 fs.

The operations of the components other than the above components in the second embodiment are the same as the operations of the corresponding components in the first embodiment. A further description of the operation is omitted. The operation and effect obtained by the second embodiment are almost the same as the operation and effect obtained by the first embodiment. Therefore, further description of the operation and effect of the second embodiment is omitted.

FIG. 14 shows a third embodiment of the orthogonal frequency division multiplexing modulation circuit according to the present invention, and is a block diagram showing a main part of the circuit, in which one interpolator of interpolation order 2 is provided. This shows an example in which the frequency interpolation of the interpolation order 2 is performed by using this.

In FIG. 14, the same components as those shown in FIG. 1 are denoted by the same reference numerals.

The third embodiment uses only the pre-stage interpolator 5 as interpolation means. The operation of the pre-stage interpolator 5 is basically the same as that of the first-stage interpolator according to the first embodiment. 5 is the same as the operation of FIG. That is, the in-phase serial signal and the quadrature serial signal (modulation signal) having the sampling frequency fs are input to the pre-stage interpolator 5, and the interpolator 5 performs signal interpolation on the in-phase serial signal and the quadrature serial signal to obtain a signal having twice the sampling frequency fs. An in-phase serial interpolation signal and a quadrature serial interpolation signal having a frequency of 2 fs are output and supplied to the next-stage interpolator 6. At this time, the first-stage interpolator 5 performs signal interpolation such that the signal change becomes smooth.
As shown in the waveform of the frequency spectrum F shown in FIG. 2, even when output at a frequency of 2 fs, which is twice the sampling frequency fs, no harmonic is generated in a frequency band centered at a frequency of 1.5 fs.

Thereafter, the in-phase signal multiplier 7I multiplies the in-phase serial interpolation signal having the sampling frequency 2fs by the in-phase signal having the frequency fs / 2 which is half the sampling frequency fs. The orthogonal signal multiplier 7Q multiplies the orthogonal serial interpolation signal having the sampling frequency 2fs by the orthogonal signal having the frequency fs / 2 which is half the sampling frequency fs. As a result of this multiplication, the in-phase serial interpolation signal and the quadrature serial interpolation signal have a frequency fs in which the center frequency of the OFDM modulation signal is shifted to a higher frequency side by fs / 2,
It is output at a sampling frequency of 2 fs.

The adder 10 adds the obtained in-phase serial interpolation signal and quadrature serial interpolation signal, and the digital-analog converter 11 converts the added serial interpolation signal into an analog signal and supplies it to the analog signal output terminal 13. .
As a result, the OFDM signal is output from the analog signal output terminal 13.
A serial interpolated signal having a modulated signal component and interpolated by degree 2 is output.

In the first to third embodiments, an example has been described in which the signal interpolation of the interpolation order 4, the signal interpolation of the interpolation order 8, and the signal interpolation of the interpolation order 2 are performed. The interpolation order of the signal interpolation according to the present invention is not limited to the case of 4, 8, and 2, but the signal interpolation of the interpolation order of 2 ^N (2, 4, 8, 16,...). In this case, the number of interpolators to be cascaded may be selected according to the interpolation order.

[0097]

As described above, according to the first aspect of the present invention, the interpolating means is formed by one or more interpolators interpolating at the interpolation order 2, and is temporally controlled by one or more interpolators. Is interpolated so that the waveform changes smoothly between the sampled signals, and a harmonic is generated in a signal band centered on a frequency three times the center frequency of the modulated signal in one or more interpolators. Therefore, there is an effect that generation of harmonics can be effectively suppressed.

According to the second aspect of the present invention, in addition to the effect obtained by the first aspect of the present invention, one or more interpolators that interpolate at the interpolation order 2 provide an infinite impulse response digital full range. Since a pass filter and a digital delay circuit that delays the signal by the signal delay of the infinite impulse response digital all-pass filter are used, the number of tap stages of the infinite impulse response digital all-pass filter is determined by a known interpolator. The number of tap stages of the finite impulse response digital low-pass filter used can be significantly reduced, and the power consumption of the orthogonal frequency division multiplex modulation circuit can be increased without increasing the circuit scale of the logic circuit section. There is an effect that can be avoided.

According to the sixth and seventh aspects of the present invention, in addition to the effects obtained by the second aspect, the number of tap stages of the infinite impulse response digital all-pass filter is set to the second aspect. Compared with the number of tap stages of the signal processing unit used in the described invention, the number of tap stages of the finite impulse response digital low-pass filter can be further reduced, and the configuration of the infinite impulse response digital all-pass filter is more improved. In addition to the simplification, there is an effect that the power consumption of the orthogonal frequency division multiplex modulation circuit can be reliably prevented from increasing without increasing the circuit scale of the logic circuit unit.

[Brief description of the drawings]

FIG. 1 is a first embodiment of an orthogonal frequency division multiplex modulation circuit according to the present invention, and is a block diagram illustrating a main configuration thereof.

FIG. 2 is a signal waveform diagram obtained in each section of the orthogonal frequency division multiplex modulation circuit shown in FIG.

FIG. 3 is a circuit diagram showing an example of a specific configuration of an infinite impulse response digital filter.

FIG. 4 is an explanatory diagram for explaining a change state of a phase of an infinite impulse response digital filter.

FIG. 5 is a characteristic diagram showing a phase change state when the number of phase gradients generated in the frequency pass band is changed in the infinite impulse response digital filter.

6 is a characteristic diagram showing a change state of a phase difference in a frequency pass band in the infinite impulse response digital filter shown in FIG.

FIG. 7 is a characteristic diagram showing a change state of a group delay when the number of phase gradients is used as a parameter in an infinite impulse response digital filter.

FIG. 8 is a table showing an example of coefficient values set in a multiplication coefficient generator when the number of generated phase gradients and the number of tap stages in a signal processing stage are determined in an infinite impulse response digital filter.

FIG. 9 is a table showing an example of coefficient values set in a multiplication coefficient generator when the number obtained by adding 1 to the number of phase gradients shown in FIG. 8 is used as the number of coefficients.

FIG. 10 is a circuit diagram showing an example of a configuration of an infinite impulse response digital all-pass filter used for an in-phase signal interpolator and a quadrature signal interpolator when coefficient values as shown in FIG. 9 are set.

11 is a circuit diagram showing another example of the configuration of the infinite impulse response digital all-pass filter used in the in-phase signal interpolator and the quadrature signal interpolator when the coefficient values as shown in FIG. 9 are set. is there.

FIG. 12 is a block diagram showing a second embodiment of the orthogonal frequency division multiplex modulation circuit according to the present invention, showing a main configuration thereof.

FIG. 13 is a signal waveform diagram obtained at an output circuit portion of the orthogonal frequency division multiplex modulation circuit shown in FIG.

FIG. 14 is a block diagram showing a second embodiment of the orthogonal frequency division multiplex modulation circuit according to the present invention, showing a main configuration thereof.

FIG. 15 is a block diagram illustrating an example of a configuration of a known orthogonal frequency division multiplex modulation circuit.

FIG. 16 is a signal waveform diagram obtained in each unit of the orthogonal frequency division multiplex modulation circuit shown in FIG.

FIG. 17 is a circuit diagram showing a basic circuit example of a finite impulse response digital low-pass filter used in the in-phase signal interpolator and the quadrature signal interpolator.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Digital modulator 2 Serial-parallel converter (S / P) 3 Inverse Fourier converter (IFFT) 4 Parallel-serial converter (P / S) 5 First-stage interpolator 5 ₁ , 6 ₁ , 15 ₁ , 1st infinity Impulse response (II
R) Digital all pass filter _{(90 °) 5 2, 6} 2, 15 2 first digital delay device _{(DL) 5 3, 6 3} , 15 3 second infinite impulse response (II
R) Digital all pass filter _{(90 °) 5 4, 6} 4, 15 4 second digital delay device _{(DL) 5 5, 6 5} , 15 5 180 ° phase shifter _{(180 °) 5 6, 6} 6, 15 ₆ first one-circuit two-contact switch 5 _7, 6 _7, 15 ₇ the second one-circuit two-contact switch 6 next stage interpolator 7I phase signal multiplier 7Q quadrature signal multiplier 8 local oscillator 9 90 ° phase shift (90 °) 10 Adder 11 Digital-to-analog converter (D / A) 12 Digital data input terminal 13 Analog signal output terminal 14, 14 ', 14' Infinite impulse response (IIR)
Digital all-pass filter 15 Another next stage interpolator

Claims (7)

[Claims] 1. An inverse Fourier transform means for mapping a digital modulation signal to a plurality of subcarriers centered on a half of the sampling frequency, performing an inverse Fourier transform, and outputting a plurality of inverse Fourier transform signals. Interpolating means comprising one or more interpolators connected in cascade for sequentially interpolating the plurality of inverse Fourier transform signals by the interpolation order 2 for each of the in-phase signal and the quadrature signal, and the in-phase output from the interpolating means. An orthogonal frequency division multiplexing modulation circuit comprising: an interpolation signal; and orthogonal modulation means for orthogonally modulating the orthogonal interpolation signal. 2. An inverse Fourier transform means for mapping a digital modulation signal to a plurality of subcarriers centered on a half of the sampling frequency, performing an inverse Fourier transform, and outputting a plurality of inverse Fourier transform signals. Interpolating means comprising one or more cascade-connected interpolators for sequentially interpolating the plurality of inverse Fourier transform signals by the interpolation order 2 for each of the in-phase signal and the quadrature signal, and the in-phase signal output from the interpolating means. An interpolation signal and an orthogonal modulation means for orthogonally modulating the orthogonal interpolation signal, wherein each of the interpolators includes an infinite impulse response digital all-pass filter that shifts an in-phase signal or an orthogonal signal by 90 °, and the orthogonal signal or the orthogonal signal. A digital delay circuit for delaying the phase signal by the signal delay of the infinite impulse response digital all-pass filter. Frequency division multiplexing modulation circuit. 3. The orthogonal frequency division multiplex modulation circuit according to claim 1, wherein said interpolation means has two interpolators when interpolating with an interpolation order of four. 4. The orthogonal frequency division multiplex modulation circuit according to claim 1, wherein said interpolation means has three interpolators when interpolating with an interpolation order of 8. 5. The orthogonal frequency division multiplex modulation circuit according to claim 1, wherein said interpolation means has four interpolators when interpolating with an interpolation order of 16. 6. The infinite impulse response digital all-pass filter includes a cascade-connected arbitrary integer of 3 or more.
Each of the signal processing units has a first delay unit, a second delay unit, an addition unit, a multiplication unit, and a multiplication coefficient generation unit, and the operating frequency of the signal processing unit is the infinite impulse. It is twice the signal output frequency of the response digital all-pass filter, and is 1/1 of the operating frequency of the signal processing unit.
The orthogonal frequency division multiplexing according to any one of claims 2 to 5, wherein constants of the respective units are set so that the number of phase gradients generated in a signal band centered on the frequency of 4 is n-1. Modulation circuit. 7. The infinite impulse response digital all-pass filter includes only an even-numbered signal processing unit from the output side, and operates at a half of the operating frequency. 4. The orthogonal frequency division multiplex modulation circuit according to 1.