JP2002290220A - Current control circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a current control circuit that reduces the current consumption in a standby state. SOLUTION: MOSFETs Q2, Q3 are nonconductive in a standby state and a MOSFET Q1 is also nonconductive in the absence of an input signal Sin. A signal detection section 1 detects the presence of the input signal Sin and gives a signal S1 as a result of the detection to a logic circuit 5. The logic circuit 5 outputs a signal S2 in response to the signal S1 to make the MOSFETs Q2, Q3 conductive to supply power to a waveform shaping section 2 and to release the standby state. Thus, almost no current flows through the waveform shaping section 2 in the standby state.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to the field of communications.
The present invention relates to a circuit that is used in a control circuit using a battery, a battery, or the like as a power supply, and particularly controls a current in a standby state of an electrical device.

[0002]

2. Description of the Related Art In a vehicle such as an automobile, for example, a plurality of electric devices such as a wiper, a door lock, and a power window are driven by a battery. Each of such electrical devices is connected to a control unit, and the control units are connected to each other by, for example, a LAN (Local Area Network), and signals are transmitted and received between the electrical devices via signal wiring constituting the LAN. Is done.

FIG. 4 shows the configuration of this type of apparatus.
As shown in FIG. 4, a plurality of control units 30 are connected to a signal line L1 such as a bus via an input terminal RX and an output terminal TX. Each control unit 30 is provided for each electric device (not shown) such as a wiper and a door lock, and each electric device is driven by a motor M connected to the control unit 30. That is, for example, the control unit 30 provided in the wiper supplies a signal to the motor M in accordance with the on / off of the switch SW arranged in the driver's seat, and the wiper operates by driving the motor M.

[0004] Recently, in vehicles using a LAN as described above, devices using the LAN even when the engine is not operating, that is, even when the battery is not charged, are increasing. Even when the engine is not operating, the electrical devices such as the wiper and the auto lock are always in an operation standby state, and the control unit 30 receives and sends signals to and from other control units via signal wiring constituting the LAN. ing. For this reason, the power of the battery is constantly consumed.

FIG. 5 shows a conventional example of the control unit 30. As shown in FIG. A resistor R3 connected in series as shown in FIG.
1, R32 divides the voltage of battery E. This divided voltage is supplied to the inverting input terminal of the comparator C. An input signal Sin from another control unit (not shown) is supplied to the non-inverting input terminal of the comparator C via a LAN signal line and an input terminal RX. The output signal S31 of the comparator C is transmitted to the LAN controller 31, the standby controller 3
2 is input to the logic circuit 33 constituting the second circuit. LA
The N controller 31 analyzes the contents of the packet of the input signal S31. As a result, the ID set in the LAN controller 31 and the ID included in the tag of the packet are
Are matched, the data in the packet is
To send to.

The standby control unit 32 controls the control unit 30 to switch between a standby state and an operating state. In the standby control 32, the logic circuit 33
Supplies a signal S32 to be described later to one input terminal of the NAND circuit 34 according to the presence or absence of an output signal from the comparator C.

The output signal S33 of the LAN controller 31
Is supplied to the logic circuit 33, and the output signal S34 is supplied to the other input terminal of the NAND circuit 34. The output terminal of the NAND circuit 34 is a P-channel MOS as a transmission driver.
It is supplied to the gate of the FET 35. This MOSFET3
5 is controlled according to the output signal of the NAND circuit 34, and outputs the output signal Sout from the output terminal TX.

The LAN controller 31 has a CP
The CPU 36 is connected to a motor M for driving electric equipment (not shown) and a switch SW for turning on / off the electric equipment.

In the control unit 30 having the above configuration, as shown in FIG.
, Currents I31 and I32 flow. For this reason, the control unit 30 can receive the input signal Sin output from another control unit via the signal wiring of the LAN. When the input signal Sin is not supplied, the MOSFET 35 is turned off by the standby control unit 32. That is, the control unit 30 is in a standby state.

On the other hand, when an input signal Sin is supplied to the input terminal RX, a high-level signal S31 is output according to the input signal Sin. Then, the signal S32 is output from the logic circuit 33, and the standby state is released.
In this state, the signal S31 corresponding to the input signal Sin
Is supplied to the LAN controller 31.

The LAN controller 31 analyzes the contents of the signal S31, and supplies the data in the packet to the CPU 36 when the ID included in the packet matches the ID of the LAN controller 31. On the other hand, LAN controller 3
No. 1 does not output a signal when the IDs do not match. Further, for example, when there is a defect or the like in the data and the CPU 36 cannot read the data, and when there is a communication request command from the CPU 36, the LAN controller 31 supplies the data to that effect to the NAND circuit 34 as a signal S34. The MOSFET 35 operates according to the signal S34, and outputs an output signal Sout from the output terminal TX.

When there is no input signal Sin for a predetermined time, the LAN controller 31 outputs a low-level signal S33 as an instruction to shift to a standby state.
Supply to Therefore, the output signal S of the logic circuit 33
32 goes low, and the output signal of the NAND circuit 34 goes high. Therefore, the MOSFET is turned off by the control unit 30, and the control unit 30 is set to the standby state. That is, the standby control unit 32 and the LAN controller 31 are stopped. But,
In this standby state, currents I31 and I32 are flowing through the resistors R31 and R32 and the comparator C, respectively.

[0013]

As described above, in the conventional control unit, current always flows even in a state where the engine is stopped and in a standby state, so that the power of the battery is consumed. For this reason, the voltage of the battery decreases, and in the worst case, a problem occurs that the engine of the automobile cannot be started. Therefore, it is desired to reduce the power consumption of the control unit even when the engine is not operating.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide a current control circuit capable of reducing current consumption during standby.

[0015]

In order to solve the above-mentioned problems, a current control circuit according to the present invention has a receiving circuit for receiving an input signal, and a switch connected between a power supply terminal of the receiving circuit and a power supply. A circuit, a detection circuit for detecting the presence or absence of the input signal, and a detection circuit connected to the detection circuit, wherein when the input signal is detected by the detection circuit, the switch circuit is turned on to supply power to the reception circuit and to enter standby mode. And a control circuit for canceling the state.

A current control circuit according to the present invention includes a receiving circuit to which an input signal is supplied and for outputting a first control signal; a switch circuit connected between a power supply terminal of the receiving circuit and a power supply; A detection circuit for detecting the presence or absence of the input signal;
A first control circuit for supplying the first control signal and outputting a second control signal in response to the first control signal; and a first control circuit connected to the detection circuit, wherein the detection circuit detects the input signal. In this case, the switch circuit is turned on to supply power to the reception circuit to release the standby state, and the switch circuit is turned off in response to the second control signal to stop power supply to the reception circuit, thereby stopping the standby circuit. And a second control circuit for setting a state.

[0017]

Embodiments of the present invention will be described below with reference to the drawings.

(First Embodiment) FIG. 1 is a circuit diagram showing a first embodiment of a current control circuit according to the present invention. FIG.
As shown in (1), an input signal Sin is input to the signal detection unit 1 from an input terminal RX via a signal wiring configuring a LAN. The signal detector 1 detects the presence or absence of the input signal Sin. The input signal Sin is input to the gate of the N-channel MOSFET Q1 constituting the signal detection unit 1. This M
The drain of the OSFET Q1 is connected to the positive terminal of a power source E such as a battery via a resistor R1, and the source and the substrate are connected to the negative terminal of the power source E and grounded.

The input signal Sin is supplied to the waveform shaping unit 2.
The waveform shaping unit 2 shapes the waveform of the input signal Sin. The waveform shaping unit 2 includes a reference voltage generating unit 3 including a resistor R2 and a resistor R3 connected in series, and a comparator C. The input signal Sin is supplied to a non-inverting input terminal of the comparator C. The resistors R2 and R3 divide the voltage of the power supply E, and the divided voltage is supplied to the inverting input terminal of the comparator C.

The waveform shaping unit 2 includes an N-channel MOSF
It is connected to a power supply control unit 4 composed of ETQ2 and Q3. These MOSFETs Q2 and Q3 control power supply to the reference voltage generator 3 and the comparator C. That is, the current path of the MOSFET Q2 is
Connected between the power supply E and the negative terminal (ground) of the power supply E
The current path of Q3 is connected to the power line L of the comparator C and the power line E.
Are connected between the negative terminals of.

A connection node between the resistor R1 and the MOSFET Q1 is connected to a standby control unit 6 composed of a logic circuit 5 and a NAND circuit ND. The standby control unit 6 controls switching between a standby state and an operation state of the control unit 9 in accordance with an output signal S1 of the signal detection unit 1 and a signal S8 supplied from a LAN controller 7 described later. The output signal S1 of the signal detector 1 is supplied to a logic circuit 5. This logic circuit 5 has, for example, a flip-flop circuit. When the input signal Sin is detected by the signal detection section 1, the flip-flop circuit is set in the logic circuit 5, and the logic circuit 5 outputs high-level signals S2 and S3. Output signal S of logic circuit 5
2 is supplied to one input terminal of the AND circuit AD and to the bases of the MOSFETs Q2 and Q3. In response to the signal S2, the MOSFETs Q2 and Q3 are turned on.
The power is turned off, and the power supply to the waveform shaping unit 2 is controlled.
The output signal S3 of the logic circuit 5 is connected to the NAND circuit ND.
Is supplied to one input terminal.

The output terminal of the comparator C is connected to the other input terminal of the AND circuit AD. AND circuit A
D is a high level signal S2 from the logic circuit 5 while the standby state of the control unit 9 is released.
Is provided so that the output signal of the comparator C can be supplied to the LAN controller 7 only during the period when is output. The output signal S7 of the AND circuit AD is supplied to the LAN controller 7. A CPU 8 is connected to the LAN controller 7. A switch SW for turning on / off an electric device (not shown) and a motor M for driving the electric device are connected to the CPU 8. The motor M is driven by a signal output from the CPU 8 in response to the operation of the switch SW. The LAN controller 7 analyzes the contents of the packet of the input signal S7. As a result, this L
When the ID set in the AN controller 7 matches the ID included in the tag of the packet, the data in the packet is sent to the CPU 8. On the other hand, the LAN controller 7
Does not output a signal when the IDs do not match. The output terminal of the NAND circuit ND is connected to the gate of the P-channel MOSFET Q4. The source of the MOSFET Q4 is connected to the positive terminal of the power supply E, and the drain is connected to the output terminal TX. Therefore, the packet is transferred to another control unit via the MOSFET Q4. further,
When the input signal Sin is not supplied for a predetermined time, the LAN controller 7 outputs a signal S8 for setting a standby state. This signal S8 is supplied to the logic circuit 5.

The operation of the current control circuit having the above configuration will be described below.

<Transition Operation from Standby State to Operating State> FIG. 2 is a timing chart of voltages of respective parts in FIG. When the power supply E is turned on at the time T1 shown in FIG. 2, the output signal S1 of the signal detector 1 goes high accordingly, and the drain voltages S4, S5 of the MOSFETs Q2, Q3 go high. Here, the input signal Si
When n is at the low level, the MOSFET Q1 is off, and when the signal S1 is at the high level, the output signal S2 of the logic circuit 5 is set at the low level. Therefore, both MOSFETs Q2 and Q3 are off. Therefore, no current flows through the signal detection unit 1, the waveform shaping unit 2, the standby control unit 6, and the LAN controller 7, and the control unit 9 is in a standby state. At this time, the logic circuit 5 constituting the standby control unit 6
Is low level, and the output signal of the NAND circuit ND is high level. Therefore, the MOSFET Q4 is turned off, and the output signal Sout is not output.

Thereafter, at time T2, the input signal Sin
Goes high, the MOSFET Q1 turns on, and the signal S1 goes low. When the low-level signal S1 is supplied to the logic circuit 5, the logic circuit 5 outputs high-level signals S2 and S3. The high-level signals S2 and S3 continue to be output until a signal S8 output from a LAN controller described later goes to a low level.

The high level signal S2 is output from the AND circuit A
D is supplied to one input terminal of the MOSFET Q.
2, supplied to the gate of Q3. Therefore, MOSFET
Q2 and Q3 are turned on, and current I1,
I2 flows. Therefore, the waveform shaping unit 2 operates. Therefore, the standby state of the control unit 9 is released.

In this state, the input signal Sin supplied from another control unit via the signal wiring of the LAN is subjected to waveform shaping by the waveform shaping section 2 and supplied to the LAN controller 7 via the AND circuit AD as the signal S7. You. When the signal S7 is supplied, the LAN controller 7 outputs a high-level signal S8.

Further, the LAN controller 7 outputs a signal S7
When the ID included in the packet matches the ID of the LAN controller 7, the data in the packet is supplied to the CPU 8. On the other hand, the LAN controller 7
Does not output any signal when the IDs do not match. Also,
For example, when there is a defect or the like in the data and the CPU 8 cannot read the data, and when there is a communication request command from the CPU 8, the LAN controller 7 supplies the data to that effect as a signal S9 to the NAND circuit ND. MOSFE
TQ4 operates according to this signal S9, and outputs an output signal Sout from the output terminal TX.

<Transition Operation from Operation State to Standby State> When the input signal Sin has not been present for a predetermined time, the LAN controller 7 outputs a low-level signal as an instruction to transition to the standby state, as shown at time T3 in FIG. S8 is supplied to the logic circuit 5. When the signal S8 is supplied, the logic circuit 5 sets the signals S2 and S3 to low level. Therefore, the MOSFETs Q2 and Q3 are turned off, and the waveform shaping unit 2 is stopped. Further, the input condition of the AND circuit AD is not satisfied, and the signal S7 is not supplied to the LAN controller 7. Therefore, the control unit 9 shifts to the standby state.

According to the first embodiment, the logic circuit 5 outputs the signal S2 in accordance with the output signal S1 of the signal detection unit 1 and the output signal S8 of the LAN controller 7, and supplies power in accordance with the signal S2. By controlling the control unit 4, the currents I1 and I2 flowing through the waveform shaping unit 2 are controlled. That is, in the standby state, the power supply control unit 4
The current to the waveform shaping section 2 is cut off by turning off the MOSFETs Q2 and Q3 constituting Therefore,
In the standby state, the control unit 9 does not consume current, so that power consumption of the battery can be suppressed.

The standby control unit 6 is constituted by the logic circuit 5 or the like, but is not limited thereto.
The CPU performs software control to detect signals SS1 and S8, and to detect signals S2 and S3.
May be controlled. Similarly, the LAN controller 7 may be configured by a CPU and controlled by software.

(Second Embodiment) FIG. 3 is a circuit diagram showing a second embodiment of the present invention. In the second embodiment, the signal detection unit 1, the waveform shaping unit 2, and the power supply control unit 4 are configured by bipolar transistors and resistors. The other components such as the logic circuit 5 and the LAN controller 7 are the same as those in the first embodiment, and thus are omitted from FIG.

As shown in FIG. 3, the input terminal RX is connected to the comparator section C of the waveform shaping section 3. The comparator section C includes transistors Q11 to Q16. That is, the input signal Sin is supplied to the base of the PNP transistor Q11. This transistor Q11
Is grounded, and the emitter is connected to the base of PNP transistor Q12. Transistor Q12
Is connected to the collector and base of the NPN transistor Q13 and the base of the NPN transistor Q14. The emitter of the transistor Q13 and the emitter of the transistor Q14 are each grounded. The emitter of the transistor Q12 is a PNP transistor Q15
The collector of the transistor Q15 is connected to the collector of the transistor Q14. The base of transistor Q15 is connected to the emitter of PNP transistor Q16.
The collector of 6 is grounded.

The base of the transistor Q16 is connected to a connection node between one end of the resistor R11 and one end of the resistor R12 constituting the reference voltage generator 3, and the other end of the resistor R11 is connected to, for example, 5
V power supply. The waveform shaping section 2 is constituted by the reference voltage generating section 3 and the comparator section C.

The connection node between the transistors Q14 and Q15 is connected to the base of an NPN transistor Q17. The emitter of this transistor Q17 is grounded,
The collector is connected to the LAN controller 7 shown in FIG. 1 via the inverter circuit IV11. The connection node between the transistor Q17 and the inverter circuit IV11 is connected to a 5V power supply via a resistor R13.

The input terminal RX is connected to the signal detector 1. The signal detection unit 1 includes resistors R14 and R15 and a transistor Q18. That is, the input signal Sin is supplied to the NPN transistor Q18 via the resistor R14.
Is supplied to the base. The emitter of the transistor Q18 is grounded and connected to the base of the transistor Q18 via a resistor R15. Also,
The collector of the transistor Q18 is connected to the logic circuit 5 shown in FIG.
It is connected to the power supply via a resistor R16.

The signal S supplied from the logic circuit 5
2 is supplied to the power supply control unit 4a. The power supply unit 4a includes resistors R17 and R18 and a transistor Q19. That is, the signal S2 is connected to the base of the NPN transistor Q19 via the resistor R17. The emitter of the transistor Q19 is grounded, connected to the base of the transistor Q19 via a resistor R18, and the collector is connected to the other end of the resistor R12.

The signal S2 is supplied to the power supply control unit 4 via the buffer BF12. This power supply control unit 4
Are resistors R19 to R25 and transistors Q20 to Q2
6. That is, the output terminal of the buffer BF12 is connected to the base of the NPN transistor Q20 via the resistor R19. The emitter of this transistor Q20 is connected to the base of NPN transistor Q21, and is grounded via resistor R20. The collector of the transistor Q21 is connected to the base of the transistor Q20, and the emitter is grounded.

The collector of the transistor Q20 is PN
Connected to the base of P transistor Q22. The collector of the transistor Q22 is grounded, and the emitter is connected to the base of the PNP transistor Q23 via the resistor R21. The collector of the transistor Q23 is connected to a connection node between the collector of the transistor Q20 and the base of the transistor Q22, and the emitter of the transistor Q23 is, for example, 1 through a resistor R22.
It is connected to a 2V power supply.

The base of the transistor Q23 and the resistor R
21 are connected to PNP transistors Q24, Q2
5, Connected to the base of Q26. The emitters of these transistors Q24 to Q26 are connected to resistors R23 and R2, respectively.
4. Connected to the 12V power supply via R25. The collector of the transistor Q24 is connected to the base of the transistor Q12. The collector of the transistor Q25 is connected to the emitters of the transistors Q12 and Q15. Also, the transistor Q26
Is connected to the base of the transistor Q15.

The operation of the current control circuit according to the second embodiment is the same as that of the first embodiment. When the high-level input signal Sin is supplied from the input terminal RX, the control unit 9 operates in the standby mode. Transition from state to operating state. That is, when the high-level input signal Sin is supplied, the transistor Q18 of the signal detection unit 1 is turned on. Therefore, the low-level signal S1 is
The signal is input to the logic circuit 5 via F11, and a high-level signal S2 is output from the logic circuit 5. This signal S2 turns on the transistors Q20 and Q21 of the power supply control unit 4, and turns on the transistors Q22 and Q23. Therefore, the transistors Q24 to Q26 turn on,
A voltage of 12 V is supplied to the comparator section C.

The transistor Q19 of the power supply control section 4a is turned on by the high level signal S2, and a voltage of 5 V is supplied to the resistors R11 and R12 constituting the reference voltage generating section 3. These resistors R11 and R12 divide a voltage of 5V. This divided voltage is supplied as a reference voltage to the base of the transistor Q16 forming the comparator section C.

Thereafter, the input signal Sin supplied from another control unit via the LAN is shaped by the waveform shaping unit 2. The transistor Q17 is controlled according to the output signal of the waveform shaping unit 2, and the signal S7 via the inverter circuit IV11 is supplied to the LAN controller 7.
The subsequent operation is the same as that of the first embodiment. Thus, the control unit 9 shifts from the standby state to the operating state.

When there is no input signal Sin for a predetermined time, the control unit shifts from the operating state to the standby state. That is, when there is no signal S8 supplied to the LAN controller 7 via the comparator section C for a predetermined time, the LAN controller 7 supplies a low-level signal S8 to the logic circuit. In response, logic circuit 5 supplies low-level signal S2 to the base of transistor Q20. Therefore, the transistor Q21 turns off,
The transistors Q22 and Q23 turn off. When the transistors Q21 and Q22 are turned off, the transistors Q24 to Q26 are turned off, and the current flowing to the comparator C is cut off. Therefore, the operation of the comparator section C stops.

The low-level signal S2 is supplied to the base of the transistor Q19, and the transistor Q19 turns off. Therefore, the current flowing to the reference voltage generator 3 is cut off. Thus, the control unit is in the standby state.

In the second embodiment, an NPN transistor is used as the transistor Q18 of the signal detecting section 1 to detect a high-level input signal Sin. However, it is also possible to use a PNP transistor to detect the low-level input signal Sin. In this case, the base of the PNP transistor is connected to the resistor R13, and the emitter is connected to the buffer circuit 11. The collector of the PNP transistor is
It is connected to the power supply and to the base of the PNP transistor via the resistor R14.

According to the current control circuit according to the second embodiment of the present invention, the same effects as in the first embodiment can be obtained.

Of course, various modifications can be made without departing from the spirit of the present invention.

[0049]

As described in detail above, according to the present invention,
A current control circuit capable of reducing current consumption during standby can be provided.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a first embodiment of a current control circuit according to the present invention.

FIG. 2 is a timing chart of voltages of respective parts in FIG. 1;

FIG. 3 is a circuit diagram showing a second embodiment of the current control circuit according to the present invention.

FIG. 4 is a diagram showing a configuration of an in-vehicle LAN.

FIG. 5 is a diagram showing a conventional example of a control unit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Signal detection part, 2 ... Waveform shaping part, 3 ... Reference voltage generation part, 4 ... Power supply control part, 5 ... Logic circuit, 6 ... Standby control part, 7 ... LAN controller, 8 ... CPU, 9 ... Control unit RX: input terminal, TX: output terminal, Q1 to Q4: MOSFET, R1 to R3: resistor, E: power supply, C: comparator AD: AND circuit, ND: NAND circuit, M: motor, SW: switch.

 ──────────────────────────────────────────────────続 き Continued on the front page F-term (reference) 5H410 BB05 CC02 DD02 EA11 EA12 EB01 EB37 FF03 FF24 KK03 KK05 5J055 AX13 AX64 BX16 CX28 DX04 DX14 DX22 EX01 EX02 EY01 EY03 EY17 EY21 EZ07 EZ10 EZ25 EZ31 EZ31 EZ25 EZ31

Claims (2)

[Claims] A receiving circuit for receiving an input signal; a power supply control circuit connected between a power supply terminal of the receiving circuit and a power supply; a detection circuit for detecting at least the presence of the input signal; A control circuit that is connected to a detection circuit and turns on the power supply control circuit to supply power to the reception circuit and release a standby state when the input signal is detected by the detection circuit. Current control circuit. 2. A receiving circuit to which an input signal is supplied and outputs a first control signal; a power supply control circuit connected between a power supply terminal of the receiving circuit and a power supply; A first control circuit that supplies the first control signal, and outputs a second control signal in response to the first control signal; and a detection circuit that is connected to the detection circuit, When the input signal is detected by the detection circuit, the power supply control circuit is turned on to supply power to the reception circuit to release a standby state, and the power supply control circuit is turned on in response to the second control signal. And a second control circuit for turning off the power supply to the receiving circuit and setting a standby state.