JP2002288107A - Device and method for data transfer, program and recording medium - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a data transferring device capable of reducing the capacity of FIFO for transmission or for reception compared with the size of the largest packet which can be handled by a system. SOLUTION: A path switching part 14 is provided with a mediation part 15 for mediating accessing a data processing part 17 from a data storage part 11, a second device 12 and a third device 13 to allow a multiplexer 16 to switch a first path, a second path and a third path based on the mediation by this part 15. Consequently, this data transferring 10 can make one path and another path between the part 11 and the part 17 do not mutually give influence. Paths between other devices are provided separately from the paths to be switched by the part 14.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for transferring data between data storage means for temporarily writing and reading data and data processing means shared by the data storage means and at least one other device. And a data transfer method.

[0002] The present invention also relates to a program relating to the data transfer method, and a recording medium recording the program.

[0003]

2. Description of the Related Art Digital signal transmission standards include, for example, IEC (International Electrotechnical Communications).
n: International Electrotechnical Standards Organization and IEEE (Institute of Elec)
There are a number of standards, including those from the Tricaland Electronic Engineer (American Institute of Electrical and Electronics Engineers).

[0004] Among them, for example, IEEE 1394 has been attracting attention as being suitable for multimedia applications such as connection between home electronic devices such as digital video recorders, and connection between these electronic devices and computers. IEEE
In a 1394 system, data is basically divided into packets and transferred. Packet transmission methods include isochronous (Isochronous) transmission and asynchronous (Async) transmission.
hronous) There is a transfer.

[0005] Isochronous transfer secures a band for transferring data such as video and audio, and enables real-time transfer. For example, video data is divided into predetermined lengths (4 kB) to form packets, and the packets are synchronously transferred at regular intervals. Instead of forwarding to a specific node, use the channel address to send across the bus. The receiving node wants the channel ID
Make sure you receive the packet. FIG. 5 shows the transition between the transmitting side and the receiving side in the isochronous transfer. The transmission request transmission from the transmission side is received by the reception side, the transmission acknowledgment is returned from the reception side to the transmission side, and after the transmission acknowledgment is received by the transmission side, data transmission starts. If the receiving side starts receiving data and then the transmitting side ends the transmission, the receiving side also ends the receiving, sends a receiving completion transmission to the transmitting side, and the transmitting side receives the receiving completion and receives this isochronous transmission. The transfer ends.

[0006] Asynchronous transfer is asynchronous transfer, and data is not transferred periodically. For example, it is used to transfer a control command for video data of a digital camera or the like. A packet is composed of several bytes of head information and actual data, and is transferred to a designated node. Specifically, the transmission ID and the reception ID are stored in the header information, and the receiving node confirms its own ID and receives the packet. The receiving node receiving the data returns an acknowledgment to the transmitting node. FIG. 6 shows the transition between the transmitting side and the receiving side in asynchronous transfer. The receiving side confirms its own ID from the head information of the packet, receives the packet, and starts receiving. When the packet ends, the reception ends.

Next, a specific example of the IEEE1394 system for multimedia use is shown in FIG. This is a 1394 network system in which a main body 2 of a personal computer (PC) 1 and a camera-integrated video tape recorder (hereinafter referred to as CAM) 5 are connected by a 1394 bus 6. Here, a PCI bus compatible IEEE1394 interface board (hereinafter 1394I /
The F board 4 is built in the PC body 2.

FIG. 8 shows a connection relationship between the 1394 I / F board 4 and the PC main body 2.

The 1394 I / F board 4 includes a physical layer block (13
94PHY) 41 and a link layer block (1394Link) 42. The physical layer block 41 initializes the 1394 serial bus 6, arbitrates the right to use the 1394 serial bus 6, and the like. Also, various control signals are communicated with the link layer block 42, and these signals are transmitted and received to and from the 1394 serial bus 6. Link layer block 4
2 is a 1394 link core (Link Core) section 420 and a reception F
IFO (FirstIn First Out: FirstIn First
Out) 421, a DMA controller / bus interface 422, and a transmission FIFO 423.

The PC body 2 is described in a simplified manner.
The configuration is such that the DRAM 23 and the ROM 24 are connected. Here, the DRAM 23 is an external storage unit when viewed from the 1394 I / F board 4.

The reception FIFO 421 and the transmission FIFO 423 are
For example, it is used to prevent data loss between the link layer block 42 and the physical layer block 41.

In IEE1394, link LINK layer, physical PHY
Once the data transfer between the layers is approved, it must be possible to receive or transmit the data of the packet length without interruption. Therefore, the reception FIFO 421 and the transmission FIFO
Data is stored in a dedicated storage unit such as the FIFO 423 to prevent data loss.

For this reason, the capacity of the reception FIFO 421 and the transmission FIFO 423 included in the link layer block 42 is equal to the maximum packet length (4 kB) that this system can handle, or 13
It had to be larger than the maximum packet length of 94. Also, to improve performance, for isochronous,
In some cases, each FIF0 was divided for asynchronous use.

In the configuration shown in FIG. 8, in the case of receiving data from the CAM 5, the transfer is approved between the physical layer block of the CAM 5 and the physical layer block 41 of the 1394 I / F board 4. Then, the data transfer of the packet length is performed without being suppressed. This data enters the reception FIF0421 of the link layer block 42, and is further transferred to the DRAM 23, which is an external storage unit.

The DRAM 23, which is an external storage unit, stores 1394 I
When viewed from the / F board 4 side, it is shared with the CPU 21. As described above, the external storage unit is generally often shared with other devices such as a CPU. Therefore, for example, data transfer between the reception FIF0421 and the DRAM 23 is affected by other devices using the bus 20, and
It is not always possible to guarantee the communication speed between the physical layer blocks. In that case, the received data gradually accumulates in the reception FIF0421.

FIG. 9 shows this situation. Since the bus 20 of the PC (PC system) also uses devices other than the 1394 I / F board 4, the bus on the system side cannot maintain the communication speed between the physical layer block 41 and the link layer block 42 for a short time , At least the maximum packet length (for example, 4 kB)
If there is no FIF0, the reception FIFO 421 will overflow.

The data read from DRAM 23 is stored in CA
When sending to M5, send FIFO of link layer block 42
At 423, an underflow will occur.

[0018]

Problems to be solved by the invention are summarized below.

First, in the prior art, the link layer block 4
2 FIFO capacity, the maximum packet length that the system can handle,
For example, it must be 4 KB or larger, and the gate size and
The problem of increased power consumption occurs.

Further, the data transfer between the FIF0 of the link layer block 42 and the external storage (DRAM) cannot be made in time.
If the packet overflows or underflows, packets may be retransmitted or dropped, which may cause a performance problem or a catastrophic failure as a system.

If the data transfer between the FIF0 of the link layer block 42 and the external storage is not completed, the data processing cannot be performed on the system side, so the data transfer between the physical layer block and the FIF0 in the link layer block is completed. When the time until the completion of the data transfer between the FIF0 and the external storage (DRAM) (the data transfer completion interrupt to the CPU) becomes long, this has a bad influence on the real-time performance of the system.

The present invention has been made in view of the above circumstances, and in a system including a 1394 device, the capacity of a transmitting or receiving FIF0 can be made smaller than the maximum packet size that can be handled by the system. It is an object of the present invention to provide a data transfer device and a data transfer method capable of reducing a gate scale of a system and low power consumption, a program related to the data transfer method, and a recording medium recording the program.

[0023]

In order to solve the above-mentioned problems, a data transfer device according to the present invention has a data storage means in which data is temporarily written and read, and at least one other data storage means. A data transfer apparatus for transferring data between a data processing unit shared by a device and a data processing unit, comprising: a switching unit that switches a data transfer path between the data processing unit and the data storage unit and the at least one other device. The connection from the data storage means and at least one other device to the data processing means is each dedicated transfer path using the switching means.

In this way, since the data transfer apparatus prepares a dedicated transfer path, it is not affected by the transfer of another device unrelated to the transfer.

The data processing means of the data transfer device is an external storage means as viewed from the data storage means.
Writing of data from the data storage means or the at least one other device to the external storage means is performed by controlling the assignment of each dedicated transfer path using the switching means. Then, the maximum time from the approval to the response to the data transfer request to the data processing unit issued by the data storage unit is guaranteed to a fixed time.

As a result, it is possible to guarantee the maximum delay time from the acknowledgment to the response to the data transfer request.

Further, the data transfer device includes arbitration means for arbitrating access to the data processing means from the data storage means and at least one other device. Switch paths.

[0028] The arbitration means raises the priority of access to the data processing means from the data storage means over the at least one other device. Further, the arbitration unit determines a maximum value of a continuous occupation time of the bus accompanying access to the data processing unit from the data storage unit and at least one other device.

Thus, the maximum delay time from the data transfer request to the approval can be guaranteed.

In order to solve the above-mentioned problems, a data transfer method according to the present invention provides a data storage means in which data is temporarily written and read and a data storage means shared by the data storage means and at least one other device. A data transfer method for transferring data to and from a processing means, comprising: a switching step of switching a data transfer path between the data processing means and the at least one other device and the data processing means; The connection from the means and at least one other device to the data processing means is each dedicated transfer path using the switching step.

This data transfer method includes an arbitration step of arbitrating access from the data storage means and at least one other device to the data processing means. Based on the arbitration in the arbitration step, the switching step performs a data path operation. Switch.

In the arbitration step, the priority of access from the data storage means to the data processing means is higher than that of the at least one other device. In the arbitration step, a maximum value of a continuous occupation time of a bus accompanying access from the data storage unit and at least one other device to the data processing unit is determined.

In order to solve the above-mentioned problems, a program according to the present invention provides a data storage unit in which data is temporarily written and read, and a data processing unit shared by the data storage unit and at least one other device. An arbitration step for arbitrating access to the data processing means from the data storage means and at least one other device, wherein the arbitration step comprises: A switching step of switching a data transfer path between the data storage means and the at least one other device and the data processing means based on arbitration of the data storage means and the at least one other device. The connection to the processing means is performed by using the above-mentioned switching step to set each dedicated transfer path. To be executed by the processor.

According to the recording medium of the present invention, data is transferred between data storage means for temporarily writing and reading data and data processing means shared by the data storage means and at least one other device. And a arbitration step for arbitrating access to the data processing means from the data storage means and at least one other device, wherein the arbitration step comprises: A switching step of switching a data transfer path between the data storage means and the at least one other device and the data processing means based on arbitration of the data storage means and the at least one other device. The processing to make the connection to the processing means a dedicated transfer path using the switching step is an arithmetic processing It records a program to be executed by a location.

[0035]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Some embodiments of the present invention will be described below with reference to the drawings. First, first
An embodiment will be described. The first embodiment is a data transfer device 10 having the configuration shown in FIG.
Data is transferred between the data storage unit 11, the second device 12 and the third device 13 which are devices, and the data processing unit 17.

The data transfer device 10 includes a data storage unit 11, a path switching unit 14 for switching the data transfer path between the second device 12 and the third device 13 and the data processing unit 17, and includes a path switching unit 14. Using the part 14,
A first pass from the data storage unit 11 to the data processing unit 17;
A second path from the second device 12 to the data processing unit 17,
The third path from the third device 13 to the data processing unit 17 is switched. Here, the first path, the second path, and the third path can be referred to as dedicated transfer paths.

The data storage unit 11 includes an input terminal IN
A first in first out (FIFO) is used in which data supplied from the memory is written and read out in the written order. This FI
The FO is used as a reception FIFO, for example, in a link layer block of the IEEE1394 interface unit, and functions to receive packet-length data without interruption.

A data transfer device using Ethernet, which is a communication protocol for LAN, is also used for receiving packet-length data.

The capacity of the FIFO affects the gate scale and power consumption of, for example, a video processing system provided with a data transfer device. If the capacity of the FIFO can be reduced, the gate scale can be reduced and low power consumption can be achieved.

The data processing unit 17 includes, for example, a dynamic random access memory (Dynamic Random Access Memory).
y: DRAM) and stores data read from the data storage unit 11. From the viewpoint of the data storage unit 11, it is an external storage unit.

The second device 12 is, for example, a central processing unit (Central Processing Unit: CPU).
The arithmetic processing is performed on the data while using the data processing unit 17 that is M as a work area.

The third device 13 is, for example, a graphics accelerator (Graphic Accelerator).
Data processing unit (DRAM) 1 used as video memory
The transfer of the image data to the CPU 7 is performed without the intervention of the CPU.

Therefore, the data storage unit 11, the second device 12, and the third device 13 are connected to the data processing unit (DR
AM) 17 are shared.

As described above, the data storage unit 11 stores, for example, the reception FIFO in the video processing system conforming to IEEE1394.
When the data transfer device 10 is used as, for example,
The data supplied through the IEEE1394 serial bus and the input terminal IN must be able to be received without interruption. That is, it is necessary to prevent data loss in the data storage unit 11.

However, as described above, since the data processing unit (DRAM) 17 is shared with other devices such as a CPU, data transfer between the data storage unit (FIFO) 11 and the data processing unit (DRAM) 17 is performed. Is affected by other devices, and the communication speed from the outside to the data storage unit (FIFO) 11 via the input terminal IN cannot be guaranteed.

Therefore, in the data transfer device 10, the path switching unit 14 is provided in a stage preceding the data processing unit 17.
The path switching unit 14 includes the data storage unit 11, the second device 1,
An arbitration unit for arbitrating access from the second and third devices to the data processing unit;
The multiplexer 16 switches the first path, the second path, and the third path based on the arbitration.

Therefore, in the data transfer device 10, the path between the data storage unit 11 and the data processing unit 17 and other paths can be prevented from affecting each other. The path between other devices is provided separately from the path by the path switching unit 14.

The data transfer device 10 includes a data processing unit (DRAM) 17 output from a data storage unit (FIFO) 11.
Guarantees the maximum time from approval to response to a data transfer request to a certain time.

The arbitration unit 15 of the path switching unit 14 includes a data storage unit (FIFO) 11 to a data processing unit (DRAM).
The priority of access to 17 is higher than that of access from the second device 12 and the third device 13.

The arbitration unit 15 of the path switching unit 14
Is a data storage unit (FIFO) 11, a second device 12, or a third device 1 for a data processing unit (DRAM) 17.
3 determines the maximum value of the continuous occupation time of the path associated with the access from 3.

Next, a second embodiment will be described with reference to FIG. The second embodiment is a video data transfer system 40 as shown in FIG.

The video data transfer system 40 is, for example, a personal computer (PC) shown in FIG.
Provided inside. The video data transfer system 40 in the PC converts video data transmitted from the camera-integrated video tape recorder (hereinafter referred to as CAM) 5 shown in FIG. 7 via the 1394 bus 6 into a physical layer block (1394PH).
Y) Received via the link layer block (1394Link) 42 and transferred to the DRAM 23. And DRAM2
3 are subjected to various video processing.

The video data transfer system 40 includes a physical layer block (1394PHY) 41, a link layer block (1394Link) 42, a CPU 21, a graphic processing unit 22 such as a graphics accelerator (Graphic Accelerator), and the like. DRAM 23 and ROM 24
And a path connection unit 25.

The path connection unit 25 includes the link layer block 42, the CPU 21, the graphic processing unit 22,
It is for connecting the RAM 23 with a plurality of paths,
It comprises a path switching unit 26, a multiplexer 27 and connection lines.

The physical layer block 41 initializes the 1394 serial bus 6, arbitrates the right to use the 1394 serial bus 6, and the like. Also, various control signals are communicated with the link layer block 42, and these signals are transmitted and received to and from the 1394 serial bus 6.

The link layer block 42 includes a 1394 link core (Link Core) section 420, a reception FIFO 421, a DMA controller / bus interface 422, and a transmission FIFO 4
23.

The CPU 21 takes out an application program for processing video data stored in the ROM 24 and executes the DRAM 23 as a work area.

The graphic processing unit 22 performs image processing on the video data in accordance with the execution of the video data processing application.

In the configuration shown in FIG. 2, in the case of receiving video data from the CAM 5, when the transfer is approved between the physical layer block on the CAM 5 side and the physical layer block 41, the packet length is changed. Is transferred without being deterred.

The video data passing through the 1394 bus 6 is
The data is supplied from the physical layer block 41 to the reception FIFO 421 via the 1394 link core unit 420 and stored.

The video data stored in the reception FIFO 421 is read out in the order of entry under the control of the DMA controller / bus interface 422 and transferred to the DRAM 23 via the path connection unit 25.

The path switching unit 26 constituting the path connection unit 25 includes an arbitration unit and a multiplexer, similarly to the path switching unit 14 shown in FIG. The arbitration unit of the path switching unit 26 arbitrates access to the DRAM 23 from the reception FIFO 421, the CPU 21, and the graphic processing unit 22. Based on the arbitration in the arbitration unit, the path switching unit 2
A multiplexer 6 switches the dedicated paths.

Therefore, in the video data transfer system 40, the path between the reception FIFO 421 and the DRAM 23 and other paths can be prevented from affecting each other. The path between other devices, for example, between the CPU 21 and the ROM 21 is provided separately from the path by the path switching unit 26.

The video data transfer system 40
By controlling the path allocation processing in the arbitration unit of the path switching unit 26, the DRAM output by the reception FIFO 421
The maximum time from acknowledgment to response to the video data transfer request to G.23 is guaranteed to a fixed time. As a result, it is possible to guarantee the maximum delay time from the approval to the response to the video data transfer request.

The video data transfer system 40
In the arbitration unit of the path switching unit 26, the reception FIFO 42
The priority of access to DRAM 23 from 1 is higher than that of access from other devices.

FIG. 3 shows a processing procedure in the arbitration unit based on the access priority. Here, the reception FIFO 42
1 is replaced with the priority device A, the CPU 21 with the normal device B, and the graphic processing unit 22 with the normal device C.

When a request is issued from a plurality of devices at the same time, which device is selected depends on the priority at that time. The initial state is, as shown in FIG.
Let A>B> C. In this state, A has the highest priority,
When A does not make a request, B is selected, and when neither A nor B makes a request, C is selected. The state indicating this priority is changed when a request from a certain device is approved.

First, the arbitration unit determines whether or not there is a request from the device in the initial state where the priority order is A>B> C ((1) in FIG. 4) (step S1). If not (YE
S) Go to step S2 and do not change the priority. If it is determined in step S1 that there is a request from the device (NO), the process proceeds to step S3.

Assume that a request has been issued from devices A and C at the stage of step S1 as shown in (2) of FIG. Then, according to the priority order A>B> C by the arbitration unit,
The request from device A is selected. This processing is confirmed in step S3. That is, it is confirmed whether the arbitration unit has selected A in accordance with the priority order. Here, the request from the device A is selected (YE
The process proceeds from step S) to step S4 to set the priority of device A to the lowest. Therefore, the priority order is B>C> A as shown in (2) of FIG.

Next, the process returns to step S1. Since the request from the device C remains, the process proceeds to step S3, and NO is determined in step S3 and the process proceeds to step S5.
In step S5, the priority order B in the case of (2) in FIG.
Since it is confirmed that C is selected according to C> A (YES), the process proceeds to step S6.

In step S6, the selected device C
, The priority of the device A is set to the highest, and the priority A>B> shown in (3) of FIG.
C is established.

Next, as shown in (4) of FIG. 4, when a request is issued only from the device B, the arbitration unit causes the device B to issue a request.
Is selected, the process proceeds to steps S1, S3, and S5, and the selection of device B is confirmed. Since the request is only from the device B, the device B is selected (YES) in step S5, and the process proceeds to step S6.
In FIG. 4, the priority of the selected device B is made the lowest, and the priority of the device A is made the highest.
(4), the priority order A>C> B is satisfied.

Next, as shown in FIG. 4 (5), when a request is issued only from the device A, the arbitration unit causes the device A to issue a request.
Is selected, the process proceeds to steps S1 and S3 to confirm the selection of the device A. And step S
4, the priority of the device A is set to the lowest order, and the priority C>B> A shown in (5) of FIG. 4 is established.

Next, the priority order C> B shown in (5) of FIG.
If the request is issued from the devices A, B, and C when> A, C is selected by the arbitration unit. Therefore, the process proceeds to step S1, step S3, and step S5. In step S5, it is confirmed that the device C is selected. In step S6, the priority of the device C selected is made the lowest, and Raise priority to the highest level,
The priority order A>B> C shown in (6) of FIG. 4 is satisfied.

Next, the process returns to step S1. Then, since requests from the devices A and B remain, the process proceeds to step S3. Since the arbitration unit selects the request from the device A according to the priority order A>B> C, the process proceeds from step S3 to step S4. Then, in step S4, the priority of A is made the lowest, and the priority B> C shown in FIG.
> A is satisfied.

Next, the process returns to step S1. Here, since the request from the device B remains, the process proceeds to step S5 via step S3. The arbitration unit determines the priority B
Select the request of device B according to>C> A. Then, in step S6, the priority of the device B is set to the lowest, and the priority of the device A is set to the highest.
The priority order A>C> B shown in (8) is established.

By the series of processing shown in FIG. 3, A, B, C
The probability that each device is selected is 2: 1: 1,
The priority device A can secure at least a 50% right.

Generally, in the isochronous transfer performed by IEEE1394, as shown in FIG. 5, a transmission request transmission from a transmission side is received by a reception side, and a transmission acknowledgment is returned from the reception side to the transmission side. After the transmission side receives the transmission acknowledgment, data transmission starts. If the receiving side starts receiving data and then the transmitting side ends the transmission, the receiving side also ends the receiving, sends a receiving completion transmission to the transmitting side, and the transmitting side receives the receiving completion and receives this isochronous transmission. The transfer ends.
The arbitration unit performs the processing on the receiving side in FIG. 5 for each device while following the priority order.

The video data transfer system 40
In the arbitration unit of the path switching unit 26, the DRAM 23
The maximum value of the continuous occupation time of the path associated with the access from the reception FIFO 421, the CPU 21, and the graphic processing unit 22 to the path is determined.

As described above, the video data transfer system 40 can establish a path between the reception FIFO 421 and the DRAM 23 without being affected by communication of another device.

Further, even if the communication conflicts, the reception FI
It is possible to guarantee the time from the data transfer request from the FO 421 to the approval to the response. That is, the following two values can be guaranteed to be constant values.

The first value is obtained from the reception FIFO 421 to the DRAM
23 is the lowest value of the data transfer performance to the H.23. The second value is
This is the maximum delay time from a request for data transfer from the reception FIFO 421 to the DRAM 23 to a response.

Then, when these two values reach a certain value, during a short time during which the physical layer block 41 performs the packet communication, the data communication speed higher than the communication speed between the physical layer block 41 and the link layer block 42 is obtained. FIFO4 receive speed
When it is possible to guarantee between the DRAM 21 and the DRAM 23, the following effects can be obtained.

The capacity of the reception FIF0 can be made shorter than the packet length. Also, no matter what kind of communication is being performed on the internal bus, no FIFO overflow occurs, and no retry or packet loss occurs.

The same applies to the transmission FIFO, and its capacity can be made shorter than the packet length. Also, no FIFO underflow occurs.

As a secondary effect, it is possible to guarantee a fixed time from the end of communication in the physical layer block to the end of communication in the link layer block, that is, from the end of communication to the system. Can have a positive effect on the real-time performance of

In the first and second embodiments, the data transfer device and the video data transfer system having the hardware configuration have been described. Each step of the data transfer method is being executed.

A program stored on a recording medium such as a ROM and relating to the data transfer method of the present invention is
The data transfer device and the video data transfer system can be constructed by software by sequentially reading and executing the data by a PU or the like.

Further, as described above, the present invention relates to the IEEE
The application is not limited to the 1394 system, but can be applied to a system in which PCs are connected to each other, a system in which a PC is connected to a printer, and the like, which form a LAN using an Ethernet protocol.

In the first embodiment, the data processing section 17 may be not only a DRAM but also an arithmetic processing section for directly performing arithmetic processing on data.

[0091]

As described above, according to the present invention, the capacity of the FIF0 for transmission or reception can be made smaller than the maximum packet size that can be handled by the system, and the gate size of the system can be reduced. Or low power consumption.

Similarly, a plurality of reception FIFs 0 can be used for one reception FI
A system can be constructed without deteriorating performance with FO. In addition, since the data transfer performance of FIF0 and external storage can be guaranteed regardless of the operation of other devices, it is guaranteed that overflow and underflow of FIF0 will not occur even if access to external storage is concentrated. it can. Therefore, regardless of the size of FIF0, performance degradation and packet loss due to packet retries can be suppressed.

For example, the maximum time from the completion of data transfer between the physical layer block PHY of the IEEE1394 system and the FIF0 of the link layer block to the completion of data transfer between the FIF0 and the external storage (data transfer completion interrupt to the CPU). This can be guaranteed and usually shortened, which has a positive effect on the real-time performance of the system.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a data transfer device according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a video data transfer system according to a second embodiment of the present invention.

FIG. 3 is a flowchart illustrating a processing procedure in an arbitration unit based on an access priority;

FIG. 4 is a diagram illustrating an operation based on a priority order with respect to requests from a plurality of devices.

FIG. 5 is a transmission / reception transition diagram between a transmitting side and a receiving side in isochronous transfer.

FIG. 6 is a transmission / reception transition diagram between a transmitting side and a receiving side in asynchronous transfer.

FIG. 7 is a diagram illustrating a configuration of a specific example of a 1394 network system.

FIG. 8 is a diagram showing a connection relationship between a 1394 I / F board 4 and a PC main body 2 of the 1394 network system.

FIG. 9 is a diagram showing a state in which data received by a reception FIF0421 gradually accumulates in a 1394 I / F board 4 of the 1394 network system.

[Explanation of symbols]

1 data transfer device, 11 data storage device, 12 second device, 13 third device, 14 path switching unit,
15 arbitration unit, 16 multiplexer, 17 data processing unit, 21 CPU, 22 graphic processing unit, 23
DRAM, 24 ROM, 25 pass connection part,
26 path switching unit, 27 multiplexer, 40 video data transfer system, 41 1394 physical layer block, 4
2 1394 link layer block, 421 receive FIFO

Claims (19)

[Claims] 1. A data transfer apparatus for transferring data between a data storage means which is a device to which data is written and read and a data processing means shared by the data storage means and at least one other device. A path switching means for switching a data transfer path between the data storage means and the at least one other device and the data processing means, wherein the data storage means and the at least one other device are connected to the data processing means. A data transfer device, wherein a connection is made to each dedicated transfer path using the path switching means. 2. The path switching means for switching a data transfer path between the data storage means and a plurality of other devices, wherein the path is different from a path between the plurality of other devices. 2. The data transfer device according to claim 1, wherein: 3. The data processing unit is an external storage unit as viewed from the data storage unit, and writing of data from the data storage unit or the at least one other device to the external storage unit is performed by the path switching unit. 2. The data transfer device according to claim 1, wherein the data transfer is performed by controlling the assignment of each dedicated transfer path by using. 4. The data transfer apparatus according to claim 1, wherein a maximum time from an approval to a response to a data transfer request to said data processing means issued by said data storage means is guaranteed in a fixed time. 5. The arbitration unit for arbitrating access to the data processing unit from the data storage unit and at least one other device, wherein the path switching unit switches a path based on arbitration of the arbitration unit. The data transfer device according to claim 1, wherein: 6. The arbitration unit according to claim 5, wherein the priority of access from said data storage unit to said data processing unit is higher than the priority of access from said at least one other device. Data transfer device. 7. The arbitration unit determines a maximum value of a continuous occupation time of a path associated with an access from the data storage unit and at least one other device to the data processing unit. Data transfer device. 8. The data transfer device according to claim 1, wherein said data storage means is a device for reading data in the order in which the data was written. 9. IEEE 1394 or Ethernet (registered trademark)
2. The data transfer device according to claim 1, wherein data transfer is performed in a system using a protocol. 10. A data transfer method for transferring data between data storage means for writing and reading data and data processing means shared by the data storage means and at least one other device. A switching step of switching a data transfer path between the data storage unit and the at least one other device and the data processing unit, wherein a connection from the data storage unit and at least one other device to the data processing unit is provided. And a dedicated transfer path using the switching step. 11. An arbitration step for arbitrating access from said data storage means and at least one other device to said data processing means, wherein said switching step switches paths based on arbitration in said arbitration step. The data transfer method according to claim 10, wherein 12. The arbitration step according to claim 11, wherein priority of access from said data storage means to said data processing means is higher than priority of access from said at least one other device. Data transfer method. 13. The arbitration step according to claim 10, wherein a maximum value of a continuous occupation time of a path associated with an access from the data storage unit and at least one other device to the data processing unit is determined. Data transfer method. 14. An execution unit for transferring data between a data storage unit to which data is written and read and a data processing unit shared by the data storage unit and at least one other device. An arbitration step of arbitrating access to the data processing means from the data storage means and at least one other device; and the data storage means and the at least one other device based on arbitration in the arbitration step. A switching step for switching a data transfer path between a device and the data processing means, wherein a connection from the data storage means and at least one other device to the data processing means is transferred using the switching step. A program for causing an arithmetic processing unit to execute processing to be a path. 15. The arbitration step according to claim 14, wherein priority of access from said data storage means to said data processing means is higher than priority of access from said at least one other device. Of the program. 16. The arbitration step according to claim 14, wherein a maximum value of a continuous occupation time of a path associated with an access from said data storage means to said data processing means and at least one other device is determined. Program. 17. An execution unit for transferring data between a data storage unit to which data is written and read and a data processing unit shared by the data storage unit and at least one other device. A arbitration step of arbitrating access from the data storage means and at least one other device to the data processing means; and a data storage means based on the arbitration in the arbitration step. And a switching step of switching a data transfer path between the at least one other device and the data processing means, wherein the connection from the data storage means and at least one other device to the data processing means is switched A program for causing an arithmetic processing unit to execute processing for each dedicated transfer path using a process. A recording medium that records a ram. 18. The arbitration step of the program, wherein the priority of access from the data storage means to the data processing means is higher than the priority of access from the at least one other device. Item 17
A recording medium on which the program described above is recorded. 19. The arbitration step of the program, wherein a maximum value of a continuous occupation time of a path accompanying an access from the data storage unit and at least one other device to the data processing unit is determined. Item 18. A recording medium recording the program according to Item 17.