JP2002288048A - One chip micro-controller and system thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a one chip micro-controller and a system thereof capable accurately diagnosing normality and abnormality of a memory. SOLUTION: After a logic part 2 of the micro-controller 1 writes a first check data 55H on an address for carrying out a diagnosis of an internal RAM 4, it writes a second check data AAH on a reversal address in which the highest level bit from the lowest level bit of the diagnosis address are reversed every by one bit. Thereafter, a check data written in the diagnosis address is read out and it is judged whether or not the read out check data is the first check data 55H.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a one-chip microcontroller having a processor and a memory in the same semiconductor chip and a system thereof, and more particularly to a one-chip microcontroller capable of accurately diagnosing a state of a memory and a system thereof. .

[0002]

2. Description of the Related Art Conventionally, when controlling a system requiring high safety such as railway traffic, it has been practiced to improve the reliability of the system by using, for example, a bus synchronous double system device. The bus synchronous dual system includes, for example, two C buses connected to an external memory or the like and operating in synchronization with each other.
PU (Central Processing Uni)
t) and one fail-safe verification circuit connected to the bus connecting the CPU and the external memory.

The failure diagnosis of the external memory in the bus synchronous duplex system having such a configuration is performed by writing and reading memory check data to and from the external memory by the CPU. That is, when the CPU reads / writes the memory check data from / to the external memory, the fail-safe verification circuit fetches the memory check data flowing through the bus of each system, and if the fetched data of each system matches. It is determined that the external memory is normal, and if they do not match, the external memory is abnormal.

[0004]

The recent LS
With the development of I technology, high integration of semiconductor circuits has become possible, and a one-chip microcontroller in which a CPU, a memory, and various peripheral functions have been integrated in one chip has been realized. However, in the one-chip microcontroller, since the CPU and the memory are formed in the same chip, the data flowing on the bus cannot be directly taken out, and the method applied to the bus synchronous dual system as described above. Can not diagnose the memory failure. Therefore, for example, even when the CPU cannot access the address specified and accesses another address, such a failure cannot be found.

The present invention has been made in view of the above circumstances, and has as its object to provide a one-chip microcontroller capable of accurately diagnosing a normal or abnormal state of a memory and a system thereof.

[0006]

For this reason, the present invention according to a first aspect of the present invention provides a one-piece semiconductor device having a memory for storing data for each address and a processor operating by accessing the memory in the same semiconductor chip. In the chip microcontroller, the processor writes first check data to an address for performing a diagnosis of the memory, and then writes a second check data different from the first check data to at least one address different from the diagnostic address. Data write means, check data read means for reading check data written to the diagnostic address, and whether the check data read by the check data read means matches the first check data written to the diagnostic address Judge
A determination unit that determines that the state is normal when the values match and determines an abnormality when the values do not match.

In such a configuration, if the processor cannot correctly access the diagnostic address of the memory, the check data read from the diagnostic address does not match the first check data written to the diagnostic address. Further, in the invention according to claim 2, the check data writing means writes the second check data to an address obtained by inverting any one bit of the diagnostic address.

In such a configuration, when two predetermined address lines out of adjacent address lines for designating a memory address come into contact with each other, the processor mistakenly accesses another address as a diagnostic address and accesses the address. It will be possible to discover such memory abnormalities. Further, in the invention according to claim 3, the check data writing means writes the second check data into a plurality of addresses obtained by inverting a least significant bit to a most significant bit of the diagnostic address one bit at a time. did.

In such a configuration, when any two address lines out of adjacent address lines for designating a memory address come into contact with each other, the processor may mistakenly access another address as a diagnostic address and access it. You will be able to discover memory anomalies. Claim 4
In the invention described in the above, after it is determined that the determination result based on the first check data is normal, the diagnostic address and the check data to be written to the at least one address are replaced and written, and check data is written from the diagnostic address. The read check data is configured to determine whether the read check data matches the second check data.

In this configuration, the processor writes the first check data to the diagnostic address and then writes the second check data to at least one address different from the diagnostic address. Then, it is determined whether or not the check data read from the check address is the first check data. Next, the processor writes the second check data to the diagnostic address, and then writes the second check data to the diagnostic address.
First check data is written to two addresses. Then, it is determined whether the check data read from the check address is the second check data.

According to a fifth aspect of the present invention, there is provided the two one-chip microcontrollers according to the first to fourth aspects, which operate in synchronization with each other, and the processor of each controller is determined to be coincident by the determination means. When the check data read from the diagnostic address and the original data stored at the diagnostic address are output to the other controller, the check data and the original data input from the other output means are A check unit that checks each of the check data and the original data read from its own diagnostic address, and determines that the data is normal if the data matches and is abnormal if the data does not match.

With this configuration, it is possible to confirm whether the diagnostic function of the other processor is normal by comparing the check data read by itself with the check data read by the other processor. Also, by comparing the original data of the own diagnostic address with the original data of the other diagnostic address, it becomes possible to confirm whether or not the processors have diagnosed the same address.

[0013]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing one embodiment of a one-chip microcontroller according to the present invention. In FIG. 1, a one-chip microcontroller 1 includes a processor 3 having a logic unit 2, a RAM 4 as a memory for storing data for each address, and an I / O port 6 for exchanging data with an external device 5. And are provided in the same semiconductor chip.

The logic unit 2, RAM 4, and I / O port 6 are electrically connected by an internal bus 7.
The logic unit 2 controls the operation of the controller 1 by accessing the RAM 4 and processing data stored in the RAM 4, and also controls the operation of the RAM 1 as described later.
Diagnose 4

FIG. 2 is a conceptual diagram of the RAM 4 before diagnosis, and FIG. 3 is a conceptual diagram of the RAM 4 during diagnosis. For example, it is assumed that the RAM 4 has addresses 0000b to 1111b in which 8-bit data can be written, as shown in FIGS. The operation of the logic unit 2 when diagnosing, for example, the address 0110b in the RAM 4 will be described with reference to the flowcharts of FIGS. 3, 4, and 5.

In step 1 (indicated by S1 in the figure, the same applies hereinafter), it is determined whether or not address data has been written to the diagnostic address 0110b. If the result of the determination is YES, the operation proceeds to the operation of step 2; if NO, the operation proceeds to the operation of step 3 without performing the operation of step 2. In step 2, the diagnostic address 0110b
Is moved to, for example, a save address 1010b.

In step 3, the diagnostic address 011
0b is written with the first check data 55H (H is 16
Hex). In step 4, the diagnostic address 01
Inversion address 011 in which the least significant bit of 10b is inverted
It is determined whether address data has been written to 1b. If the result of the determination is YES, the operation proceeds to the operation of step 5, and if NO, the operation proceeds to the operation of step 6 without performing the operation of step 5.

In step 5, the inverted address 011
The address data written in 1b is moved to, for example, a save address 1001b. In step 6, the second check data AAH is written to the inverted address 0111b. In Steps 7 to 15, the inversion address 0100b obtained by inverting the second bit from the least significant bit of the diagnostic address 0110b, the inversion address 0010b obtained by inverting the third bit, and the inversion address 1110b obtained by inverting the most significant bit are described in Step 4 respectively. The same operation as Step 6 is performed.

As described above, steps 3, 6, 9, 9, and 15 function as a check data writing unit. In step 16, the check data written in the diagnostic address 0110b is read. Thus, step 16 functions as the check data reading means.

In step 17, the address data moved to the save address is written back to the original address. In step 18, it is determined whether the check data read in step 16 is the first check data 55H. Thus, step 18 functions as a determination unit.

If the check data read out in the operation of step 18 is not 55H, it is determined in step 19 that the RAM 4 is abnormal, and after the controller 1 is operated on the safe side, all processing is stopped. If it is determined in the operation of step 18 that the read check data is 55H and the RAM 4 is normal, the data to be written to the diagnostic address 0110b is replaced with the second check data A
AH, inverted address 0111b, 0100b, 0010
b. The diagnostic operation of the address 0110b is performed using the data to be written to 1110b as the first check data 55H.
In this operation, the first check data 55H is replaced with the second check data AAH and the second check data AAH is replaced with the first check data 55H in steps 1 to 19, so that the operation flowchart is omitted.

Thereafter, all addresses in the RAM 4 are similarly diagnosed based on the first check data and the second check data. As described above, the diagnostic address 01
After the first check data 55H is written in 10b, the inverted addresses 0111b, 0100b, 0010b, 11
Since the second check data AAH is written in 10b and then the check data read from the diagnostic address 0100b is determined to be the first check data 55H, for example, any one of the address lines adjacent to the diagnostic address When the two contacts, the logic unit 2 can reliably detect an abnormality in the RAM 4 that occurs relatively frequently, such as accessing the diagnostic address 0110b by mistake.

Also, as in this embodiment, 55H and AAH
With this configuration, it is possible to confirm whether data 0 and 1 can be written to all the memory cells at the diagnostic address 0110b. still,
In this embodiment, the check data 55H and the AAH are exchanged for diagnosis. However, the two check data may be data having different contents, and the diagnosis may be performed without exchanging the two check data. Good. In this case, the diagnosis is performed for the purpose of finding an abnormality in the address line that specifies the address of the RAM 4.

The inverted address is an address obtained by inverting the least significant bit to the most significant bit of the diagnostic address one bit at a time. However, if at least one address is different from the diagnostic address, the type of the inverted address is Not exclusively. The write operation of the check data to the inverted address is performed sequentially from the address obtained by inverting the least significant bit of the diagnostic address. However, the check data may be written in any order.

Further, a configuration is provided in which a dedicated save address for saving the address data of the diagnostic address and the inverted address is provided. However, the logical unit 2 writes data other than the diagnostic address and the inverted address without providing the save address. It is also possible to adopt a configuration in which addresses not found are sequentially searched and address data is individually saved. FIG. 6 is a block diagram showing an embodiment of a one-chip microcontroller system according to the present invention using the above-described one-chip microcontroller.

Referring to FIG. 6, the one-chip microcontroller system 8 includes two one-chip microcontrollers 9 and 10 having the same configuration and operating in synchronization with each other. One-chip microcontroller 9,
Reference numeral 10 denotes processors 17 and 18 including logic units 11 and 12, synchronization units 13 and 14, and matching units 15 and 16, and RAMs 19 and 20 as memories having the same configuration as the first embodiment.
And an I / O port 2 for exchanging data with the external device 21
2 and 23 are provided in the same semiconductor chip.

The logic units 11 and 12 of the controllers 9 and 10, the synchronization units 13 and 14, and the comparison units 15 and 16.
Are electrically connected by two-way transmission lines, respectively.
Communication is possible. The logic units 11 and 12 perform arithmetic processing to control the operation of the microcontrollers 9 and 10 of the own system, similarly to the logic unit 2 described above, but input data to be processed from other systems and input them. After confirming that the data matches the data to be processed by the own system, processing of the data is started. In addition, the self-system RAMs 19 and 20 are diagnosed as described later.

The synchronizing units 13 and 14 output the interrupt signal to each other and synchronize with the other system based on the interrupt signal. Thus, the two microcontrollers 9 and 10 in FIG. 6 operate in synchronization. Collation unit 1
Reference numerals 5 and 16 output check data read from the diagnostic address to each other to check whether the check data of the own system is normal, and also check data and check data input from the other system. The check data read from the system diagnostic address is collated. In addition, in order to confirm that the same diagnostic address has been diagnosed by the own system and the other system, the address data of the diagnostic address of the own system is mutually output to the other system, and the address data input from the other system is automatically compared with the address data input from the other system. Check with the address data of the system diagnostic address.

The processors 17 and 18 having such a configuration are described.
The RAMs 19 and 20 and the I / O ports 22 and 23 are electrically connected by internal buses 24 and 25. Next, the operation of the matching unit 15 of the one-chip microcontroller 9 will be described with reference to the flowcharts of FIGS. Here, the microcontroller 9 of one system is used.
Will be described, but the operation of the other microcontroller 10 is the same, and a description thereof will be omitted. The operations of the logic unit 11 in steps 20 to 38 in FIGS. 7 and 8 are the same as the operations in steps 1 to 19 in FIGS. Furthermore, in the present embodiment, a case will be described in which the diagnostic address is set to 0110b, as in the above-described embodiment.

In step 39, the first check data 55H read in step 35 is compared with the collation unit 16 of the other system.
Output to In step 40, the collation unit 16 of the other system
Input the first check data. In step 41, it is determined whether the first check data input from the collation unit 16 of the other system is 55H. As a result of the determination, YE
In the case of S, the process proceeds to the operation of Step 42, and in the case of NO, the process proceeds to the operation of Step 46 described later.

At step 42, the contents of the first check data input from the collation unit 16 of the other system at step 40, and at step 35 the logic unit 11
It is determined whether or not the contents of the first check data read from b match. If the result of determination is YES, the operation proceeds to the operation of step 43, and if NO, the operation proceeds to the operation of step 46 described later.

In step 43, the address data written back to the diagnostic address 0110b in step 36 is read, and the address data is output to the collation unit 16 of the other system. Thus, steps 39 and 43 function as an output unit. In step 44, address data is input from the collation unit 16 of the other system.

In step 45, the collation unit 16 of the other system
Then, it is determined whether or not the address data input from the address data and the address data written back to the diagnostic address 0110b in step 36 match. As described above, steps 41, 42, and 45 function as a collating unit.

If it is determined that the data collated in steps 41, 42, and 45 do not match,
In step 46, the processor 18 of the other system is determined to be abnormal, and the failure information is transmitted to the logic unit 11. The logic unit 11 that has received the failure information transmits the control signal for operating the one-chip microcontroller 10 to the safe side to the logic unit 12 of the other system at the same time as operating the microcontroller 9 of the own system to the safe side. I do. Then, the logic units 11 and 12 stop all processing of the system 8.

If the address data of the own system and the address of the other system match in the operation of step 45 and it is determined that the processor 18 of the other system is normal, the data to be written to the diagnostic address 0110b is replaced with the second check data AAH and the inverted address. 01
The diagnostic operation of the processor 18 of the other system is performed using the data to be written to 11b, 0100b, 0010b, and 1110b as the first check data 55H. In this operation, the first check data 55H is transferred to the second
Since only the check data AAH and the second check data AAH are replaced with the first check data 55H, the operation flowchart is omitted.

Thereafter, diagnosis is performed for all the addresses in the RAM 19 in the same manner based on the first check data and the second check data. As described above, the configuration is such that the check data read by the own system and the check data read by the other system are collated by the processors 17 and 18, so that the diagnostic functions of the processors 18 and 17 of the other system are normal. You can check whether or not. Further, since the configuration is such that the address data of the diagnostic address of the own system and the address data of the diagnostic address of the other system are compared, the processor 17,
18 can check whether the same address has been diagnosed. Therefore, the other processor 1
The abnormalities 8 and 17 can be detected, and the diagnosis of the RAM can be performed more reliably.

[0037]

As described above, according to the first aspect of the present invention, it is possible to find a memory failure in which a processor cannot access a specified address and accesses another address. This makes it possible to accurately diagnose whether the memory is normal or abnormal.

According to the second aspect of the present invention, an abnormality in the memory which occurs relatively frequently, for example, when two predetermined address lines of adjacent address lines for designating an address of the memory come into contact with each other. Be able to discover. According to the third aspect of the present invention, it is possible to detect an abnormality in the memory such as a case where any two address lines out of adjacent address lines that specify an address of the memory are in contact with each other, and to detect a memory abnormality that occurs relatively frequently. Abnormalities can be reliably detected.

According to the fourth aspect of the present invention, since two types of check data are written to the diagnostic address to diagnose the memory, it is possible to find an abnormality in the memory such that data cannot be correctly written to the memory cell at the diagnostic address. Become like According to the invention according to claim 5, when the diagnostic function of the other processor has an abnormality, or when the other processor and the other processor have not diagnosed the same address, the abnormality of the other processor can be detected. . Therefore, the memory can be diagnosed more reliably.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a one-chip microcontroller according to the present invention.

FIG. 2 is a conceptual diagram of a RAM before diagnosis applied to the embodiment;

FIG. 3 is a conceptual diagram of a RAM during diagnosis applied to the embodiment;

FIG. 4 is an operation flowchart of a logic unit according to the embodiment.

FIG. 5 is an operation flowchart of the logic unit following FIG. 4;

FIG. 6 is a block diagram showing one embodiment of a one-chip microcontroller system according to the present invention.

FIG. 7 is an operation flowchart of a logic unit and a matching unit of the embodiment.

FIG. 8 is a flowchart of the operation of the logic unit and the matching unit following FIG. 7;

FIG. 9 is an operation flowchart of a logic unit and a collation unit following FIG.

[Explanation of symbols]

 1, 9, 10 One-chip microcontroller 2, 11, 12 Logic unit 3, 17, 18 Processor 4, 19, 20 RAM 15, 16 Collation unit

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) G11C 29/00 675 G11C 29/00 675M

Claims (5)

[Claims] A memory for storing data for each address;
A one-chip microcontroller comprising a processor operating by accessing the memory in the same semiconductor chip, wherein the processor writes first check data to an address for diagnosing the memory, A second address different from the first check data is assigned to at least one different address.
Check data writing means for writing check data; check data reading means for reading check data written to the diagnostic address; check data read by the check data reading means; first check data written to the diagnostic address And a determining means for determining whether or not the values match with each other, and determining that the values are normal when the values match and abnormal when the values do not match. 2. The one-chip device according to claim 1, wherein said check data writing means writes the second check data to an address obtained by inverting any one bit of the diagnostic address. Microcontroller. 3. The diagnostic data writing means according to claim 1, wherein the least significant bit to the most significant bit of the diagnostic address is 1
The one-chip microcontroller according to claim 2, wherein the second check data is written to a plurality of addresses that are inverted bit by bit. 4. A method according to claim 1, wherein after the determination result based on said first check data is determined to be normal, the check data to be written into said diagnostic address and said at least one address are replaced and written, and check data is written from said diagnostic address. The one-chip microcontroller according to any one of claims 1 to 3, wherein the read check data is configured to determine whether the read check data matches the second check data. 5. The two one-chip microcontrollers according to claim 1, which operate in synchronization with each other, wherein the processor of each controller reads out from the diagnosis address when the judgment is made by the judging means that they match. Output means for outputting the data and the original data stored at the diagnostic address to the other controller; and check data read from the diagnostic address of the check data and the original data input from the other output means And a collating means for collating with the original data and judging normal when there is a match and determining abnormal when there is no match, a one-chip microcontroller system characterized by comprising: