JP2000347948A - Memory check system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To detect a defect about address setting in a short time and to specify a defect occurrence place. SOLUTION: A CPU 32 sets 1st addresses being different from each other in accordance with each check object bit check the existence/absence of a defect in each bit of an address of a RAM 36 and writes 1st data being different from each other in each of the addresses. Next, the CPU 32 sets 2nd addresses obtained by changing the logical value of each check object bit as many as the number of check object bits and writes 2nd data being different from the 1st data in each of the addresses. Subsequently, the CPU 32 designates the 1st address, reads data from the RAM 36 and detects the existence/absence of a defect about address setting by comparing the written data with the read data.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a memory check method for checking the operation of a semiconductor memory mounted in a protocol analyzer or the like.

[0002]

2. Description of the Related Art In recent years, a digital circuit network has been developed with the progress of a highly information-oriented society. In particular, the Internet connection using an ISDN line and the use of a dedicated line by a provider have been rapidly progressing. A data collection device called a protocol analyzer monitors the transmission and reception of signals via such various lines and detects a failure. With the spread of the above-mentioned ISDN lines and the like, there is a strong demand for further improving the performance of the protocol analyzer, such as speeding up data processing and realizing processing of a plurality of channels.

In order to realize the high performance of the protocol analyzer as described above, semiconductor parts such as memories used for constructing the protocol analyzer have been reduced in weight and size, and those having a very narrow pin pitch have been used. It is becoming possible. Therefore, when a memory or the like is mounted, a defect such as a short circuit or non-contact is likely to occur in an address bus or a data bus.
Therefore, there is a need for a self-diagnosis function for diagnosing a memory failure in a memory check performed at the time of startup in a device such as a protocol analyzer itself.

[0004]

By the way, a memory check performed in a conventional electronic device such as a protocol analyzer is performed after a predetermined data is written in order from a head address to a last address of the memory when the device is started. This is done by reading the written data and comparing the written data with the read data. When a mismatch between the written data and the read data is detected, the user is notified of the check result by displaying “no good” or the like.

However, in such a checking method,
Although data was written to the entire memory space, it was effective for detecting internal defects in memory chips,
When the check result is displayed as "no good", there is a problem that it is difficult to identify the position where the address bus failure has occurred. Also, as the number of address buses increases, the memory space rapidly increases, and there has been a problem that it takes a long time to check if the memory capacity has recently increased.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has as its object to detect a failure relating to address setting in a short time and to specify a location where the failure has occurred. It is to provide a memory check method.

[0007]

In order to solve the above-mentioned problems, a memory check method according to the present invention sets a check target bit to a first logical value in order to detect a defective portion related to an address setting of a memory. A first data writing means for writing the first data to the memory by designating the first address, and a second data setting means for setting the check target bit to a second logical value different from the first logical value. A second data writing means for setting second addresses to write second data different from the first data to the memory, and after the writing of the second data to the memory is completed, Data reading means for reading data from a first address, and writing the data read by the data reading means and the first address It is compared with the first data and a determination means for determining whether the check target bit abnormal. If the logical value of the check target bit is switched and two different data are written to the memory, the data corresponding to the first written address is overwritten by the next written data. This means that the bit is fixed to "0" or "1", which indicates that the bit to be checked has an error. As described above, according to the present invention, an abnormality of one check target bit is determined by two data write operations and one data read operation, and a defect related to a partial address setting can be detected in a short time. it can. Further, since the presence / absence of a defect in the check target bit itself for switching the logical value can be directly detected, the position of the address bit in which the defect has occurred can be easily specified.

It is preferable that the apparatus further comprises target bit designating means for sequentially switching the check target bits in correspondence with the respective bits of the memory address. By sequentially switching the check target bits and detecting a defect of each check target bit, a defect relating to the address setting of the entire memory can be detected in a short time.

Further, the determination means detects two or more check target bits whose data read by the data read means coincide with each other when the check bit is sequentially switched by the target bit designating means. Accordingly, it is desirable to determine whether there is a short circuit between the check target bits. When two or more bits other than the check target bit are short-circuited to each other, data may be written to the same address as a result even if the address to which data is first written is made different. Therefore, when first data having different contents are sequentially written to different first addresses, by checking whether or not the same data is read from each address, a short circuit between two or more address bits is determined. Can be detected. in this way,
According to the present invention, by detecting that two or more pieces of read data match, it is possible to detect a defect due to short-circuiting of an address bit. The short-circuit location can be easily specified.

It is preferable that the apparatus further comprises a judgment result notifying means for notifying information on the check target bit for which an abnormality has been judged by the judging means. By notifying the user of the information on the check target bit, for example, by display or the like, each user can easily know the position where the defect has occurred.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a protocol analyzer according to an embodiment to which the memory check method of the present invention is applied will be described in detail with reference to the drawings. FIG. 1 is a diagram illustrating a configuration of a protocol analyzer according to the present embodiment. The protocol analyzer shown in FIG. 1 includes a signal processing board 10, a plurality of monitor boards 20, a host processing unit 30.
It is comprised including.

The signal processing board 10 is connected to one or a plurality of physical lines, establishes synchronization with a signal received through the line, and uses this frame for data having a frame structure. Extraction is performed, and bit strings of data are extracted for data having no frame structure. The data extracted in this way is output to the measurement data collection bus 90. Lines connected to the signal processing board 10 include a dedicated line and a serial line such as RS232C in addition to a switched line such as an ISDN line or a packet line. Used.

The monitor board 20 includes the signal processing board 10
By extracting predetermined data to be collected from various data output to the measurement data collection bus 90 from the server and performing data collection processing, and sequentially storing the collected data as needed, the Make a time record.

The host processing unit 30 receives data collected by using the monitor board 20, converts the data into a predetermined display format, and displays the result. The CPU 32, the ROM 34, and the RAM 36 And a display unit 38. In addition, these CPs
Each of the U32, the ROM 34, the RAM 36, and the display unit 38 is connected via a data bus 40 and an address bus 42.

The CPU 32 is connected to the monitor board 20 via the host-side CPU bus 92, reads the collected data stored in the monitor board 20, and converts the read collected data into a display format designated by the user. Then, a monitor image converted to is created and displayed on the screen of the monitor display unit 38.

The ROM 34 stores various programs such as a data processing program executed by the CPU 32. R
The AM 36 stores various board information in the protocol analyzer, system information for controlling the entire protocol analyzer, data collected from a line connected to the signal processing board 10, and executes various programs by the CPU 32. Includes the work area when doing.

The protocol analyzer of the present embodiment has such a configuration. Next, the CPU 32 included in the host processing unit 30 when the protocol analyzer is started up.
Will be described in the case of checking whether there is a defect regarding the address setting of the RAM 36.

For example, in the RAM 36 of this embodiment, the bus width of the data bus 40 is 16 bits, and the least significant bit of the address is fixed to "0", and data is input / output in units of 16 bits (2 bytes). Shall be. ROM3
By executing the self-diagnosis program stored in the CPU 4 by the CPU 32, a defect check relating to the address setting of the RAM 36 is performed. In this case, the CP
U32 corresponds to first and second data writing means, data reading means, determination means, and target bit designation means, and the CPU 32 and the display unit 38 correspond to determination result notification means. In the case of a defect relating to the address setting of the RAM 36, the address terminal of the RAM 36 or each bit line of the address bus 42 is connected to a fixed potential electrode so that a specific address bit has a fixed logical value (“0” or “1”). And two or more address terminals of the RAM 36 and two or more bit lines of the address bus 42 are short-circuited and these two or more address bits are always set to the same logical value. .

FIG. 2 is a flowchart showing an outline of an operation procedure for specifying a defective portion related to the address setting of the RAM 36. First, the CPU 32 sets different first addresses corresponding to the respective bits to be checked in order to check the presence or absence of a defect for each bit of the address of the RAM 36, and also sets different first addresses to the respective addresses. 1 is written (step 100).

Next, the CPU 32 sets the second address in which the logical value of each check target bit is changed by the number of check target bits, and writes the first data written in the above-described step 100 to each address. The second data different from the above is written (step 101). A case will be described below where all of the second data prepared for the number of bits to be checked are set to the same value, but they may be set to different values.

Next, the CPU 32 reads data from the RAM 36 by designating the first address set in step 100 (step 102), and reads out the read data and the data written in each address in step 101. By comparing the RAM 36
It is determined whether or not each check target bit is defective with respect to the address setting (step 103). And CPU3
2 displays this determination result on the screen of the display unit 38 and, when there is a defect, also displays information for specifying the defective portion (step 104).

FIG. 3 is a flowchart showing a detailed operation procedure for specifying a defective portion related to the address setting of the RAM, and corresponds to the operation procedure of step 100 shown in FIG. For example, it is assumed that the position of the bit to be checked is moved from the lower bit of the address to the upper bit in order.

First, the CPU 32 sets an address check bit position x to an initial value "0" (step 200), and then adds 1 to the check bit position x (step 201). It is determined whether or not x matches the most significant bit position of the address (step 202). For example, when considering an (n + 1) -bit address, the n-th bit is the most significant bit position of the address, so it is determined whether or not x = n.

If the bit position x to be checked is not the most significant bit of the address, a negative determination is made in step 202 described above, and then the CPU 32 sets the address bit position y for setting the logical value to "1". A value obtained by adding 1 to the above-described check target bit position x (y = x +
1) is set (step 203). On the other hand, when the check target bit position x matches the most significant bit position of the address, the address bit position y is set to the minimum value of the check target bit position x in order to set the address bit position y cyclically. 1 "(step 20)
4). When considering an address of (n + 1) bits, the minimum value of the address bit position is “0”,
As described above, since the 0th bit of the address is fixed to “0” in order to handle data in units of 2 bytes, the minimum value of the check target bit position x (the value obtained by adding “1” to the initial value “0”) ) Is set as the address bit position y.

After the address bit position y is set in this way, the CPU 32 sets a write address (first address) in which only the address bit position y is set to "1" and the rest is set to "0". (Step 20
5) The check target bit position x is set as write data (first data) (step 206), and the RAM
36 is written (step 20).
7). Thereafter, the CPU 32 determines whether or not the check target bit position x matches the most significant bit position of the address (step 208). If the bit has not been moved to the most significant bit and the process returns to step 201, the operation of adding 1 to the check target bit position x and the subsequent steps are repeated. If the bit position x to be checked matches the most significant bit position of the address, the RAM 3
Then, the operation of writing the first data into No. 6 is completed.

As described above, the second data having the content of the check target bit position x is stored in the first address in which only the upper one bit of the check target bit position is set to "1" and the others are set to "0". Is written. Therefore, as shown in FIG. 4, a different address (an address in which only one bit higher than each check target bit position x becomes “1”) is set for each check target bit position x, and this check target bit position is set. Data writing is performed using the position x itself as write data.

FIG. 5 is a flowchart showing a detailed operation procedure for specifying a defective portion related to the address setting of the RAM, and corresponds to the operation procedure from step 101 shown in FIG. First, the CPU 32 sets the check target bit position x of the address to an initial value “0” (step 300), and then adds 1 to the check target bit position x (step 301). It is determined whether or not it matches the most significant bit position (step 303). Specifically, as described above,
Since the n-th bit is the most significant bit position of the address,
It is determined whether or not x = n.

If the bit position x to be checked is not the most significant bit position, a negative determination is made in step 302 described above, and then the CPU 32 sets the logical value to "1".
Is set to the value (y = x + 1) obtained by adding 1 to the above-described check target bit position x (step 303). On the other hand, if the bit position x to be checked matches the most significant bit of the address,
In order to cyclically set the address bit position y, the address bit position y is set to "1" which is the minimum value of the check target bit position x (step 304). The operations in steps 300 to 304 described above are basically the same as the operations in steps 200 to 204 shown in FIG. 3 performed to write the first data into the RAM 36.

After the address bit position y is set in this way, the CPU 32 sets the logic of both the address bit position y and the check target bit position x to "1", and the other logic values to "0". A second address is set (step 305), and second data (for example, 0xF) different from the first data already written in the RAM 36 is set.
FFFH (H represents a hexadecimal number) is written to the RAM 36 (step 306).

Next, the CPU 32 designates a first address in which only the logical value of the address bit position y is "1" and the other logical values are "0" as a read address (step 307), and the RAM 36 The data is read from the memory (step 308).

Next, the CPU 32 checks the current time.
Set target bit position x to expected value data and read
Judge whether the data set matches the expected value data
(Step 309). A match is an address
If the check target bits included are normal,
In addition, the CPU 32 determines that the check target bit position x is an address.
Judge whether it matches the most significant bit position of the
(Step 310). If they do not match, that is,
Bit positions to be checked in order from the upper bits of the address
If it is moved to the side and it does not reach the most significant bit
In this case, the process returns to step 301 described above,
The operation after adding 1 to the symbol bit position x is repeated.
You. Also, the bit position x to be checked is located at the top of the address.
If the bit position matches,
"Pass" character string indicating that the target bit is normal
Is displayed on the screen of the display unit 38 (step 311).
Complete a series of check operations normally. Also mentioned above
The data read from the RAM 36 in step 309
If the data does not match the expected value data,
A negative judgment is made in the comparison judgment of Step 309, and the display is made.
Display information on the location of the defect on the screen of the unit 38
(Step 312), a series of check operations are abnormally terminated.
Let it. For example, as information on the location where the defect occurred,
"ERROR: A _x [Y] ”is displayed. This
X in the character string is the bit position to be checked
Where y is the actual reading and see this display.
The user who knows the location of the defect based on these values
Can be

FIG. 6 shows that in the above-described check operation, R
FIG. 4 is a diagram for explaining an example of various addresses and data read / written to / from an AM 36. For example, the RAM 36
₃ is fixed to one logical value "1" due to short-circuiting of the address terminal or the like. In such a case, when writing the first data set the third bit of the address to be checked bit position, this third bit A ₃ if the normal "0"
But it is where the first data to the first address is to be written, in practice the first data is written to the address of the third bit A ₃ is "1". Therefore, the next time the same check target bit position is specified and the second address is set, the address set for writing the first data is specified again, and this address has already been written. The second data will be overwritten on the first data that has been written. Therefore, the first
In this case, the data read out by specifying the address does not match the expected value data, and a defective address setting of the RAM 36 is detected. At this time, “ERROR: A
₃ [0xFFFFH] ”is displayed and notified to the user, and the user who sees this can specify that the third bit of the address is a defective part.

FIG. 7 is a diagram for explaining another example of various addresses and data read / written to / from the RAM 36 in the above-described check operation. For example, R
The case where the first bit A ₁ and the third bit A ₃ of the AM 36 are short-circuited and always have the same logical value is shown. In such a case, after writing first data "0x0002H" check target bits as second bit A _2, when writing the first data "nH" check target bits as the n bits A _n , And the same first address “0 ... 01010” is designated, and data is overwritten. Therefore, the bit to be checked is changed to the second bit A
_Since the data read by setting to ₂ becomes “nH” and is different from the expected value data “0x0002H”, the RAM 3
No. 6 address setting failure is detected. At this time, a character string of “ERROR: A ₂ [nH]” is displayed on the display unit 38 and notified to the user.
And address bits A ₃ when the checked bit bit, the address bits A ₁ when the checked bit the n-th bit estimates that it is mutually the same logical value by short-circuiting And the location where the defect occurs can be specified.

As described above, in the present embodiment, the RAM 36
By setting each bit of the address as a check target bit and performing data writing twice and data reading once, it is possible to detect the presence or absence of a defect related to the address setting. The defect of the RAM 36 can be detected with a smaller number of times of reading and writing data as compared with the case of reading and writing data. In addition, the position of the bit to be checked when a defect actually occurs and the content of the data read at that time are displayed, and a user who has seen this can specify the location where the defect has occurred.

The present invention is not limited to the above embodiment, and various modifications can be made within the scope of the present invention. For example, in the above-described embodiment, the first address to which the first data is written is set such that the logical value of a bit higher than the bit position to be checked is “1” and the logical values of the other bits are “0”. However, the logic of each bit except the least significant bit of the address may be inverted to set the first address.

Further, in the above-described embodiment, the case where the address of the RAM 36 is specified by using both the upper side and the lower side of the address has been described. However, depending on how the RAM is used, one RAM is assigned to the upper byte of the address. And another lower RAM may correspond to another lower RAM. In such a case, when a failure related to one of the address settings occurs, only the first data stored in one of the RAMs is overwritten by the second data. . In the example shown in FIG. 6, the data read from the first address is “0xFF03H” when the address setting on the upper byte side is defective, and the first address when the address setting on the lower byte side is defective. The data read out from "0x00F
F ". Therefore, by displaying these values that are actually read out as a result of detecting a failure, the user can specify whether the failure occurrence location is on the upper byte side or on the lower byte side.

In the example shown in FIG. 7, if there is a defect in the address setting of the upper byte or the lower byte, the defect may not be detected depending on the first data to be written. For example, if the first data to be written first is “0x0002H” and the second data to be overwritten is “0x0006H”, and there is a defect on the upper byte side, the upper byte “0x00H” of “0x0002H” is defective.
"H" is the upper byte "0x00H" of "0x0006H"
Is overwritten, so that overwriting is not detected. Therefore, in such a case, it is necessary to devise a method of writing the first data having a unique value in each RAM in consideration of the connection form of the RAM. For example,
By setting each of “0x0202H” and “0x0606H” as the first data, it is possible to detect that the data has been overwritten.

In the present embodiment, the case where the host processor 30 of the protocol analyzer checks whether there is a defect relating to the address setting of the RAM 36 has been described, but the address setting of the RAM included in the monitor board 20 and the signal processing board 10 has been described. The present invention may be applied to the case of checking for the presence or absence of a defect related to. In this case, the R that can be accessed by the CPU 32 in the host processing unit 30
For the AM, the data may be directly read and written by the CPU 32 to detect the presence / absence of an address setting defect. For a RAM that cannot be directly accessed, the monitor board 20 or the signal processing board 1
0 may be used to detect a defect and send only the result to the host processing unit 30 to display the display result on the screen of the display unit 38.

In the above-described embodiment, the case where the present invention is applied to the protocol analyzer has been described. However, the present invention is applicable to the case where a defect relating to the address setting of a memory such as a RAM used in other electronic devices is detected. Can be applied.

[0040]

As described above, according to the present invention, the abnormality of one check target bit is determined by two data write operations and one data read operation. Time can be detected. Further, since the presence / absence of a defect in the check target bit itself for switching the logical value can be directly detected, the position of the address bit in which the defect has occurred can be easily specified.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a configuration of a protocol analyzer according to an embodiment.

FIG. 2 is a flowchart showing an operation procedure for specifying a defective portion related to an address setting of a RAM;

FIG. 3 is a flowchart showing a detailed operation procedure for specifying a defective portion related to an address setting of a RAM;

FIG. 4 is a diagram illustrating a specific example of first data written to a RAM and a first address specified at that time;

FIG. 5 is a flowchart showing a detailed operation procedure for specifying a defective portion related to the address setting of the RAM;

FIG. 6 is a diagram for explaining an example of various addresses and data read / written to / from a RAM.

FIG. 7 is a diagram for explaining another example of various addresses and data read / written to / from a RAM.

[Explanation of symbols]

 Reference Signs List 10 signal processing board 20 monitor board 30 host processing unit 32 CPU 34 ROM 36 RAM 38 display unit 40 data bus 42 address bus

Claims (4)

[Claims] In a memory check method for detecting a defective portion related to an address setting of a memory, a first address in which a check target bit is set to a first logical value is designated, and first data is written to the memory. A first data writing unit, a second address having the check target bit set to a second logical value different from the first logical value, and a second address different from the first data in the memory. Second data writing means for writing data of the following; data reading means for reading data from the first address of the memory after writing of the second data to the memory is completed; and the data reading means And compares the data read by the first data with the first data written to the first address. Memory check method, characterized in that it comprises the determining means whether there is an abnormality, the. 2. The memory check method according to claim 1, further comprising target bit designating means for sequentially switching the check target bits in correspondence with the respective bits of the memory address. 3. The check target according to claim 2, wherein the determination unit is configured to sequentially switch the check target bits by the target bit designating unit, and that the data read by the data read unit match two or more of the check targets. A memory check method, wherein the presence or absence of a short circuit between the check target bits is determined by detecting a bit. 4. The memory check method according to claim 1, further comprising: a determination result notifying unit that notifies information on the check target bit for which an abnormality has been determined by the determining unit.