JP2002283094A - Brazing filler metal - Google Patents

Brazing filler metal

Info

Publication number
JP2002283094A
JP2002283094A JP2001086674A JP2001086674A JP2002283094A JP 2002283094 A JP2002283094 A JP 2002283094A JP 2001086674 A JP2001086674 A JP 2001086674A JP 2001086674 A JP2001086674 A JP 2001086674A JP 2002283094 A JP2002283094 A JP 2002283094A
Authority
JP
Japan
Prior art keywords
brazing material
gold
thickness
alloy
void
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2001086674A
Other languages
Japanese (ja)
Inventor
Nobumoto Mori
伸幹 森
Chiyuu Inoue
注 井上
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sumitomo Metal Mining Co Ltd
Original Assignee
Sumitomo Metal Mining Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumitomo Metal Mining Co Ltd filed Critical Sumitomo Metal Mining Co Ltd
Priority to JP2001086674A priority Critical patent/JP2002283094A/en
Publication of JP2002283094A publication Critical patent/JP2002283094A/en
Pending legal-status Critical Current

Links

Abstract

PROBLEM TO BE SOLVED: To provide a brazing filler metal which does not produce the voids by an oxidized film admitted in a brazing filler metal made of a gold alloy. SOLUTION: This brazing filler metal is an alloy consisting of gold of Au/20Sn, Au/1 to 3.15Si, Au/12Ge as base and is subjected to gold plating of a thickness >=0.01 μm on its top and under surfaces.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は各種電子部品等の接
合に用いられるロウ材に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a brazing material used for joining various electronic parts and the like.

【0002】[0002]

【従来の技術】電子部品等の接合用として各種金属組成
からなるロウ材が広く用いられている。ロウ材は、一般
的に所望金属を所望割合に調合し、これを溶解して合金
化した後に薄板化し、その後圧延加工を施して所望厚み
とし、最後に打ち抜き加工をによって所定の形状に仕上
げられている。こうしたロウ材の中に金をベースとする
ものが一般的となっている。例えば、Au/20Sn合
金、Au/1〜3.15Si合金、Au/12Ge合金
である。これらはその目的や接合しようとする対象金属
等により適宜選択され、用いられている。
2. Description of the Related Art Brazing materials having various metal compositions are widely used for joining electronic parts and the like. The brazing material is generally prepared by mixing a desired metal in a desired ratio, melting and alloying the metal, thinning it, then rolling it to a desired thickness, and finally finishing it into a predetermined shape by punching. ing. Among these brazing materials, those based on gold are common. For example, an Au / 20Sn alloy, an Au / 1 to 3.15Si alloy, and an Au / 12Ge alloy. These are appropriately selected and used depending on the purpose, the target metal to be joined, and the like.

【0003】[0003]

【発明が解決しようとする課題】ところで、上記の合金
は温間加工により所定厚みまで圧延されるため、例えば
Au/20Sn合金では表面にSnの酸化膜層が形成さ
れ、そのためAu/20Sn合金が溶融した際にSnの
酸化膜層が残り、シールカバーを接合した場合にはボイ
ドが発生しリーク不良が発生するという問題があり、ま
た例えばAu/1〜3.15Si合金では表面にSiの
酸化膜層が形成され、Au/1〜3.15Si合金が溶
融した際にSiの酸化膜層が残り接合部にボイドが発生
し接合不良による熱伝導不足が生じるという問題があ
り、また例えばAu/12Ge合金では、表面にGeの酸
化膜層が形成され、Au/12Ge合金が溶融した際に
Geの酸化膜層が残るため接合部にボイドが発生し接合
不良による熱伝導不足が生じるという問題がある。本発
明は上記欠点の無いロウ材の提供を目的とする。
Since the above alloy is rolled to a predetermined thickness by warm working, for example, in the case of an Au / 20Sn alloy, a Sn oxide film layer is formed on the surface, so that the Au / 20Sn alloy is When melted, an Sn oxide film layer remains, and when the seal cover is joined, there is a problem that voids are generated and leak failure occurs. For example, in the case of Au / 1 to 3.15 Si alloy, oxidation of Si is caused on the surface. When a film layer is formed and the Au / 1 to 3.15 Si alloy is melted, an oxide film layer of Si remains and a void is generated in a bonding portion, resulting in insufficient heat conduction due to poor bonding. In the case of the 12Ge alloy, a Ge oxide film layer is formed on the surface, and when the Au / 12Ge alloy is melted, the Ge oxide film layer remains. There is a problem that occurs. An object of the present invention is to provide a brazing material that does not have the above-mentioned disadvantages.

【0004】[0004]

【課題を解決するための手段】上記課題を解決するため
本発明者は種々の検討を試みた結果、それぞれの合金の
表面に存在する酸化膜を除去した後、該合金表面に金メ
ッキを施せば上記課題は解決できることを見いだして本
発明に至った。
In order to solve the above-mentioned problems, the present inventor has made various studies. As a result, after removing an oxide film present on the surface of each alloy, gold plating is applied to the surface of each alloy. The present inventors have found that the above problems can be solved, and have reached the present invention.

【0005】すなわち、上記課題を解決する本発明のロ
ウ材は、金をベースとする合金であり、かつ少なくとも
その上、下面に金メッキが施されているものである。そ
して、金メッキの厚さは0.01μm以上であり、好ま
しくは5μm以下のものである。
That is, the brazing material of the present invention that solves the above-mentioned problems is an alloy based on gold, and at least the upper and lower surfaces thereof are plated with gold. The thickness of the gold plating is 0.01 μm or more, and preferably 5 μm or less.

【0006】[0006]

【発明の実施の形態】本発明のロウ材は、少なくともそ
の上、下面が金に覆われているため、耐酸化性に優れ、
その金に覆われている表面にはSn、Si、Ge等の添
加金属の酸化物は生成しない。そのため、本発明のロウ
材を用いて半導体装置を接合しても、上記添加金属の酸
化物による不良は実質的に発生しない。実質的としたの
は、多くてもロウ材の側面部には酸化皮膜が発生する
が、使用に支障は起きない範囲内の酸化物量になるから
である。
BEST MODE FOR CARRYING OUT THE INVENTION The brazing material of the present invention has excellent oxidation resistance because at least the upper and lower surfaces are covered with gold,
No oxide of an additional metal such as Sn, Si, or Ge is generated on the surface covered with gold. Therefore, even when the semiconductor device is joined using the brazing material of the present invention, the defect due to the oxide of the additional metal does not substantially occur. The reason why it is substantial is that an oxide film is generated on the side surface of the brazing material at most, but the amount of oxide is within a range that does not hinder use.

【0007】本発明のロウ材を得るには、所望金属を用
いて組成調合し、これを溶解して合金化した後に薄板化
し、その後圧延加工を施して所望厚みとし、この圧延物
の表面を、塩酸等を用いて処理し、該圧延物表面の酸化
皮膜を除去した後に、該圧延物を陰極として金メッキを
施し、その後打ち抜き加工等により所望形状にする。
[0007] In order to obtain the brazing material of the present invention, a composition is prepared using a desired metal, which is melted and alloyed, then thinned, and then rolled to a desired thickness. After removing the oxide film on the surface of the rolled material, gold plating is performed using the rolled material as a cathode, and then a desired shape is formed by punching or the like.

【0008】金メッキ層は表面酸化膜を除去したロウ材
表面の酸化を防ぐために用いられ0.01μm以上であ
れば有効である。金メッキの厚さが厚くなればなるほど
長期間放置しても酸化が防止できるが、あまり厚くなる
と生産性が低下する。また、組成ずれの可能性も高くな
るため、5μm以下とすることが好ましい。ロウ材に組
成ずれが起きると、ロウ材の融点が上昇するので好まし
くない。
The gold plating layer is used to prevent oxidation of the surface of the brazing material from which the surface oxide film has been removed, and is effective if the thickness is 0.01 μm or more. As the thickness of the gold plating increases, oxidation can be prevented even when the gold plating is left for a long period of time. However, when the thickness is too large, productivity decreases. Further, since the possibility of a composition deviation increases, it is preferable that the thickness be 5 μm or less. If the composition shift occurs in the brazing material, the melting point of the brazing material increases, which is not preferable.

【0009】[0009]

【実施例】次に実施例を用いて本発明をさらに説明す
る。
Next, the present invention will be further described with reference to examples.

【0010】(実施例1) Au/20Snの板厚0.
050mmのフォイルを脱脂し、塩酸でエッチングした
後、厚さ2μmの金メッキを施し、その後外形4mm,
内形3mm,厚さ0.030mmのワッシャ形状の金錫
ロウ材にプレス加工した。これを用いて半導体素子をセ
ラミックパッケージに封止し、その後X線透過法により
ボイド発生面積を調査した。その結果、ボイドは確認で
きなかった。なお、この大きさの従来のAu/20Sn
製ロウ材を用いたものボイド発生面積は2%程度であ
る。
(Embodiment 1) The thickness of Au / 20Sn is 0.1 mm.
After the 050 mm foil is degreased and etched with hydrochloric acid, it is plated with gold having a thickness of 2 μm.
It was pressed into a washer-shaped gold-tin brazing material having an inner shape of 3 mm and a thickness of 0.030 mm. Using this, the semiconductor element was sealed in a ceramic package, and then the void generation area was examined by an X-ray transmission method. As a result, no void could be confirmed. Note that a conventional Au / 20Sn of this size is used.
Using a brazing material, the void generation area is about 2%.

【0011】(実施例2) Au/20Snの板厚0.
050mmのフォイルを脱脂し、塩酸でエッチングした
後、厚さ0.2μmの金メッキを施し、その後2mm幅
のリボンに加工し2mm長さに切断して矩形状のロウ材
を得た。これを用いて半導体素子と半導体素子接合用の
メタライズ層を有する下層板を接合した。 その後X線
透過法によりボイド発生面積を調査した結果、ボイドは
確認できなかった。
(Example 2) Au / 20Sn sheet thickness
After the 050 mm foil was degreased and etched with hydrochloric acid, it was plated with gold having a thickness of 0.2 μm, then processed into a ribbon having a width of 2 mm and cut into a length of 2 mm to obtain a rectangular brazing material. Using this, a semiconductor element and a lower plate having a metallized layer for bonding the semiconductor element were joined. Thereafter, the void generation area was examined by the X-ray transmission method. As a result, no void could be confirmed.

【0012】(実施例3)Au/1Siの板厚0.04
0mmのフォイルを脱脂し、塩酸にてエッチングした
後、この表面に厚さ0.2μmの金Auメッキを施し、
その後1mm角 厚さ0.040mmの形状にプレス加
工して矩形形状のロウ材を得た。このロウ材を用いてヒ
ートシンクと基板とを接合した。その後、X線透過法に
よりボイド発生面積を調査した結果、ボイドは確認でき
なかった。なお、この大きさの従来のAu/1Si製ロ
ウ材を用いたものでは、ボイド発生面積は6%程度であ
る。
(Embodiment 3) Au / 1Si plate thickness 0.04
After the foil of 0 mm is degreased and etched with hydrochloric acid, the surface is plated with gold Au having a thickness of 0.2 μm.
Then, it was pressed into a shape of 1 mm square and 0.040 mm thick to obtain a rectangular brazing material. The heat sink and the substrate were joined using this brazing material. Then, as a result of investigating the void generation area by the X-ray transmission method, no void could be confirmed. In the case of using a conventional Au / 1Si brazing material of this size, the void generation area is about 6%.

【0013】(実施例4)Au/1Siの板厚0.04
0mmのフォイルを脱脂し、塩酸にてエッチングした
後、この表面に厚さ0.2ミクロンの金メッキを施し、
その後1.2mm幅のリボンに加工し3mm長さに切断
して矩形形状のロウ材を得た。これを用いて半導体素子
と半導体素子接合用のメタライズ層を有する下層板を接
合した。その後、 X線透過法によりボイド発生面積を
調査した結果、ボイドは確認できなかった。なお、この
大きさの従来のAu/1Si製ロウ材を用いたもので
は、ボイド発生面積は5%程度である。
(Embodiment 4) Au / 1Si plate thickness 0.04
After degreasing the 0 mm foil and etching with hydrochloric acid, this surface is plated with gold of 0.2 micron thickness,
Then, it was processed into a ribbon having a width of 1.2 mm and cut into a length of 3 mm to obtain a rectangular brazing material. Using this, a semiconductor element and a lower plate having a metallized layer for bonding the semiconductor element were joined. Then, as a result of investigating the void generation area by the X-ray transmission method, no void could be confirmed. In the case of using a conventional Au / 1Si brazing material of this size, the void generation area is about 5%.

【0014】(実施例5)Au/2Siの板厚0.02
5mmのフォイルを脱脂し、塩酸にてエッチングした
後、その表面に厚さ0.2μmの金メッキを施し、その
後5mm幅のリボンに加工し3mm長さに切断して矩形
形状のロウ材を得た。このロウ材を用いて半導体素子と
半導体素子接合用のメタライズ層を有する下層板を接合
した。その後、X線透過法によりボイド発生面積を調査
した結果、ボイドは確認できなかった。この大きさの従
来のAu/2Si製ロウ材を用いたものではボイド発生
面積は5%程度である。
(Embodiment 5) Au / 2Si plate thickness 0.02
A 5 mm foil was degreased and etched with hydrochloric acid, and the surface was gold-plated with a thickness of 0.2 μm, then processed into a 5 mm wide ribbon and cut into a 3 mm length to obtain a rectangular brazing material. . Using this brazing material, a semiconductor element and a lower plate having a metallized layer for bonding the semiconductor element were joined. Then, as a result of investigating the void generation area by the X-ray transmission method, no void could be confirmed. In the case of using the conventional Au / 2Si brazing material of this size, the void generation area is about 5%.

【0015】(実施例6)Au/3.15Siの板厚
0.050mmのフォイルを脱脂し、塩酸にてエッチン
グした後、その表面に厚さ0.2μmの金メッキを施
し、その後1.5mm角 厚さ0.040mmの形状に
プレス加工して矩形形状のロウ材を得た。このロウ材を
用いてヒートシンクと基板を接合し、その後X線透過法
によりボイド発生面積を調査した結果、ボイドは確認で
きなかった。この大きさの従来のAu/3.15Si製
ロウ材を用いたものでは、ボイド発生面積は6%程度で
ある。
(Example 6) A foil of Au / 3.15Si having a thickness of 0.050 mm was degreased and etched with hydrochloric acid, and then the surface thereof was plated with gold having a thickness of 0.2 μm and then 1.5 mm square. It was pressed into a 0.040 mm-thick shape to obtain a rectangular brazing material. As a result of bonding the heat sink and the substrate using the brazing material and then examining the void generation area by the X-ray transmission method, no void could be confirmed. In the case of using the conventional Au / 3.15Si brazing material of this size, the void generation area is about 6%.

【0016】(実施例7)Au/12Geの板厚0.0
50mmのフォイルを脱脂し、塩酸にてエッチングした
後、その表面に厚さ0.2μmの金メッキを施し、その
後4mm角 厚さ0.050mmの形状にプレス加工し
て矩形形状のロウ材を得た。このロウ材を用いてヒート
シンクと基板しを接合し、その後にX線透過法によりボ
イド発生面積を調査した。その結果、ボイドは確認でき
なかった。この大きさの従来のAu/12Ge製ロウ材
を用いたものでは、ボイド発生面積は5%程度である。
(Embodiment 7) Au / 12Ge plate thickness 0.0
A 50 mm foil was degreased and etched with hydrochloric acid. The surface was gold-plated with a thickness of 0.2 μm, and then pressed into a 4 mm square and 0.050 mm thick shape to obtain a rectangular brazing material. . Using this brazing material, the heat sink and the substrate were joined, and thereafter, the void generation area was examined by the X-ray transmission method. As a result, no void could be confirmed. In the case of using a conventional Au / 12Ge brazing material of this size, the void generation area is about 5%.

【0017】(実施例8)Au/12Geの板厚0.0
50mmのフォイルを脱脂し、塩酸にてエッチングした
後、その表面に厚さ0.2μmの金メッキを施し、その
後2mm幅のリボンに加工し2mm長さに切断して矩形
形状のロウ材を得た。このロウ材を用いて半導体素子と
半導体素子接合用のメタライズ層を有する下層板を接合
した。 その後、X線透過法によりボイド発生面積を調
査した。その結果、ボイドは確認できなかった。なお、
この大きさの従来のAu/12Ge製ロウ材を用いたも
のでは、ボイド発生面積5%程度となっている。
(Embodiment 8) Au / 12Ge plate thickness 0.0
A 50 mm foil was degreased and etched with hydrochloric acid, and the surface was gold-plated with a thickness of 0.2 μm, then processed into a ribbon having a width of 2 mm and cut into a length of 2 mm to obtain a rectangular brazing material. . Using this brazing material, a semiconductor element and a lower plate having a metallized layer for bonding the semiconductor element were joined. Then, the void generation area was investigated by the X-ray transmission method. As a result, no void could be confirmed. In addition,
In the case of using a conventional Au / 12Ge brazing material of this size, the void generation area is about 5%.

【0018】[0018]

【発明の効果】以上述べたように、本発明のロウ材で
は、その表面が金メッキで保護され、酸化されないた
め、ロウ材として使用したときに酸化物によるボイドの
発生は見られず、収率が向上する。よって、本発明は半
導体装置組み立てコスト等を低減することを可能とす
る。
As described above, since the surface of the brazing material of the present invention is protected by gold plating and is not oxidized, no voids due to oxides are observed when used as a brazing material, and the yield is low. Is improved. Therefore, the present invention makes it possible to reduce the cost of assembling a semiconductor device.

Claims (5)

【特許請求の範囲】[Claims] 【請求項1】 金をベースとする合金であり、かつ少な
くともその上、下面に厚さ0.01μm以上の金メッキ
が施されていることを特徴とするロウ材。
1. A brazing material comprising an alloy based on gold, and having at least an upper surface and a lower surface plated with gold having a thickness of 0.01 μm or more.
【請求項2】 金メッキの厚さが5μm以下のものであ
る請求項1記載のロウ材。
2. The brazing material according to claim 1, wherein the thickness of the gold plating is 5 μm or less.
【請求項3】 金をベースとする合金がAu/20Sn
であることを特徴とする請求項1または2記載のロウ
材。
3. The gold-based alloy is Au / 20Sn.
The brazing material according to claim 1, wherein
【請求項4】 金をベースとする合金がAu/1〜3.
15Siであることを特徴とする請求項1または2記載
のロウ材。
4. The gold-based alloy is Au / 1 to 3.
The brazing material according to claim 1, wherein the brazing material is 15Si.
【請求項5】 金をベースとする合金がAu/12Ge
であることを特徴とする請求項1または2記載のロウ
材。
5. The gold based alloy is Au / 12Ge
The brazing material according to claim 1, wherein
JP2001086674A 2001-03-26 2001-03-26 Brazing filler metal Pending JP2002283094A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2001086674A JP2002283094A (en) 2001-03-26 2001-03-26 Brazing filler metal

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2001086674A JP2002283094A (en) 2001-03-26 2001-03-26 Brazing filler metal

Publications (1)

Publication Number Publication Date
JP2002283094A true JP2002283094A (en) 2002-10-02

Family

ID=18942016

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2001086674A Pending JP2002283094A (en) 2001-03-26 2001-03-26 Brazing filler metal

Country Status (1)

Country Link
JP (1) JP2002283094A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012206142A (en) * 2011-03-29 2012-10-25 Nichia Corp Solder, semiconductor device using solder and soldering method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012206142A (en) * 2011-03-29 2012-10-25 Nichia Corp Solder, semiconductor device using solder and soldering method

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