JP2002280879A - Data latch device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a highly reliable data latch device capable of more surely excluding a malfunction caused by noises from an adjacently arranged circuit than in a conventional device. SOLUTION: Between a P channel transistor (23) of a data input tristate inverter (10) constructed on a semiconductor wafer by freely using thin film technology and one power source VDD, the circuit of P channel transistors (21 and 22) is interposed and between an N channel transistor (24) of the data input tristate inverter (10) and another power source (GND 27), the circuit of N channel transistors (25 and 26) is interposed. Then, the output of the circuit of N channel transistors (25 and 26) is turned on by ANDing a first write control signal (A) and a second write control signal (B), and the output of the circuit of P channel transistors (23 and 24) is turned on by ANDing an inverted signal (A<-> ) of the first write control signal and an inverted signal (B<-> ) of the second write control signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data latch device for holding a digital signal.

[0002]

2. Description of the Related Art FIG. 8 shows a conventional data latch device.
The data latch device 7 includes a data input tri-state inverter 1 of a data input unit, an output inverter 3 to which an output thereof is input, and a data holding tri-state inverter 4.

A first control signal E is supplied to an enable terminal of the data input tri-state inverter 1 via an output wiring 5. The other end of the output wiring 5 is connected to the first
Write control signal A and another second write control signal B
Is connected to the output of the AND circuit 2 which detects the logical product of.

Data holding tri-state inverter 4
Has an output connected to the input of the output inverter 3, an input connected to the output of the output inverter 3, and an enable terminal supplied with an inverted signal of the first control signal E as a second control signal NE. I have.

In the conventional data latch device, the held data is updated only when the first control signal E supplied from the output of the AND circuit 2 via the output wiring 5 becomes valid.

[0006]

As described above, by using the AND circuit 2, the first and second control signals E,
A countermeasure is taken against latch malfunction due to noise from a circuit arranged adjacent to the NE. However, if noise is present on the output side of the AND circuit 2, the latch data is erroneously updated. There is.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a highly reliable data latch device capable of more reliably eliminating a malfunction due to noise from a circuit arranged adjacently.

[0008]

According to a first aspect of the present invention, there is provided a data latch device, wherein an output of an output inverter is connected to an input of a data holding tri-state inverter, and an output is connected to an input of the output inverter. An input signal is supplied to an input of the output inverter through a data input tri-state inverter, and a write control signal of the data input tri-state inverter and an enable signal of the data holding tri-state inverter are controlled to convert the input signal into a data holding tri-state. What is claimed is: 1. A data latch device for holding a state inverter and outputting an output signal from an output of an output inverter, comprising: a P-channel transistor circuit between a P-channel transistor of a data input tri-state inverter built on a semiconductor wafer and one power supply Interposed,
The N-channel transistor circuit and the P-channel transistor are turned on by the logical product of a first write control signal and another second write control signal, and a signal obtained by inverting the input signal is output to an inverted holding signal, A P-channel transistor circuit is interposed between the P-channel transistor of the holding tri-state inverter and one power source, and an N-channel transistor circuit is interposed between the N-channel transistor of the tri-state inverter and the other power source. A channel transistor and the P channel transistor are turned on by a logical OR of an inverted signal of a first write control signal and an inverted signal of another second write control signal, and a signal obtained by inverting the output signal is an inverted holding signal. Characterized in that it is configured to output to

According to a second aspect of the present invention, there is provided a data latch device according to the first aspect, wherein a first and a second power supply are provided between a P-channel transistor of a data input tri-state inverter built on a semiconductor wafer and one power supply. A series circuit of P-channel transistors, and a series circuit of first and second N-channel transistors between the N-channel transistor of the data input tri-state inverter and the other power supply;
A first write control signal is supplied to the gate of the first N-channel transistor, another second write control signal is supplied to the gate of the second N-channel transistor, and the gate of the first P-channel transistor is supplied to the gate. An inverted signal of the first write control signal is supplied, and a gate of the second P-channel transistor is supplied with the inverted signal of the second write control signal. And a parallel circuit of third and fourth N-channel transistors between the N-channel transistor of the data holding tri-state inverter 12 and the other power supply. And the first N-channel transistor has the first gate
Supply the inverted signal of the write control signal, supply the inverted signal of the second write control signal to the gate of the fourth N-channel transistor, and supply the first write control signal to the gate of the third P-channel transistor Further, an inverted signal of the second write control signal is supplied to the gate of the fourth N-channel transistor.

According to a third aspect of the present invention, in the data latch device according to the second aspect, two data holding tri-state inverters sharing an input and an output are connected in parallel to the output inverter.

According to a fourth aspect of the present invention, in the data latch device, the output of the output inverter is connected to the input of the data holding tristate inverter, the output is connected to the input of the output inverter, and the data is input to the input of the output inverter. An input signal is supplied through an input tri-state inverter, and a plurality of write control signals of the data input tri-state inverter and an inverted signal of a specific write control signal among the plurality of write control signals are input as an enable signal of the data holding tri-state inverter. A data latch device for holding a signal in a data holding tri-state inverter and outputting an output signal from an output of an output inverter, wherein another data connected in parallel to share an input and an output with the data holding tri-state inverter Holding tri-state inverter Only, the data holding tristate inverter, characterized in that the said enabling signal an inverted signal of another signal from the data holding tristate inverters enable signal of the plurality of write control signals.

According to a fifth aspect of the present invention, in the data latch device according to the third or fourth aspect, the two data holding tri-state inverters are disposed on both sides of the output inverter. I do.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to FIGS. 1 to 7 and FIG. (Embodiment 1) FIGS. 1 to 3 and 9 show a data latch device according to Embodiment 1 of the present invention.

The data latch device shown in FIG. 1 includes a data input tristate inverter 10 to which a first write control signal A and another second write control signal B are input as control signals, and a data input tristate inverter. An output inverter 11 having an output connected to the input of the state inverter 10 and a data holding tristate inverter 12 having an output connected to the input and an output connected to the input of the output inverter 11. .

Data holding tri-state inverter 12
In this example, an inverted signal A # of the first write control signal A and an inverted signal B # of the second write control signal B are supplied as enable signals.

Data input tri-state inverter 10
Is configured as shown in FIG. 2, and an input signal is output when the first and second write control signals A and B are "1".

Referring to FIG. 2 in more detail, VDD1
6, P-channel transistors 21, 22, 23 are sequentially connected in series, and N-channel transistors 24, 25, 26 are sequentially connected to 3,
Are connected in series. The other end of the N-channel transistor 26 is connected to GND 27. The input signal X is input to the P-channel transistor 23 and the N-channel transistor 24, and the output signal Y is output from the connection between the P-channel transistor 23 and the N-channel transistor 24.

When the first and second write control signals A and B are both "1", inverted signals A #, B
￣ are both “0”. Therefore, P channel transistors 21 and 22 and N channel transistors 24 and 25 are all O
It becomes N state. At this time, if the input signal X is "1", the N-channel transistor 24 is turned on and the output signal Y is "0".
Is output, and if the input signal X is "0", the P-channel transistor 23 is turned on and the output signal Y is output "1". FIG. 3 shows the truth table of FIG.

In FIGS. 2 and 3, when the first write control signal A is "0" and the second write control signal B is "1", the P-channel transistor 22 and the N-channel transistor 25 The output signal Y becomes high impedance 28 regardless of the value of the input signal X.

Similarly, when the first write control signal A is "1" and the second write control signal B is "0", the P-channel transistor 21 and the N-channel transistor 26 are turned off and the output The signal Y becomes the high impedance 28 regardless of the value of the input signal X.

Data holding tri-state inverter 12
Is configured as shown in FIG. 9, and an input signal is output in a state other than when the first and second write control signals A and B are both "1".

FIG. 9 will be described in more detail.
5, the P-channel transistors 59 and 60 are connected in parallel, and the P-channel transistors 59 and 60 and the P-channel transistor 61 are connected in series. N from GND66
The N-channel transistors 63 and 64 are connected in parallel, and the N-channel transistors 63 and 64 and the N-channel transistor 6 are connected.
2 are connected in series. The input signal X is input to the P-channel transistor 61 and the N-channel transistor 62,
The output signal Y is output from the connection between the P-channel transistor 61 and the N-channel transistor 62.

When the first and second write control signals A and B are both "1", the inverted signals A # and B # are both "0". Therefore, P-channel transistors 59 and 6
The 0 and N-channel transistors 63 and 64 are all turned off, and the output signal Y becomes high impedance regardless of the value of the input signal X.

When the first write signal A is "0" and the second write signal B is "1", the P-channel transistor 59 and the N-channel transistor 63 are turned on. The channel transistor 62 is turned on, the output signal Y outputs “0”, and the input signal X becomes “0”.
If so, the P-channel transistor 61 turns ON and the output signal Y
Is output as 1.

When the second write signal A is "1" and the second write signal B is "0", the P-channel transistor 60 and the N-channel transistor 64 are turned on. The channel transistor 62 is turned on, the output signal Y outputs “0”, and the input signal X becomes “0”.
If so, the P-channel transistor 61 turns ON and the output signal Y
Is output as 1.

When the first and second write signals A and B are both "0", the P-channel transistors 59 and 60 and the N-channel transistors 63 and 64 are turned on. 62 turns ON and the output signal Y outputs "0". If the input signal X is "0", the P-channel transistor 61 turns ON and the output signal Y outputs "1".

Therefore, at the time of data hold, if the first
Even if one of the write control signal A or the second write control signal B becomes “1” due to the noise of the adjacent circuit, in this case, the output signal Y becomes the high impedance 28. As a result, a write malfunction of the latch can be prevented.

As described above, the series circuit of the P-channel transistors 21 and 22 is interposed between the P-channel transistor 23 and the VDD 16 of the data input tri-state inverter 10 constructed using the thin film technology on the semiconductor wafer.
Since the series circuit of the N-channel transistors 25 and 26 is interposed between the N-channel transistor 24 and the GND 27, the data input constructed using the thin film technology on the semiconductor wafer as in the conventional example shown in FIG. The AND circuit 2 is formed separately from the tri-state inverter, and the output wiring 5 such as when the output of the AND circuit 2 is connected to the enable terminal of the data input tri-state inverter via a wiring is eliminated. As a result, it is possible to improve the reliability of the latch by eliminating noise from adjacent circuits.

(Embodiment 2) FIG. 4 shows a data latch device according to (Embodiment 2) of the present invention. It is to be noted that components having the same functions as those of the first embodiment shown in FIG.

The data latch device according to the second embodiment differs from the first embodiment in that data holding tristate inverters 29 and 30 are connected instead of data holding tristate inverter 12. I have.

The data holding tristate inverter 29 and the data holding tristate inverter 30
Is a side view of the output inverter 11 constructed and arranged on the semiconductor wafer by making full use of thin-film technology, along the input / output direction of the output inverter 11 by making full use of thin-film technology on the semiconductor wafer. It is built and arranged towards.
More specifically, the data holding tristate inverters 30 and 29 are disposed on the right side as shown in FIG. 4 when the output is viewed from the input of the output inverter 11. The inputs and outputs of the data holding tristate inverters 30 and 29 are connected in parallel to each other. The enable terminal of the data holding tristate inverter 30 is supplied with the inverted signal A #, and the enable terminal of the data holding tristate inverter 29 is connected to the enable terminal of the data holding tristate inverter 29. Is supplied with the inverted signal B #.

Therefore, the input signal is output to the output of the data input tri-state inverter 10 only when both the first and second write control signals A and B become "1".
By using the data holding tri-state inverters 30, 29, even if one of the inverted signal A # or the inverted signal B # becomes "0" during data hold due to noise, in this case, ,
Even when one of the data holding tri-state inverters stops driving, the data holding tri-state inverter controlled by the other enable signal drives accurately, so that a malfunction in rewriting the held data due to noise can be prevented.

(Embodiment 3) FIGS. 5 to 7 show a data latch device according to (Embodiment 3) of the present invention. It is to be noted that components having the same functions as those of the second embodiment shown in FIG.

The data latch device according to the third embodiment is characterized in that the two data holding tri-state inverters 3
0 and 29 are only provided on both sides of the output inverter 11.

The difference in the operation of this arrangement will be described (Embodiment 2).
A description will be given in comparison with the case. FIG. 6 shows an arrangement of gate cells in the configuration of the second embodiment. In the second embodiment, the data holding tristate inverter 30,
29 is arranged in parallel and in the same direction as the output inverter 11, the noise 49 generated in the adjacent cell 48 disposed adjacent to the output inverter 11 causes the output of the output inverter 11 and the input of the data holding tristate inverter 29 to be connected. Of the wiring 50 to be connected and the wiring 51 connecting between the inputs of the tri-state inverters 30 and 29, the noise 49 rides on the wiring 51, and both held data are degraded by the noise to hold accurate data. You will not be able to do it.

On the other hand, in the case of the arrangement of the gate cells shown in FIG. 7 (Embodiment 3), data holding tristate inverters 30 and 29 are arranged in parallel to output inverter 11 and in the other direction. Therefore, adjacent cell 4
The noise 49 generated in 8 causes a wire 57 connecting the output of the output inverter 11 and the input of the data holding tristate inverter 29, and a wire 58 connecting the output of the output inverter 11 and the input of the data holding tristate inverter 30. In the case where the noise 49 rides on the wiring 58, the data held by the data holding tristate inverter 30 is deteriorated by the noise 49. However, the tri-state inverter 29 has noise 4
9, accurate data can be held.

The data input tristate inverter is supplied from the AND circuit 2 through the output wiring 5 as shown in FIG. 8, and only the data holding tristate inverter connected to the output inverter 11 is shown in FIG. Alternatively, even with a configuration in which they are simply connected in parallel as shown in FIG. 5, improvement in reliability can be expected as compared with the conventional example.

[0038]

As described above, according to the data latch device of the present invention, it is possible to prevent a malfunction in writing data due to noise in a write control signal and a malfunction in rewriting held data due to noise in wiring of a data holding circuit. Operation can be ensured, and the reliability is improved.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a data latch device according to a first embodiment of the present invention;

FIG. 2 is a transistor configuration diagram of the data input tri-state inverter of the embodiment.

FIG. 3 is a truth table of the data input tri-state inverter according to the embodiment;

FIG. 4 is a configuration diagram of a data latch device according to a second embodiment of the present invention;

FIG. 5 is a configuration diagram of a data latch device according to a third embodiment of the present invention;

FIG. 6 is an explanatory diagram of an arrangement of gate cells in the configuration of the data latch device according to the second embodiment of the present invention;

FIG. 7 is an explanatory diagram of the arrangement of gate cells in the configuration of the data latch device according to (Embodiment 3) of the present invention;

FIG. 8 is a configuration diagram of a conventional data latch device.

FIG. 9 is a configuration diagram of a data holding tri-state inverter according to the first embodiment of the present invention;

[Explanation of symbols]

Reference Signs List 10 data input tri-state inverter 11 output inverter 12, 30 data holding tri-state inverter A first write control signal A￣ inverted signal of first write control signal A B second write control signal B￣ second write control Inverted signal of signal B X input signal Y output signal 16 VDD (one power supply) 21, 22, 23, 59, 60, 61 P channel transistor 24, 25, 26, 62, 63, 64 N channel transistor 27 GND (the other side) Power supply) 29 Data retention tri-state inverter 48 Adjacent cell

Claims (5)

[Claims] An output of an output inverter is connected to an input of a data holding tri-state inverter, an output is connected to an input of the output inverter, and an input signal is supplied to an input of the output inverter via a data input tri-state inverter. And a data for controlling a write control signal of the data input tri-state inverter and an enable signal of the data retention tri-state inverter to retain the input signal in the data retention tri-state inverter and to output an output signal from an output of the output inverter. A latch device, comprising a P-channel transistor circuit interposed between a P-channel transistor of a data input tri-state inverter built on a semiconductor wafer and one power supply, and an N-channel transistor of the data input tri-state inverter and the other. Power supply An N-channel transistor circuit is interposed therebetween, and the N-channel transistor circuit and the P-channel transistor are turned on by a logical product of a first write control signal and another second write control signal to invert the input signal The output signal is output to the inverted holding signal, a P-channel transistor circuit is interposed between the P-channel transistor of the data holding tri-state inverter and one power supply, and the P-channel transistor circuit is interposed between the N-channel transistor of the tri-state inverter and the other power supply. Interposing an N-channel transistor circuit, turning on the N-channel transistor circuit and the P-channel transistor with a logical sum of an inverted signal of a first write control signal and another inverted signal of a second write control signal;
A data latch device configured to output a signal obtained by inverting an output signal to an inverted holding signal. 2. A data input tri-state inverter comprising a series circuit of first and second P-channel transistors interposed between a P-channel transistor of a data input tri-state inverter constructed on a semiconductor wafer and one power supply. A first write control signal is supplied to the gate of the first N-channel transistor, and a first write control signal is supplied to the gate of the first N-channel transistor. Another second write control signal is supplied to the gate of the N-channel transistor, an inverted signal of the first write control signal is supplied to the gate of the first P-channel transistor, and the gate of the second P-channel transistor is supplied to the gate of the second P-channel transistor. The P-channel transistor of the data holding tri-state inverter that has supplied the inverted signal of the second write control signal and one of the power supplies A third and fourth parallel circuit of P-channel transistors is interposed therebetween, and N of the data holding tri-state inverter 12 is connected.
Third and fourth N between the channel transistor and the other power supply.
An inverted signal of the first write control signal is supplied to the gate of the third N-channel transistor, and an inverted signal of the second write control signal is supplied to the gate of the fourth N-channel transistor. 2. The data according to claim 1, wherein a first write control signal is supplied to a gate of the third P-channel transistor, and an inverted signal of the second write control signal is supplied to a gate of the fourth N-channel transistor. Latch device. 3. The data latch device according to claim 2, wherein two data holding tri-state inverters sharing an input and an output are connected in parallel to said output inverter. 4. The output of the output inverter is connected to the input of a data holding tristate inverter, the output is connected to the input of the output inverter, and an input signal is supplied to the input of the output inverter via a data input tristate inverter. Holding the input signal in the data holding tristate inverter as a plurality of write control signals of the data input tristate inverter and an inversion signal of a specific write control signal among the plurality of write control signals as an enable signal of the data holding tristate inverter; A data latch device for outputting an output signal from an output of an output inverter, further comprising another data holding tri-state inverter connected in parallel so as to share an input and an output with the data holding tri-state inverter. State Inva The motor, the plurality of data latches apparatus enable signal an inverted signal of another signal is an enable signal of the data holding tristate inverters of the write control signal. 5. The data latch device according to claim 3, wherein said two data holding tri-state inverters are arranged on both sides of said output inverter.