JP2002279786A - Semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device provided with a CAM(content addressable memory) in which stable operation and low power consumption are realized. SOLUTION: A plurality of memory cells provided with a memory sections holding stored data and a comparing section comparing stored data with a retrieving input signal inputted to a pair of complementary data lines and forming a current path in accordance with uncoincidence output are provided at intersections of complementary data lines and word lines, a plurality of detecting lines in which a current path of the comparing section is connected to wired logic constitution in parallel to the word line are provided, and such circuits are used as its voltage discriminating circuit that a reference voltage circuit generating reference voltage by making to flow a current to a resistance means by a selecting signal, an amplifier comprising a differential circuit in which an operation current is made to flow by the selecting signal and which receives the reference voltage and signal voltage of the detecting line, and a current restricting means restricting respective current of a current path receiving voltage of the detecting signal and forming the reference voltage by voltage corresponding to uncoincidence output and a current path making to flow an operation current of the differential circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to a technology effective when used in a device having a content call memory.

[0002]

2. Description of the Related Art In the field of CMOS microprocessors, the operating frequency and the degree of integration have been improved by the miniaturization of processing technology and the improvement of circuits, and CMOS microprocessors whose operating frequency has reached 1 GHz have already been announced. I have. In order to obtain the maximum performance of these high-speed microprocessors, it is necessary to secure a memory bandwidth for instructions and data corresponding to the operation speed, and it is important to consider how a cache memory system can increase the execution memory bandwidth. Is the key to improving the execution performance of

Since a program executed on a high-speed microprocessor is generally described by a virtual address, it is necessary to convert a virtual address (VA) into a physical address (PA) in order to access a cache memory during program execution. Becomes Therefore, in order to realize a high-speed cache memory system, it is important to speed up the conversion from a virtual address to a physical address.

In order to speed up the conversion from the virtual address to the physical address, an address translation buffer (TLB: Tr
Functional memory called anslation look-aside buffer) is commonly used. This TLB is not usually required to have a large capacity like a cache memory, but a high hit rate is required. Therefore, if a high-speed TLB of a full associative system can be realized by a content addressable memory (CAM), the effect is large. Therefore, high-speed T
Implementation of LB is being attempted.

[0005] An example of such a TLB is 1996
IEE International Solid State Circuits Conference Digest of Technical Papers Pages 360-361 (IE
EE International Solid-State Circuits Conference
The circuit (Example 1) of Digest of Technical papers pp360-361) is known. In this conventional TLB circuit, a precharged match detection line is stored in an associative memory (CAM cell).
And a high-speed and low-power CAM comparison operation has been realized by devising a circuit for layering the match detection lines.

[0006]

SUMMARY OF THE INVENTION The inventors of the present invention use a differential type static circuit to eliminate the time required for precharging, use an accelerator, drive a coincidence detection line with a pulse, and use a current source of an amplifier. By using the coincidence detection line as the control signal, it was studied to reduce the current consumption by setting only the amplifier connected to the coincidence coincidence detection line to a completely activated state (Example 1). Further, by using a dummy entry that is always missed (or hit) during the comparison operation, the start timing of the differential amplifier is generated to prevent an increase in the timing margin and to increase the speed. 2) I did. In this case, low power can be achieved by using a static CMOS logic gate circuit as the coincidence detection circuit.

In the TLB circuit described in the above-mentioned document, a pair of coincidence detection lines is precharged and a virtual address (V
A) A match detection line where the data of the CAM cell does not match the CA
By adopting a dynamic operation of discharging in the M cell and layering the match detection lines, the virtual address (V
From the input of A), the virtual address (VA) is compared with the data of the CAM cell, and the time from when an entry storing the same data as the virtual address (VA) is detected is reduced. Also, the switches that hierarchically match the match detection lines are represented by P
It is composed of a channel type MOSFET, and since the mismatched global-match detection lines are not completely discharged, the time required for the precharge can be shortened and the power can be reduced.

However, since a differential amplifier is used as an amplifier for the coincidence detection line, it is necessary to provide two signal lines, a reference voltage line and a coincidence detection line, for each row of the memory array in one entry. There is a disadvantage that the area of the circuit becomes large. Furthermore, since these are arranged adjacent to each other, there is a concern about noise caused by coupling capacitance between wirings. In addition, since the P-channel MOSFET has a lower current driving capability than the N-channel MOSFET,
It is necessary to increase the gate width, which increases the load capacitance of the global match detection line. Further, as the number of bits to be compared increases, the change of the coincidence detection line becomes slow, and as a result, the comparison operation is delayed. Moreover,
In terms of power consumption, power is consumed because all amplifiers operate regardless of whether they match or mismatch.

In view of the above, C of the above-mentioned Study Example 2
In the AM, the timing margin is reduced by generating an enable signal for the match detection circuit by using a dummy entry. On the other hand, since the CMOS logic gate is used in the match detection circuit, the potential of the match detection line is set to the logic level of the CMOS gate. Until the threshold value is exceeded, the enable signal and the match detection signal cannot be output. Also, in terms of power consumption, it is difficult to reduce the amplitude of the coincidence detection line as described above, so that current consumption due to precharge increases. Further, it is necessary to increase the precharge time, which hinders a reduction in cycle time. Further, in order to solve the above problem, it is conceivable to reduce the amplitude of the coincidence detection line by using a differential amplifier to increase the speed even in the circuit as in the study example 1. Since all the differential amplifiers are operated in the same manner as in the first embodiment, the current consumption increases.

As described above, in the known technology and the study example, at the operating frequency currently required, the result of the dummy entry (always a miss or a hit) is used to make the activation signal of the amplifier and the enable of the word signal. Can not cope with speeding up. Even if the starting signal of the amplifier is generated from the clock, there is a power margin because the timing margin and all the amplifiers are started. For power requirements, the amplifier can be simplified by driving the match detection line with a large MOS, but that results in an increase in the power of the match detection line. In the method of Study Example 1, the coincidence detection line is activated with a large current in order to achieve both the area of the CAM cell and the high speed. For this reason, the potential at the time of a mistake becomes high, and it is necessary to obtain a gain at a higher potential than the configuration of the differential amplifier.

As described above, in the circuit used in the study example 1,
Although the current consumption is reduced by using the coincidence detection line as the enable signal, this means that the amplifier does not operate unless the potential of the coincidence detection line becomes high, and it is not possible to cope with further high-speed operation. Further, when the load due to the number of associated bits or the like increases, the potential change of the coincidence detection line becomes slow, and the delay of the coincidence detection signal increases. In order to reduce the current consumption by using a single reference voltage, it is necessary to design with a sufficient margin so as not to malfunction due to fluctuations in the reference voltage due to power supply noise or voltage drop.

An object of the present invention is to provide a semiconductor integrated circuit device having a CAM that realizes stable operation and low power consumption. The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0013]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application. A memory unit having a pair of complementary input / output nodes and holding storage data written from the complementary data line by the word line selecting operation; and a storage unit configured to store the storage data and a search input signal input to the pair of complementary data lines. A plurality of memory cells each including a comparison unit that forms a current path in response to a mismatch output are provided at intersections of a plurality of complementary data lines and word lines, and the current path of the comparison unit is parallel to the word lines. Is provided with a plurality of detection lines connected to a wired logic configuration, a reference voltage circuit that generates a reference voltage by flowing a current to the resistance means by a selection signal as a voltage determination circuit, an operating current flows by the selection signal, An amplifier including a differential circuit receiving the reference voltage and the signal voltage of the detection line; and a voltage corresponding to the mismatched output receiving the voltage of the detection signal. Current limiting means for limiting the respective currents of the formed current path and current path flowing an operating current of the differential circuit is used.

[0014]

FIG. 1 shows a CAM according to the present invention.
1 is a schematic circuit configuration diagram of one embodiment. Each circuit block of this embodiment is formed on a single semiconductor substrate such as single crystal silicon, though not particularly limited, by a known CMOS integrated circuit manufacturing technique.

A key (query) input signal as a search data input is set in a register included in the address bus driver. This search data input is, for example,
It is composed of a plurality of bits such as key 0 to key 63.
In this embodiment, a pair of comparison data lines corresponding to one bit among them, one detection line provided corresponding to the plurality of bits of search data input, and a match detection circuit corresponding thereto are exemplarily shown. Have been.

Although not particularly limited, in the address bus driver, a max register is provided for the search data input consisting of the plurality of bits. That is, the input of the search data line composed of a plurality of bits is masked with respect to the bit specified by the mask register, and is supplied to the comparison data line of the CAM. The mask register has a function of substantially invalidating the collation of a specific bit among the plurality of bits. For example, for the bit specified by the mask register, both the input signals transmitted to the comparison data line are set to low level. Thereby, the comparison logic output with the storage information of the memory cell MC of the corresponding CAM is always matched.

A memory cell composed of, for example, 256 × 4 columns is arranged corresponding to each of the keys composed of a plurality of bits. The CAM recell has a storage function and a comparison logic function. For example, 256 memory cells are connected to a column corresponding to the comparison data line, and 64 × 4 sets of memory cells are arranged in the horizontal row corresponding to 64 pairs of the comparison data lines. A word line and a detection line (match line) are arranged corresponding to the memory cells. A coincidence detection circuit is provided corresponding to each detection line. The match detection circuit
It includes a reference voltage circuit 0, a load 2, and an amplifier 0 as described later. When 256 × 4 columns of memory cells are provided per key as described above, the match detection circuit is provided with 256 × 4 match detection circuits corresponding thereto.

A control signal generation circuit 0 is provided for the comparison data line of one column. This control signal generation circuit 0
Has a detection circuit 0 and generates a control signal 1 (enable signal) for controlling operations of the reference voltage circuit 0 and the amplifier 0 of the coincidence detection circuit. The coincidence detection line 1 is provided with a reset circuit. This reset circuit performs a reset operation of the detection line 1 by the control signal 0 and the control signal 1.

FIG. 2 is a circuit diagram showing one embodiment of the CAM cell. A memory section including a latch circuit composed of two CMOS inverter circuits IN1 and IN2 whose inputs and outputs are cross-connected, and between a pair of input / output nodes of the latch circuit and complementary data lines D0 and / D0 for writing. Has an N-channel transmission gate MOSFET Q
A selection circuit including 10 and Q11 and a comparison circuit are provided. The comparison circuit receives at its gate the signal of the pair of input / output nodes (storage nodes) and the signal of the complementary data line D1 / D1 for comparison, and provides a current path between the detection line and the ground potential of the circuit. CMOS switch circuits (Q12, Q13) and (Q1
4, Q15).

In the CAM cell, when the stored data and the comparison data do not match, the MOSFET Q1
2, Q13 or Q14, Q15 are turned on, and the high level of the comparison data line D1 or / D1 is changed to the above-mentioned MOSFET.
A current path for transmitting the signal to the gate of TQ16 to turn on and discharging the detection line is formed. When they match, one of the two CMOS switches (Q12, Q13) and (Q14, Q15) is turned on, and the low level of the comparison data line D1 or / D1 is set to the M level.
Since the gate of OSFET Q16 is transmitted and turned off,
No current path for discharging the detection line is formed.

In FIG. 1, a control signal generation circuit 0 is provided in the CAM cell mat as described above at a far end from a driver for comparison data and a coincidence detection circuit. The control signal generation circuit 0 has a detection circuit 0 that detects a change in the potential of the comparison data line and a load 0 that is the same as the load 1 that is parasitic on the actual coincidence detection line 1. The detection circuit 0 is supplied with a signal control signal 0 from a comparison data line.

The coincidence detection line 1 includes the detection line 1 as described above.
A match detection circuit having an amplifier 0 that amplifies a change in the potential and performs a match detection and a reset circuit are connected. The coincidence detection circuit includes an amplifier 0, a reference voltage circuit 0, and a load 2
The reference voltage generated by the reference voltage circuit 0 and the voltage of the coincidence detection line 1 are supplied to the amplifier 0. The voltage of the coincidence detection line 1 and the control signal 1 are supplied to the reference voltage circuit 0 as described later. The reset circuit includes a control signal 0 and a control signal 1 output from the control signal generation circuit 0.
Is supplied.

The load 2 of the reference voltage circuit 0 changes the signal of the coincidence detection line 1 at the slowest time and the control signal 1 changes from a low level (hereinafter simply referred to as "L") to a high level (hereinafter simply referred to as "H"). (Or from "H" to "L"
), The load is such that the change in the reference voltage output from the reference voltage circuit 0 does not exceed the change amount of the coincidence detection line 1.

The detection circuit 0 of the control signal generation circuit 0
Indicates that after the control signal 0 changes from “L” to “H” (or “H” to “L”), the comparison data line changes from “L” to “H” (or “H” to “L”). This is a circuit that senses that it has changed and outputs a control signal 1 via a load 0.

After the control signal 1 changes from "L" to "H" (or "H" to "L"), the coincidence detection circuit
This circuit detects that the match detection line 1 has changed from "H" to "L" (or "L" to "H") and outputs a match detection signal.

The reset circuit changes the control signal 0 and the control signal 1 from "L" to "H" or from "H" to "L" so that the coincidence detection line 1 becomes "H" during the comparison operation period.
This is a circuit having a function of resetting from "H" to "H" (in other words, "L" from "L" to "H").

In the reference voltage circuit 0, when the control signal 1 is "L"
Is changed from "H" (or "H" to "L") to generate a voltage that does not exceed the potential of the match detection line 1 and to control the reference voltage by the potential of the match detection line 1. Circuit.

The amplifier 0 is a circuit having a function of comparing the potential of the coincidence detection line 1 with the reference voltage output from the reference voltage circuit 0, and controlling the gain by the potential of the coincidence detection line 1. For example, the amplifier 0 and the reference voltage circuit 0 are configured by the circuit of FIG. 3 described below. in this case,
The potential of the match detection line precharged to “H” is
When they match, they maintain "H", and when they do not match, they are discharged by the CAM cell shown in FIG.

FIG. 3 is a block diagram showing one embodiment of the coincidence detecting circuit and the reference voltage circuit according to the present invention. The voltage of the match detection line is supplied to the gate of the N-channel MOSFET Q1, and a reference voltage is applied to the gate of the other N-channel MOSFET Q2 which is in a differential form with the gate. N-channel MOS in differential form
The drains of the FETs Q1 and Q2 have a P-channel type MOSFET configured as a current mirror to constitute a load circuit.
TQ3 and Q4 are provided. An N-channel MOSFET Q7, which receives an enable signal and allows an operating current to flow between a commonly connected source of the differential N-channel MOSFETs Q1 and Q2 and the ground potential of the circuit, and a voltage of the coincidence detection line. N-channel type MOSFE
A series circuit of TQ6 is provided. The above differential MOSFET
The amplified signal obtained from the connection point between Q1 and load MOSFET Q2 is amplified by an inverter circuit to form a CMOS level coincidence detection signal.

The reference voltage circuit includes a P-channel MOSFET Q5 which operates as a fixed resistance element with a ground potential constantly applied to its gate, an N-channel MOSFET Q9 which receives the enable signal and flows an operating current, and a coincidence detection line. N-channel MOSFET Q receiving voltage
And a reference voltage is generated by dividing the power supply voltage based on the on-resistance value of the MOSFET Q5 and the combined resistance value of the MOSFETs Q8 and Q9.
Supply to the gate of SFET Q2.

In the circuit of this embodiment, the series M
By using the OSFETs Q6, Q7 and Q8, Q9, the coincidence detection line and the enable signal become substantial enable signals for the amplifier and the reference voltage circuit. Thus, the amplifier (comparator) and the reference voltage circuit as described above are realized. The operation of the circuit of this embodiment is such that the reference voltage is set immediately after the enable signal becomes "H" since the coincidence detection line is precharged to "H" as shown in the waveform shown by way of example. If the coincidence detection line remains "H" as shown by the dotted line, the difference is amplified to form a low-level coincidence signal (hit). In the case of a mismatch, a high-level mismatch signal (miss) is formed because the match detection line is much lower than the reference voltage.

At the time of the mismatch, as the potential of the match detection line decreases, the gate potential of the MOSFET Q6 decreases to act to limit the current of the amplifier. Similarly,
The current of the reference voltage circuit is also limited by the decrease in the gate voltage of the MOSFET Q8. By such a current limiting action, in the case of a mismatch, the current consumed by the amplifier and the reference voltage circuit can be reduced. Further, the reference voltage becomes higher than the reference voltage set in response to the drop of the coincidence detection line potential at the time of the non-coincidence due to the decrease in the current flowing through the load MOSFET Q5. Even if the gain is reduced, it is possible to correctly detect a match even if the signal amplitude in the mismatched state on the match detection line is very small.

FIG. 4 is a waveform chart for explaining the operation of the coincidence detecting circuit according to the present invention. The comparison data sets the comparison data line to the high level in response to the rise of the control signal 0 to the high level. In response to the high level of the comparison data line, the control signal 1 is generated by the detection circuit 0. The control signal 1 monitors completion of the comparison operation in the CAM cell at the far end of the CAM cell, activates the amplifier and the reference voltage circuit of the match detection circuit, and determines the level of the match detection line. . As shown in the figure, a hit signal is output if the level is high, such as the first input data. If the data is at a low level as in the second input data, a mishit signal is output.

In this embodiment, the comparison starts when the associative bit line is at the high level.
The channel type MOSFET is enlarged to make tr of the rising comparison data line faster. Since the falling (discharge) tf of the comparison data line may be the same during the next cycle, the N-channel MOSFET is designed to be small.

FIG. 5 is a schematic circuit diagram of an embodiment of the CAM according to the present invention. In the figure, one CA
The circuit of the M cell, the detection line corresponding thereto, and the coincidence detection circuit is illustratively shown as a representative. The current of the amplifier and the comparison voltage generation circuit is limited in the mishit match comparison circuit as in the above-described embodiment, so that the power consumption is low. The circuit is activated by the control signal 1 and operates at high speed.

In the circuits sz0 to sz2 of this embodiment, the MOSFET to which the control signal 1 is input and the source terminal of the match detection line discharge MOSFET in the CAM cell are connected. In this embodiment, the amplitude of the coincidence detection line is reduced by using charge sharing. That is, as described above, the N-channel type M for discharging the coincidence detection line of the CAM cell is used.
An N-channel MOSFET for current control, operated by the control signal 1, is provided at the source of the OSFET. Thus, the potential of the match detection line can be prevented from reaching the ground level, and the time required for precharging the match detection line can be reduced. Thereby, power can be reduced according to the frequency. Since such a detection line has a small amplitude, the time required for precharging can be shortened, and high-frequency operation can be expected. In this embodiment, a P-channel MOSFET receiving the control signal 1 and a P-channel MOSFET receiving the voltage of the detection line are arranged in parallel to perform a pull-up operation of the output terminal of the amplifier. This operates so that the output of the amplifier recovers quickly in the event of a mishit.

FIG. 6 is a schematic circuit diagram of another embodiment of the CAM according to the present invention. FIG. 1 exemplarily shows one CAM cell, a detection line corresponding thereto and a circuit of a coincidence detection circuit as a representative. The CAM cell is
Unlike the above-described embodiment, the comparison unit has a MOSFET receiving the voltage of the stored data and an MO receiving the voltage of the comparison data line.
The SFETs are arranged in series to form a discharge path for the detection line. That is, by using such a CAM cell, the load on the comparison data line is reduced and the speed is increased. That is, two MOSFEs are provided for the match detection line.
Since the source and drain diffusion layers of T are connected, the capacitance is approximately doubled, but the capacitance of the comparison data line is
This is greatly reduced to about 1/7, and the switching speed of the N-channel MOSFET of the detection line is fast, so that the speed can be increased.

The other structure is the same as that of the embodiment of FIG. 5, and the input node N0 of the amplifier is connected to the control signal 0 of FIG.
Is changed to low level in the case of a miss hit. At this time, in the circuit in which the amplitude of the coincidence detection line is reduced by using the charge sharing using the circuits sz0 to sz2 as described above, the final low-level potential is changed between the case of all bit misses and the case of one bit miss. Can be done without change.

Further, as compared with the CAM cell of FIG. 2, the switching delay of the discharge MOS with respect to the change of the comparison data line is small, so that the speed can be increased. Further, since the circuit shown in the embodiment can detect a match even if the amplitude of the match detection line is minute,
Since the gate size of the MOS can be reduced, the speed can be increased. By sharing the source of the comparator, the reference voltage circuit, the reset circuit, and the CAM cell discharge MOS in layout, it is not necessary to consider malfunction due to power supply noise.

FIG. 7 is a schematic circuit diagram of another embodiment of the CAM according to the present invention. FIG. 1 exemplarily shows one CAM cell, a detection line corresponding thereto and a circuit of a coincidence detection circuit as a representative. This example is
This corresponds to the embodiment of FIG. 1, and the configuration of the coincidence detection circuit is changed. That is, the coincidence detection signal is added to the control signal 1 to control the amplifier and the reference voltage circuit. N-channel type MOSF receiving control signal 1
For ET, by connecting in series an N-channel MOSFET that is turned on by the low level of the match detection signal, the current of the mishit amplifier is stopped, thereby reducing power consumption.

FIG. 8 is a schematic circuit diagram of still another embodiment of the CAM according to the present invention. In this embodiment, the coincidence detection line is divided by NMOS or PMOS,
At this time, the speed is increased by setting the parasitic capacitance CS on the match detection circuit side to be smaller than the parasitic capacitance CL on the CAM cell side (CL> CS). That is, by dividing the capacitance in such a relationship, the input signal of the amplifier can be made larger than the potential change of the coincidence detection line on the CAM cell side.

As described above, the CA according to the present invention is
In M, by using the detection circuit to generate a comparator (amplifier) activation signal from the comparison address, the timing design is facilitated without excessive timing margin. In addition, in addition to the activation signal (control signal 1), the coincidence detection line is connected to the amplifier and the gate of the current source MOS of the reference voltage circuit, and the current is controlled by coincidence / mismatch. At the same time as the power consumption is reduced, the reference voltage swings to the potential opposite to that of the coincidence detection line, so that coincidence can be detected even with a small amplitude, and the speed can be increased.

Further, in the method of the above-described study example 1, since the activation of the coincidence detection line is accelerated by a large current in order to accelerate the activation of the coincidence detection line, it is necessary to enlarge the MOS for discharging the coincidence detection line of the CAM cell. However, in the CAM according to the present invention, it is not necessary to increase the amplitude of the coincidence detection line.
The MOS for discharging the match detection line can be reduced, and CA
Since the area of the M cell can be reduced, the area can be reduced. In addition, since each entry has a reference voltage circuit,
The detailed study of the power supply noise as in the study example 1 is unnecessary, and the reference voltage circuit of the mismatched entry consumes almost no current, so that the power does not increase.

In the CAM according to the present invention, even if the same amplifier (amplifier) as in the case of the above-described study example 1 is used, the CAM can be operated in a large gain region. Match detection can be performed at high speed even if the N-channel MOSFET for discharging the detection line is reduced in size. In addition, regarding the power, the enable is created from the change of the associative bit line. However, the amplifier of the entry in which the error has occurred has no problem in terms of power because the current is limited.

As for the reference voltage circuit, the power can be reduced by using the coincidence detection line as the enable of the current source as in the case of the amplifier (comparator). However, the signal of propagating the comparison result is enabled in the method of the study example 1, and the method itself does not require a timing margin for starting the amplifier. However, in the precharge method, the match detection line is missed from a hit state. If it is too early, multiple entries will be mistakenly hit. Therefore, attention must be paid to the timing of the enable signal. However, the enable signal generation circuit according to the present invention directly detects a change in the comparison data line in order to avoid the above-mentioned problem when the dummy entry is used. Further, since there is no need to have an extra entry, an increase in area can be suppressed. Further, by devising the arrangement, it is possible to eliminate the need for a timing margin, so that high speed and low power consumption can be achieved.

The functions and effects obtained from the above embodiment are as follows. (1) A memory unit having a pair of complementary input / output nodes and holding storage data written from the complementary data line by the word line selecting operation, and a search input input to the storage data and the pair of complementary data lines A plurality of memory cells each including a comparison unit for comparing a signal and forming a current path in response to a mismatch output, provided at intersections of a plurality of complementary data lines and a word line, and provided in parallel with the word line; A plurality of detection lines each having a current path connected to a wired logic configuration, a reference voltage circuit for generating a reference voltage by flowing a current to a resistance means according to a selection signal as a voltage determination circuit, and an operating current according to the selection signal. And an amplifier including a differential circuit receiving the reference voltage and the signal voltage of the detection line, and a voltage corresponding to the mismatched output receiving the detection signal voltage. By using current limiting means for limiting the current in each of the current path for forming the illumination voltage and the current path for flowing the operation current of the differential circuit, it is possible to realize stable operation and low power consumption. The effect is obtained.

Although the invention made by the inventor has been specifically described based on the embodiments, the invention of the present application is not limited to the above embodiments, and various modifications can be made without departing from the gist of the invention. Needless to say. For example, FIG.
In the above, the CAM cell may share the data lines D0 and D1 (/ D0 and / D1). In other words, when writing data to the storage unit, the word line is set to the selected level, the memory cells are selected one by one, and the data is sequentially written. Just enter it. Further, the signal amplitude limiting circuit provided in the coincidence detection line can adopt various embodiments. The CAM uses the T
Besides those used for LB, it can be widely used as an associative memory. INDUSTRIAL APPLICABILITY The present invention can be widely used for various semiconductor integrated circuit devices having a CAM.

[0048]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows. A memory unit having a pair of complementary input / output nodes and holding storage data written from the complementary data line by the word line selecting operation; and a storage unit configured to store the storage data and a search input signal input to the pair of complementary data lines. A plurality of memory cells each including a comparison unit that forms a current path in response to a mismatch output are provided at intersections of a plurality of complementary data lines and word lines, and the current path of the comparison unit is parallel to the word lines. Is provided with a plurality of detection lines connected to a wired logic configuration, a reference voltage circuit that generates a reference voltage by flowing a current to the resistance means by a selection signal as a voltage determination circuit, an operating current flows by the selection signal, An amplifier including a differential circuit receiving the reference voltage and the signal voltage of the detection line; and a voltage corresponding to the mismatched output receiving the voltage of the detection signal. By using the current limiting means for limiting the respective current of the current path and the current path flowing an operating current of the differential circuit to form, it is possible to realize stable and low power consumption operation.

[Brief description of the drawings]

FIG. 1 is a schematic circuit diagram showing an embodiment of a CAM according to the present invention.

FIG. 2 is a circuit diagram showing one embodiment of a CAM cell used in the present invention.

FIG. 3 is a configuration diagram showing one embodiment of a coincidence detection circuit and a reference voltage circuit according to the present invention;

FIG. 4 is a waveform chart for explaining the operation of the coincidence detection circuit according to the present invention;

FIG. 5 is a schematic circuit diagram showing one embodiment of a CAM according to the present invention.

FIG. 6 is a schematic circuit diagram showing another embodiment of the CAM according to the present invention.

FIG. 7 is a schematic circuit diagram showing another embodiment of the CAM according to the present invention.

FIG. 8 is a schematic circuit diagram showing still another embodiment of the CAM according to the present invention.

[Explanation of symbols]

 Q1-Q16 ... MOSFET.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Noriaki Maeda 5-22-1, Josuihoncho, Kodaira-shi, Tokyo Inside Hitachi Super-LSI Systems Co., Ltd. (72) Inventor Yasuhisa Shimazaki Tokyo 5-2-1, Josuihoncho, Kodaira-shi Within the Hitachi, Ltd. Semiconductor Group, Inc.

Claims (1)

[Claims] A plurality of complementary data lines, a plurality of word lines, and a pair of complementary input / output nodes corresponding to the plurality of complementary data lines, respectively. A memory unit for holding storage data written from the memory unit, and a comparison unit for comparing the storage data with a search input signal input to the pair of complementary data lines or the comparison data line to form a current path according to a mismatch output. A plurality of memory cells comprising: a plurality of memory cells, a plurality of detection lines provided in parallel with the word line, and a current path of the comparison unit connected to a wired logic configuration; and a voltage determination circuit for determining a level of the detection line. With
A reference voltage circuit configured to generate a reference voltage by flowing a current through the resistance unit according to the selection signal; and a differential circuit receiving an operation current flowing according to the selection signal and receiving the reference voltage and the signal voltage of the detection line. An amplifier including a circuit, a current path for receiving the voltage of the detection signal and forming a reference voltage with a voltage corresponding to a mismatched output, and a current path for limiting a current flowing in an operation current of the differential circuit. A semiconductor integrated circuit device comprising: