JP2002277958A - Projector and image forming method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a projector capable of obtaining one picture of high definition by preventing split images from overlapping each other at boundary parts where the split images are adjacent to each other, and also, preventing the occurrence of a gap between the images, in the case of projecting more than one divided images on a screen. SOLUTION: The analog input image signals Ri, Gi and Bi for one picture, a horizontal synchronizing signal HD and a vertical synchronizing signal VD are inputted to an image splitting circuit 1, images are split into a plurality of split images, and then, the analog image signals S1 and S4 corresponding to the split images are inputted from the image splitting circuit 1 to a split projectors P1 to P4. The split projection images F1 to F4 are separately projected on the screen 2 by the split projectors P1 to P4 based on the analog image signals S1 to S4, then, one picture is displayed on the screen 2. By individually adjusting the size of the split/projected images F1 to F4 by respective adjusting means arranged in the split projectors P1 to P4, the images are prevented from overlapping each other at the boundary part where the split/projected images F1 to F4 are adjacent to each other on the screen 2, and also, the occurrence of the gap between the images are prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a projector and an image forming method for forming one display image on a screen by dividing one screen into a plurality of images. Of the divided image, and a plurality of image projection units project the divided image on the screen so as to overlap with each other to form one display image, and the divided projected image is formed such that the image of the overlapped portion is eliminated. The present invention relates to a projector and an image forming method capable of forming a high-quality image in which overlapping of divided images on a screen and a gap between divided images are not generated by adjusting the size of the divided images by an adjusting unit.

[0002]

2. Description of the Related Art In recent years, needs for thinner and larger displays have been rapidly increasing, and projectors particularly suitable for large-screen display have been rapidly spreading. This projector is roughly classified into the following two types. (1). Method using a spatial light modulator represented by liquid crystal (2). An optical scanning method in which an image is formed by scanning while power-modulating a laser beam is a typical application example of a projector. In these information processing devices, the data processing capability has been dramatically improved in recent years, and extremely high-precision images have been generated. In order to make the projector compatible, a high-resolution spatial light modulation element corresponding to an image is required for the projector of the above-mentioned method (1), but at present, it cannot be sufficiently followed.

[0003] Further, the projector of the above-mentioned method (2) requires an extremely high light modulation speed, requires a sophisticated design and expensive devices, and consequently requires expensive products. There is a problem that it becomes. Therefore, as a means for obtaining a large and high-definition image at a relatively low cost, an image display method of connecting divided images by a plurality of projectors to obtain one large-screen display has been conventionally used. However,
Such a projector of the image display method has a major drawback in that images overlap at the boundary of the divided images and a gap is generated between the divided images in adjacent portions of the divided images, resulting in significant deterioration of image quality. .

[0004]

As a conventional example for solving such deterioration of image quality, for example,
(A) JP-A-6-222381 ("Projector device", hereinafter referred to as "first publication"), (B). Japanese Patent Application Laid-Open No. 9-326981 ("Image projection system", hereinafter referred to as "second publication") is known. Of these publications,
First, in the case of the first publication, a plurality of liquid crystal projectors are used in combination, and in order to make joints of the screens inconspicuous when displaying one screen, predetermined light is emitted from a light source having a reflector. Provide a plurality of liquid crystal projectors that project the image on the liquid crystal panel with the magnifying projection lens to display the image of the Each image is projected on a screen from a projector to form one image.

[0005] In the case of the projector disclosed in the first publication, a divided image is formed on each liquid crystal panel without using the full resolution of the liquid crystal panel, and each divided image is moved on the liquid crystal panel, thereby forming a boundary portion. The image is adjusted. However, in such a projector device, in order to secure a sufficient adjustment range of the divided image, a liquid crystal panel having a sufficiently high resolution for the input image is required. Therefore, a considerable portion of the display performance of the liquid crystal panel is not used, which is extremely inefficient and has a problem that the cost is eventually increased. For example, when considering a projector using four 800 × 600 pixel (SVGA) liquid crystal panels, a divided image is adjusted to adjust the connection between the divided images for a 1600 × 1200 (UXGA) input image. There is no room to move. In order to secure this connection adjustment range, a liquid crystal panel of 800 × 600 pixels or more is required. However, if a panel with a standard resolution is selected in terms of cost, at least 1024 × 768 pixels (XG
The liquid crystal panel of A) will be used.

In the case of the second publication, a plurality of projectors for projecting at least a part of high-definition image data created and output by a personal computer are arranged, and the high-definition image data is stored in a controller unit. The image data is input to the image processing unit, and the image processing unit determines which part of the high-definition image data is output as a divided image to each projector based on the parameters stored in the projector arrangement storage unit in advance. The signals of the image processing unit are converted into analog signals by a plurality of D / A (digital / analog) conversion units, and then supplied to each projector, and the divided images are projected on the screen by the projectors. Is a high-definition image in which each divided image is accurately aligned. As described above, in the image projection system disclosed in the second gazette, the divided images projected by the respective projectors on the screen are formed so that the overlapping portion is common at the boundary portion, and the overlapping portion is For example, each projector performs a weighting such that the luminance decreases at a fixed rate toward the outer pixels, thereby preventing the luminance from increasing at the boundary. However, in such an image projection system, an image at a boundary portion is blurred, and an image which requires high-definition and clear quality such as text and graphics becomes very difficult to see. There is.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and it is possible to improve the quality of a display screen by eliminating overlapping or gaps between adjacent borders of a divided image displayed on a screen. It is an object to provide a projector and an image forming method. Particularly, an object of claim 1 of the present invention is to provide a display image by dividing a single screen into a plurality of images and forming one display image. To prevent gaps from occurring, preventing degradation in image quality.
It is an object of the present invention to provide a projector with excellent cost performance by making full use of display performance. An object of claim 2 of the present invention is to adjust the size of a divided image by cutting out a peripheral portion having low importance as information, so that the processing is extremely easily realized and the cost is further reduced. Is to provide a projector that can realize the above. The object of claim 3 of the present invention is to prevent the loss of image information and to adjust the size of the divided projection image while maintaining the input image quality. It is an object of the present invention to provide a projector suitable for displaying an image that is not allowed.

An object of the present invention is to prevent the loss of image information and to adjust the size of the divided projection image while maintaining the input image quality. A projector suitable for displaying an unacceptable image is provided. The object of claim 5 of the present invention is to provide a high-definition and low-cost projector for a wide range of applications, which can arbitrarily change the resolution and pixel density, can respond to image input of all image densities while maintaining its image quality. To provide. An object of claim 6 of the present invention is to provide a high-definition and low-cost projector for a wide range of applications in which resolution and pixel density can be arbitrarily changed, and image input of all image densities can be handled while maintaining the image quality. To provide. It is an object of a seventh aspect of the present invention to provide a projector that allows a user to arbitrarily adjust the size of a divided projection image according to the state of a screen. The object of claim 8 of the present invention is that, with a simple configuration, it is possible to prevent overlapping of images at a boundary portion of a divided image, to prevent generation of a gap, and to prevent deterioration of image quality.
Moreover, it is an object of the present invention to provide a projector that allows a user to easily and arbitrarily adjust a screen size.

A further object of the present invention is to provide a projector capable of writing an analog image signal of an input divided image to a frame memory with a simple configuration. In particular, when reading an image signal from a frame memory, an object of the present invention is to shift the horizontal and vertical read start addresses by the values of the horizontal differential signal and the vertical differential signal. An object of the present invention is to provide a projector capable of reliably preventing adjacent portions from overlapping. An object of an eleventh aspect of the present invention is to enable a horizontal and a vertical read start address to be shifted by a value of a horizontal differential signal and a vertical differential signal when an image signal is read from a frame memory. An object of the present invention is to provide a projector that can prevent loss of information and can adjust the size of a divided projection image while maintaining input image quality. The object of claim 12 of the present invention is that, in particular, the resolution of a display image in an optical scanning projector and the pixel density can be arbitrarily changed,
It is an object of the present invention to provide a projector that can easily adjust the size of an image.

The object of claim 13 of the present invention is to provide a highly accurate cycle of the basic clock, the horizontal scanning reference timing signal, and the vertical scanning reference timing signal, and the variation in the size after the screen size is adjusted is small. To provide a projector capable of obtaining a customized display screen. An object of a fourteenth aspect of the present invention is to provide a projector which does not substantially display a black image in the peripheral portion of the divided image and hardly affects the lack of the peripheral portion of the divided image. . The object of claim 15 of the present invention is to provide an image having excellent preservation of information of an original image, in which information such as text and drawings is not allowed to be lost in a method using a spatial light modulator such as a liquid crystal. It is to provide a suitable projector. The object of claim 16 of the present invention is particularly for displaying images having excellent preservability of information of an original image and in which information such as texts and drawings is not tolerated by a method using a spatial light modulator such as a liquid crystal. It is to provide a suitable projector. An object of claim 17 of the present invention is to prevent the loss of image information and adjust the size of the divided projection image while maintaining the input image quality, and to prevent the loss of information such as text and drawings. An object of the present invention is to provide a projector suitable for displaying an unacceptable image.

An object of an eighteenth aspect of the present invention is to provide a projector capable of performing light modulation and driving of a liquid crystal panel with a simple structure. Claim 19 of the present invention
In particular, an object of the present invention is to provide a projector that can easily perform horizontal scanning and vertical scanning of modulated light by performing horizontal driving and vertical driving of an illumination optical system. An object of a twentieth aspect of the present invention is to provide a projector capable of easily performing light modulation by an analog image signal and horizontal and vertical scanning of the modulated light. The object of claim 21 of the present invention is to prevent the image quality from deteriorating, particularly by preventing the images from overlapping at the boundary of the divided images or by creating a gap between the divided images. It is an object of the present invention to provide an image forming method which is utilized to the maximum extent and which is excellent in cost performance.

[0012] An object of claim 22 of the present invention is to provide an adjusting means for adjusting the size of a divided image, in particular, by providing a means for cutting off a peripheral part of the divided image, and cutting off the peripheral part of the image.
In the case of an image image or the like, the importance of information is generally lower as it is closer to the peripheral portion of the image, but it is an object of the present invention to provide an image forming method which hardly affects the omission of an image in the peripheral portion. An object of claim 23 of the present invention is to provide an adjusting means for adjusting the size of a divided image, in particular, a means for changing the pixel density of the original divided image to prevent loss of the image and maintain the input image quality. It is an object of the present invention to provide an image forming method that can adjust the size of a divided projection image as it is, and is suitable for displaying an image such as a text or a drawing that does not allow loss of information. The object of claim 24 of the present invention is to provide a means for changing the pixel density of the original divided image in the adjusting means for adjusting the size of the divided image, and to prevent the loss of the image and maintain the input image quality. It is an object of the present invention to provide an image forming method which can adjust the size of a divided projection image as it is, and is suitable for displaying an image in which information such as text or drawing is not allowed to be lost.

[0013]

In order to achieve the above object, a projector according to the present invention forms one display image by dividing one screen into a plurality of divided images. In the projector, a plurality of image projection units arranged so that a plurality of divided projection images are projected on the screen so as to partially overlap each other to form one display image, and the size of each of the divided projection images is And adjusting means for adjusting. The projector according to the invention described in claim 2 is characterized in that the adjusting means includes a means for cutting out a peripheral portion of the original divided image. A projector according to a third aspect of the invention is characterized in that the adjusting means includes means for converting the resolution of the original divided image. A projector according to a fourth aspect of the invention is characterized in that the adjusting means includes means for changing the pixel density of the original divided image. A projector according to a fifth aspect of the present invention is an optical scanning projector that forms an image by scanning output light power-modulated according to input pixel data, wherein the means for changing the pixel density includes: It is characterized by including a means for changing the scanning speed of the output light. The projector according to the invention according to claim 6 is an optical scanning type projector that forms an image by scanning output light that is power-modulated according to input pixel data, wherein the means for changing the pixel density includes: It is characterized by including means for changing the modulation speed of the output light.

According to a seventh aspect of the invention, the projector is characterized in that the adjusting means can individually and arbitrarily adjust the size of each of the divided projected images. In the projector according to the eighth aspect of the present invention, the adjusting means may synchronize the digital image signal within one vertical period in synchronization with a synchronization clock generated by a horizontal synchronization signal and a vertical synchronization signal for each of the divided projection images. Writing means for writing with a write address generated based on the number of scanning lines and the number of effective pixels within one horizontal period from the synchronous clock;
A frame memory for writing the digital image signal in synchronization with the synchronization clock in accordance with the write address; and a difference between a screen size of each of the divided projection images adjusted by the size adjustment signal and a screen size of each of the original divided projection images. A screen size generation circuit for generating a horizontal difference output signal and a vertical difference output signal, and writing only the values of the horizontal difference output signal and the vertical difference output signal to the horizontal and vertical frame memories. The read start address of the digital image signal is shifted,
Arithmetic processing means for reading a digital image signal written in the frame memory by a basic clock generated from the horizontal synchronization signal and the vertical synchronization signal, a vertical scanning reference timing signal, and a horizontal scanning reference timing signal; A signal synchronized with the reading of the last pixel data in the horizontal direction of the frame memory is set to the “L” level immediately before the reading of the first pixel of the next line is started based on the horizontal scanning reference timing signal, and 1
A signal synchronized with the reading of the last pixel data of the last line of the screen is read from the frame memory at the “L” level immediately before the reading of the first pixel of the next screen is started based on the vertical scanning reference timing signal. The relationship between the input image signal and the actual display image is linearly corrected with respect to the digital image signal, and one of the horizontal scanning reference timing signal and the vertical scanning reference timing signal has an "H" level. Data processing means for obtaining output image data corrected so as to output black image data, and driving the image projection means by the basic clock, the horizontal scanning reference timing signal, and the vertical scanning reference timing signal. Image projection means for supplying correction processing output image data output from the data processing means to the image projection means It is characterized in that it comprises a drive means.

According to a ninth aspect of the invention, in the projector according to the ninth aspect, the writing means generates a synchronization clock based on the horizontal synchronization signal and the vertical synchronization signal for each of the divided projection images; An analog / digital converter for converting an analog image signal of the divided projection image into a digital image signal in synchronization with a synchronization clock signal, and a horizontal synchronization pulse within one vertical period for writing the digital image signal to the frame memory And a write address generation circuit for detecting the number of scanning lines and detecting the number of effective pixels within one horizontal period from the synchronous clock to generate a write address. The projector according to claim 10, wherein the arithmetic processing unit generates a basic clock, a horizontal scanning reference timing signal, and a vertical scanning reference timing signal from the horizontal synchronization signal and the vertical synchronization signal. Generating a read address of the digital image signal from the frame memory in synchronization with the basic clock based on the horizontal scan reference timing signal and the vertical scan reference timing signal; and A read address generation circuit that shifts a read start address of the digital image signal in the horizontal direction and the vertical direction by the value of the difference signal.

In the projector according to an eleventh aspect of the present invention, in the projector, the arithmetic processing means converts the basic clock, the horizontal scanning reference timing signal, and the vertical scanning reference timing signal from the horizontal synchronization signal and the vertical synchronization signal. While generating, the display pixels in the image projection unit are adjusted in size by associating the number of pixels adjusted in size based on the horizontal direction difference signal and the vertical direction difference signal with the original number of display pixels in the image projection unit. An arithmetic processing circuit for generating interpolation processing table data generated after conversion into image coordinates, a write control signal, and a write address; the horizontal scanning reference timing signal and the vertical scanning reference output from the arithmetic processing circuit Digitize from the frame memory in synchronization with the basic clock based on the timing signal. Read out the digital image signal and generate an address signal, and shift the read start address of the digital image signal written in the horizontal and vertical frame memories by the value of the horizontal difference signal and the vertical difference signal. A read address generating circuit for performing the write operation, and an interpolation table for writing the interpolation processing table data in accordance with the write address and the write control signal.

In the projector according to the twelfth aspect of the invention, the arithmetic processing means may determine a horizontal screen size based on the horizontal synchronization signal, the vertical synchronization signal, the horizontal difference signal, and the vertical difference signal. A basic clock for reading a digital image signal from the frame memory by shortening the synchronization for shortening, a horizontal scanning reference timing signal, and a vertical scanning reference timing signal for shortening synchronization to shorten the vertical screen size. And a basic clock output from the frame memory based on the basic clock, the horizontal scanning reference timing signal, and the vertical scanning reference timing signal output from the arithmetic processing circuit. Reading the digital image signal from the frame memory in synchronization with It is characterized in that it comprises a read address generating circuit for outputting an address signal out.
The projector according to the invention according to claim 13, wherein the arithmetic processing unit outputs the basic clock, the horizontal scanning reference timing signal, and the vertical scanning reference timing signal.
It is obtained by controlling a voltage controlled oscillator by an output of a digital / analog converter whose output voltage changes in accordance with the output of the horizontal difference output signal and the vertical difference signal, respectively.

According to a fourteenth aspect of the present invention, in the projector, the data processing means performs a logical sum of a signal synchronized with reading of the frame memory and a signal synchronized with reading of last pixel data of the last line of one screen. And an OR circuit that outputs a selection signal when the selection signal is “L”
A selection circuit for selecting and outputting the digital image signal output from the frame memory when the signal is at a level, and selecting and outputting black data from a black data output circuit when the selection signal is at an "H"level; An image processing circuit is provided which linearly corrects the relationship between the digital image signal output from the selection circuit and the actual image and outputs the result. In the projector according to the invention described in claim 15, the data processing means reads the interpolation processing table data written in the interpolation table, and a corresponding display pixel is closest to a display pixel among four adjacent pixels. A difference in gray level between two pixels is obtained, a display pixel value is calculated by a process according to the difference in gray level, and the relationship between the calculated display pixel value and the actual display pixel is linearized. It is characterized by being constituted by a data processing circuit for processing.

According to a sixteenth aspect of the present invention, in the projector, the data processing means stores a line buffer for storing three lines of digital image signals read from the frame memory, and a line buffer for storing the digital image signals for three lines. A control circuit for reading display pixel data corresponding to the two lines of images from the interpolation table and reading four corresponding pixels from the coordinate data in the data from the line buffer; and image data read from the line buffer. And an interpolation processing circuit for setting a display pixel value interpolated based on a linear interpolation method, and performing a linearization correction process on the relationship between the interpolated display pixel value data and an actual display image. An image processing circuit that outputs correction processing output image data, and reads the correction processing output image data by the interpolation table. It is characterized by comprising a timing adjusting circuit for timing adjustment based on the read address of the table. 18. The projector according to claim 17, wherein the data processing means is a digital signal output from the frame memory read in synchronization with a basic clock output from the arithmetic processing circuit. It is an image processing circuit for inputting an image signal and linearizing the relationship between the input image signal and the actual display image.

In the projector according to the eighteenth aspect of the invention, the driving means for the image projection means converts the corrected output image data output from the data processing circuit into an analog signal and supplies the analog signal to the image projection means. A digital-to-analog converter that outputs a control signal for controlling the driving of the image projection unit based on the basic clock, the horizontal scanning reference timing signal, and the vertical scanning reference timing signal output from the read processing unit. A drive control signal generation circuit.
20. The projector according to claim 19, wherein the driving means for the image projecting means comprises: a rotation speed detection signal of an illumination optical system of the image projecting means; a basic clock output from the arithmetic processing circuit; A horizontal drive circuit for horizontally driving the illumination optical system of the image projection means with a timing signal; and a vertical drive for vertically driving the illumination optical system of the image projection means based on a vertical scanning reference timing signal output from the arithmetic processing means. And a driving circuit.

According to a twentieth aspect of the present invention, in the projector, the image projection means includes a light source that continuously generates light of three primary colors of red, green, and blue at a constant power, and a light source of the three primary colors. An optical modulator that modulates with an analog image signal;
Means for combining the light modulated by the light modulator into one light, a polygon motor driven by the output of the horizontal drive circuit in the adjustment means, and the output of the vertical drive circuit in the adjustment means A galvano motor driven by the above, a polygon mirror rotated by the polygon motor and reflected in the horizontal direction when the synthesized light is incident, and a reciprocating motion in the vertical direction driven by the galvano motor causes When the reflected light from the polygon mirror is incident, a galvano mirror that forms a display image on the screen by reflecting the reflected light in the vertical direction and guiding the reflected light to the screen is provided.

An image forming method according to a twenty-first aspect of the present invention is a projector for forming one display image by dividing and projecting one screen by a plurality of image projecting means. A first step of arranging the plurality of image projecting means for projecting each divided projection image on the screen such that a part thereof partially overlaps each other; A second step of adjusting the size of each of the divided projection images by an adjustment unit so as to project only the image from one of the image projection units. An image forming method according to a twenty-second aspect is characterized in that the size of each of the divided projection images is adjusted by cutting out a peripheral portion of the original divided image. An image forming method according to a twenty-third aspect is characterized in that the size of each of the divided projection images is adjusted by converting the resolution of the original divided image. An image forming method according to a twenty-fourth aspect is characterized in that the size of each divided projection image is adjusted by changing the pixel density of the original divided image.

[0023]

In other words, the projector according to the first aspect of the present invention is a projector that forms one display image by dividing and projecting one screen into a plurality of divided images. A plurality of image projection units are arranged so that the units are projected so as to overlap each other to form one display image, and an adjustment unit that adjusts the size of each of the divided projection images is provided. With such a configuration, by adjusting the size of the divided image, it is possible to improve the quality of the display screen by eliminating the overlap and the gap between the adjacent boundary portions of the divided image displayed on the screen. In the projector according to a second aspect of the present invention, the adjusting means includes a means for cutting out a peripheral portion of the original divided image. With such a configuration, the peripheral portion of the divided image is cut out by the adjusting unit that adjusts the size of the divided image, and the peripheral portion of the image is cut out. It is possible to hardly affect the missing image of the part.

In the projector according to the third aspect of the present invention, the adjusting means includes means for converting the resolution of the original divided image. With such a configuration, the adjusting means for adjusting the size of the divided image is provided with a means for converting the resolution of the original divided image, and the size of the divided projected image is reduced while preventing the loss of the image and maintaining the input image quality. Can be adjusted, and is suitable for displaying an image such as a text or a drawing in which loss of information is not allowed. In the projector according to a fourth aspect of the present invention, the adjusting means includes means for changing a pixel density of the original divided image. With such a configuration, it is possible to adjust the size of the divided projection image while preventing loss of the image and maintaining the input image quality, and when displaying an image in which information such as text or drawing is not allowed to be lost. It is suitable. The projector according to claim 5 is an optical scanning type projector that forms an image by scanning output light power-modulated according to input pixel data, wherein the means for changing the pixel density comprises: Means for changing the scanning speed of the image. With such a configuration, the resolution and pixel density can be arbitrarily changed, and even if the scanning speed is the same, the screen size can be reduced by increasing the modulation speed. can do.

A projector according to a sixth aspect of the present invention is an optical scanning type projector that forms an image by scanning output light power-modulated according to input pixel data, wherein the means for changing the pixel density includes: Means for changing the modulation speed of the output light. As described above, by changing the modulation speed of the output light, the resolution and the pixel density can be arbitrarily changed.Even if the scanning speed is the same, a higher modulation speed can reduce the screen size. Even if the scanning speed is reduced, the screen size can be reduced. In a projector according to a seventh aspect of the present invention, the adjusting means can individually and arbitrarily adjust the size of each of the divided projection images. In this way, by allowing the adjusting means for adjusting the size of each divided projection image to be able to individually adjust the size of each divided projection image, the user can arbitrarily adjust the size of each divided projection image according to the situation of the screen. The size can be adjusted.

In the projector according to an eighth aspect of the present invention, the adjusting means synchronizes a digital image signal within one vertical period in synchronization with a synchronization clock generated by a horizontal synchronization signal and a vertical synchronization signal for each of the divided projection images. Writing means for writing with a write address generated based on the number of scanning lines and the number of effective pixels in one horizontal period from the synchronous clock;
A frame memory for writing the digital image signal in synchronization with the synchronization clock in accordance with the write address; and a difference between a screen size of each of the divided projection images adjusted by the size adjustment signal and a screen size of each of the original divided projection images. A screen size generation circuit for generating a horizontal difference output signal and a vertical difference output signal, and writing only the values of the horizontal difference output signal and the vertical difference output signal to the horizontal and vertical frame memories. The read start address of the digital image signal is shifted,
Arithmetic processing means for reading a digital image signal written in the frame memory by a basic clock generated from the horizontal synchronization signal and the vertical synchronization signal, a vertical scanning reference timing signal, and a horizontal scanning reference timing signal; A signal synchronized with the reading of the last pixel data in the horizontal direction of the frame memory is set to the “L” level immediately before the reading of the first pixel of the next line is started based on the horizontal scanning reference timing signal, and 1
A signal synchronized with the reading of the last pixel data of the last line of the screen is read from the frame memory at the “L” level immediately before the reading of the first pixel of the next screen is started based on the vertical scanning reference timing signal. The relationship between the input image signal and the actual display image is linearly corrected with respect to the digital image signal, and one of the horizontal scanning reference timing signal and the vertical scanning reference timing signal is at the “H” level. Data processing means for obtaining output image data corrected so as to output black image data, and driving the image projection means by the basic clock, the horizontal scanning reference timing signal, and the vertical scanning reference timing signal. For image projection means for supplying correction processing output image data output from the data processing means to the image projection means And a dynamic means. With such a configuration, it is possible to prevent the images from overlapping and generating a gap at the boundary of the divided image with a simple configuration, to prevent the image quality from deteriorating, and to make it easy and easy for the user to reduce the screen size. Can be adjusted.

According to a ninth aspect of the present invention, in the projector, the writing means generates a synchronization clock based on the horizontal synchronization signal and the vertical synchronization signal for each of the divided projection images, and the synchronization clock signal. An analog / digital converter for converting an analog image signal of the divided projection image into a digital image signal in synchronization with the above, and a scanning line number from a horizontal synchronization pulse within one vertical period for writing the digital image signal to the frame memory. And a write address generation circuit for generating a write address by detecting the number of effective pixels within one horizontal period from the synchronous clock. With such a configuration, an analog image signal of the input divided image can be written to the frame memory with a simple configuration. According to a tenth aspect of the present invention, in the projector, the arithmetic processing unit comprises:
A synchronization signal generating circuit for generating a basic clock, a horizontal scanning reference timing signal, and a vertical scanning reference timing signal from the horizontal synchronization signal and the vertical synchronization signal, and a synchronization signal generation circuit based on the horizontal scanning reference timing signal and the vertical scanning reference timing signal; A read address of the digital image signal is generated from the frame memory in synchronization with the basic clock, and reading of the digital image signal in the horizontal and vertical directions is started by the values of the horizontal difference signal and the vertical difference signal. A read address generation circuit for shifting an address. With such a configuration, the values of the horizontal difference signal and the vertical difference signal can be shifted in the horizontal and vertical read start addresses when the image signal is read from the frame memory, and the overlapping of the adjacent portions of the divided projection image can be reliably performed. Can be prevented.

[0028] The projector according to claim 11 of the present invention comprises:
The arithmetic processing means generates the basic clock, the horizontal scanning reference timing signal, and the vertical scanning reference timing signal from the horizontal synchronization signal and the vertical synchronization signal, and generates the horizontal difference signal and the vertical difference signal. Interpolation processing table data generated after converting the display pixels in the image projection unit to the coordinates of the image after the size adjustment by associating the number of pixels adjusted in size based on the number of pixels and the original number of display pixels in the image projection unit, An arithmetic processing circuit that generates a write control signal and a write address; and, from the frame memory, synchronizing with the basic clock based on the horizontal scanning reference timing signal and the vertical scanning reference timing signal output from the arithmetic processing circuit. Reads the digital image signal to generate the address signal, A read address generation circuit for shifting a read start address of the digital image signal written in the frame memory in the horizontal direction and the vertical direction by the value of the horizontal direction difference signal and the vertical direction difference signal; An interpolation table for writing the interpolation processing table data in accordance with a signal. With such a configuration, when reading an image signal from the frame memory, the horizontal and vertical read start addresses can be shifted according to the values of the horizontal difference signal and the vertical difference signal, and loss of image information can be prevented. The size of the divided projection image can be adjusted while maintaining the image quality.

A projector according to claim 12 of the present invention
The arithmetic processing means shortens the synchronization to shorten the horizontal screen size based on the horizontal synchronization signal, the vertical synchronization signal, the horizontal difference signal, and the vertical difference signal, and An arithmetic processing circuit that generates a basic clock for reading an image signal, a horizontal scanning reference timing signal, and a vertical scanning reference timing signal whose synchronization is shortened to shorten the vertical screen size; and Reading out a digital image signal from the frame memory in synchronization with the basic clock output from the frame processing circuit from the frame memory based on the output basic clock, the horizontal scanning reference timing signal, and the vertical scanning reference timing signal. A read address generation circuit that outputs an address signal. Obtain. With such a configuration, it is possible to arbitrarily change the resolution and the pixel density of the display image in the optical scanning type projector, and easily adjust the image size. 14. The projector according to claim 13, wherein the arithmetic processing means outputs the basic clock, the horizontal scanning reference timing signal, and the vertical scanning reference timing signal to the horizontal difference output signal and the vertical difference signal, respectively. It is obtained by controlling the voltage controlled oscillator by the output of the digital / analog converter whose output voltage changes according to the following. With such a configuration, the periods of the basic clock, the horizontal scanning reference timing signal, and the vertical scanning reference timing signal can be made highly accurate, and the size of the screen after the screen size adjustment is small, and a stable display screen can be obtained. .

A projector according to claim 14 of the present invention
An OR circuit for outputting a selection signal by performing a logical sum of a signal synchronized with reading of the frame memory and a signal synchronized with reading of last pixel data of the last line of one screen; Selects and outputs the digital image signal output from the frame memory when is at the "L" level, and selects and outputs black data from the black data output circuit when the selection signal is at the "H" level. A selection circuit; and an image processing circuit that performs linearization correction processing on the relationship between the digital image signal output from the selection circuit and an actual image and outputs the result.
According to such a configuration, the black image in the peripheral portion of the divided image is not substantially displayed, and therefore, there is almost no effect on the lack of the peripheral portion of the divided image. In a projector according to a fifteenth aspect of the present invention, the data processing means reads the interpolation processing table data written in the interpolation table, and a corresponding display pixel for two pixels which are closest to the display pixel among four adjacent pixels. Data for obtaining a difference between the gradation levels, calculating a display pixel value by a process corresponding to the difference between the gradation levels, and linearizing and correcting the relationship between the calculated display pixel value and an actual display pixel. It is composed of a processing circuit. Such a configuration is excellent in preservation of information of an original image, and is suitable for display of an image in which information such as text or drawing is not allowed to be lost in a method using a spatial light modulator such as a liquid crystal.

A projector according to claim 16 of the present invention
The data processing means includes a line buffer for accumulating three lines of digital image signals read from the frame memory, and display pixel data corresponding to an image for two lines stored earlier in the line buffer. A control circuit for reading from the line buffer four pixels corresponding to the coordinate data in the data read from the table, and a display obtained by inputting image data read from the line buffer and performing interpolation processing based on a linear interpolation method An interpolation processing circuit for setting a pixel value, an image processing circuit for linearizing and correcting a relationship between the display pixel value data subjected to the interpolation processing and an actual display image and outputting correction processing output image data, Timing for adjusting the timing of reading the correction processing output image data based on the read address of the interpolation table And a grayed adjustment circuit. With such a configuration, the preservation of the information of the original image is excellent, and it is suitable for displaying an image in which information such as text or drawing is not allowed to be lost in a method using a spatial light modulator such as a liquid crystal.

A projector according to claim 17 of the present invention
The data processing means inputs a digital image signal output from the frame memory read out in synchronization with a basic clock output from the arithmetic processing circuit, and determines a relationship between the input image signal and an actual display image. It is an image processing circuit to make it linear. With such a configuration, it is possible to prevent loss of image information and adjust the size of the divided projection image while maintaining the input image quality, and to display an image in which loss of information such as text or drawing is not allowed. It is suitable for. 19. A digital / analog converter according to claim 18, wherein said driving means for image projection means converts the corrected output image data output from said data processing circuit into an analog signal and supplies it to said image projection means. A liquid crystal drive control signal generation circuit that outputs a control signal for controlling the driving of the image projection unit based on the basic clock, the horizontal scan reference timing signal, and the vertical scan reference timing signal output from the read processing unit; Is provided. With such a configuration, light modulation and driving of the liquid crystal panel can be performed with a simple configuration.

A projector according to claim 19 of the present invention
The driving unit for the image projection unit is configured to control the illumination optical system of the image projection unit based on a rotation speed detection signal of the illumination optical system of the image projection unit, a basic clock output from the arithmetic processing circuit, and the horizontal scanning reference timing signal. And a vertical drive circuit for vertically driving the illumination optical system of the image projection means based on a vertical scanning reference timing signal output from the arithmetic processing means. With such a configuration, horizontal scanning and vertical scanning of light modulated by performing horizontal driving and vertical driving of the illumination optical system can be easily performed. According to a twentieth aspect of the present invention, in the projector, the image projecting means modulates the light of the three primary colors by an analog image signal, and a light source that continuously generates light of the three primary colors of red, green, and blue at a constant power. An optical modulator, a unit for combining light modulated by the optical modulator into one light, a polygon motor driven by an output of a horizontal drive circuit in the adjusting unit, and the adjusting unit A galvano motor driven by the output of the vertical drive circuit, a polygon mirror rotated by the polygon motor and reflected in the horizontal direction when the synthesized light is incident, and a polygon mirror driven by the galvano motor in the vertical direction. When the reflected light from the polygon mirror enters due to the reciprocating motion, the reflected light is reflected and scanned in the vertical direction to guide the screen to the screen. And a galvanometer mirror for forming a display image to. With such a configuration, light modulation by an analog image signal and horizontal scanning and vertical scanning of the modulated light can be easily performed.

An image forming method according to a twenty-first aspect of the present invention comprises:
In a projector that forms one display image by dividing and projecting one screen by a plurality of image projecting units, each of the divided projected images from the plurality of image projecting units is projected on a screen so that a part of the divided projected images overlaps each other. A first step of arranging the plurality of image projecting means, and each of the plurality of image projecting means so as to project only an image from any one of the image projecting means to each pixel of a divided image of a portion overlapping on the screen. A second step of adjusting the size of the divided projection image by the adjusting unit. With such a configuration, it is possible to prevent the images from overlapping each other at the boundary of the divided images and to prevent a gap from being generated between the divided images, thereby preventing the deterioration of the image quality and maximizing the display performance. It is excellent in cost performance. In the image forming method according to the present invention, the size of each of the divided projection images is adjusted by cutting out a peripheral portion of the original divided image. With such a configuration, the means for trimming the periphery of the divided image is provided in the adjustment means for adjusting the size of the divided image, and by cutting the periphery of the image, the importance of the information in the case of an image or the like is reduced. Normally, the lower the nearer the peripheral part, the lower the influence of the loss of the peripheral image.

An image forming method according to claim 23 of the present invention comprises:
The size of each divided projection image is adjusted by converting the resolution of the original divided image. With such a configuration, it is possible to adjust the size of the divided projection image while preventing loss of the image and maintaining the input image quality, and display an image such as a text or a drawing in which loss of information is not allowed. It is suitable for the case. In the image forming method according to claim 24 of the present invention, the size of each of the divided projection images is adjusted by changing the pixel density of the original divided image. With such a configuration, it is possible to adjust the size of the divided projection image while preventing loss of the image and maintaining the input image quality, and when displaying an image in which information such as text or drawing is not allowed to be lost. It is suitable.

[0036]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a projector and an image forming method according to the present invention will be described in detail with reference to the drawings based on embodiments of the present invention. FIG. 1 is a schematic configuration explanatory view of a projector according to a first embodiment of the present invention, in which one screen is divided into a plurality of images and projected on the screen, so that one display screen is displayed on the screen. 1 shows a configuration example of a multi-screen projector formed in FIG. In FIG. 1, an image dividing circuit 1 as an image dividing means
Include analog input image signals Ri (red), Gi (green),
Bi (blue) and these analog input image signals Ri, G
i, Bi, the vertical synchronizing signal VD and the horizontal synchronizing signal H
D is input. These analog input image signals Ri,
Gi, Bi, the vertical synchronizing signal VD, and the horizontal synchronizing signal HD are signals corresponding to one complete screen, and are output from, for example, an image information generating device such as a personal computer (not shown).

The analog input image signals Ri, Gi, Bi output from the image information generating device and the vertical synchronizing signal V
D, when the horizontal synchronizing signal HD is input to the image dividing circuit 1, the input image signal for one screen is divided into, for example, four, and the horizontal synchronizing signal and the vertical synchronizing signal correspond to each divided image. To generate analog image signals S1 to S1.
S4 is output and input to a plurality of divided projectors P1 to P4 corresponding to the number of divided images. The analog image signals S1 to S1
S4 collectively shows the analog image signal of the corresponding divided image, the horizontal synchronization signal, and the vertical synchronization signal. The divided projectors P1 to P4 are used as image projection means, generate divided projected images F1 to F4 based on the signals S1 to S4, respectively, and project the divided projected images F1 to F4 on the screen 2 to obtain an original image before the division. One screen is formed and enlarged and displayed (corresponding to claims 2 and 21). By the divided projectors P1 to P4, as in the related art,
When the divided images are projected on the screen 2, the divided projected images F <b> 1 to F <b> 4 are displayed in a state of being overlapped at each adjacent boundary as shown in FIG. 5, and the quality as one screen is deteriorated.

Therefore, in the present invention, the quality of the display screen on the screen is improved by forming one screen without overlapping the divided images at each adjacent boundary portion. Therefore, this first
The embodiment is configured as described below.
First, the case of the divided projectors P1 to P4 as image projection means will be described. FIG. 2 shows an illumination optical system of the divided projectors P1 to P4, FIG. 3 shows an electric system, and the divided projector P1
FIG. 9 is a block diagram illustrating a configuration of an adjusting unit that drives the liquid crystal panel in P4 to P4 and adjusts the size of the divided projection image. FIGS. 2 and 3 show the divided projectors P1 to P4.
The configuration of the divided projector P1 is shown as a representative. First, FIG. 2 will be described. The divided projector P1 shown in FIG.
Shows a liquid crystal projector as an example, and light P1b generated from a lamp light source P1a is made uniform by an integrator optical system including a first fly-eye lens P1c and a second fly-eye lens P1d, and further a condensing lens P
The light is focused on the liquid crystal panel P1g by 1e and P1f.

The liquid crystal panel P1g modulates the transmitted light by controlling the amount of transmitted light based on the image signal.
The modulated light is projected on the screen 2 by the projection lens P1h, so that the projection divided image F1 is formed on the screen 2. Next, the internal configuration of the electrical system of the divided projector P1 will be described with reference to FIG. Image dividing circuit 1 shown in FIG.
The analog image signal S1 of the analog image signals S1 to S4 output from is input to the divided projector P1,
As shown in FIG. 3, the analog image signal S1 includes the analog image signals Ri1 (red), Gi1 (green), and Bi1.
(Blue) and these analog image signals Ri1, Gi1,
The horizontal synchronization signal HD1 and the vertical synchronization signal VD1 corresponding to each of Bi1 are included. Analog image signal Ri
1, Gi1 and Bi1 are input to the video amplifier P1i, respectively, and after being amplified there, A / D (analog /
(Digital) converter P1j supplies the analog image signal ARi
(Red), AGi (green), and ABi (blue).

The horizontal synchronizing signal HD1 and the vertical synchronizing signal VD1 are input to a synchronizing signal extracting circuit P1k, a write address generating circuit P1m, and a synchronizing signal generating circuit P1n. The synchronization signal extraction circuit P1k includes a PLL circuit (not shown), reproduces and outputs the synchronization clock RCK of the analog image signals Ri1, Gi1, and Bi1 from the horizontal synchronization signal HD1, and outputs the A / D converter P1i and the frame memory. P1
o, output to the write address generation circuit P1m. The synchronization clock RC generated by the synchronization signal extraction circuit P1k
In synchronization with K, in the A / D converter P1j, the analog image signals Ri1, Gi amplified by the video amplifier P1i.
1 and Bi1 are digitally converted to digital image signal D.
Ri (red), DGi (green), and GBi (blue) are output to the frame memory P1o. On the other hand, the write address generation circuit P1m detects the number of scanning lines by counting the number of pulses of the horizontal synchronization signal HD1 within one vertical period of the input vertical synchronization signal VD1, and detects the number of scanning lines. The number of effective pixels in one horizontal period is detected from the output synchronous clock RCK, and the write address WAD
And outputs the write address WAD to the frame memory P1o.

Video amplifier P1i, synchronization signal extraction circuit P
1k, a write address generation circuit P1m, and an A / D converter P1j constitute a write unit of the frame memory P1o (corresponding to claims 9 and 26). The frame memory P1o sequentially writes the digitized digital image signals DRi, DGi, and GBi in synchronization with the synchronization clock RCK input from the synchronization signal extraction circuit P1k according to the designated write address WAD. The frame memory P1o has a dual-port function that can read data asynchronously with the operation of the write system. Therefore, the frame memory P1o stores the digital image signals DRi (red), DGi (green), DBi
Regardless of the (blue) write timing, the data is read out and input to the data processing circuit P1q by the read address signal RAD output from the read address generation circuit P1p (described later). Synchronous signal generation circuit P1
n, the read address generation circuit P1P constitutes an arithmetic processing means of a read system of the frame memory P1o.
(Corresponding to claim 10 and claim 27).

The synchronizing signal generating circuit P1n generates a basic clock TCK for the reading system of the frame memory P1o and outputs the basic clock TCK to the reading address generating circuit P1P and the data processing circuit P1q. Horizontal scanning reference timing signal HDR
, And the read address generation circuit P1P
To send to. These vertical scanning reference timing signals VD
The R and the horizontal scanning reference timing signal HDR serve as a vertical scanning reference timing signal and a horizontal scanning reference timing signal, respectively. On the other hand, the screen size generation circuit P1r outputs the size adjustment signal SZ of the divided image F1.
When C is input, the difference between the original screen size and the adjusted screen size is output. The horizontal difference signal HOFF and the vertical difference signal VOFF are output from the screen size adjustment circuit P1r, and the read address is output. It is sent to the generation circuit P1p. The size adjustment signal SZC can be used for a user-friendly system if the user of the projector can arbitrarily set the optimal value by operating buttons on a remote controller while watching the screen on the screen 2. realizable.

Thus, the screen size generation circuit P1r
Has a function of individually and arbitrarily adjusting the size of each divided projection image. The read address generation circuit P1p generates the read address signal RAD in synchronization with the basic clock TCK based on the horizontal scanning reference timing signal HDR and the vertical scanning reference timing signal VDR input from the synchronization signal generation circuit P1n, and generates the frame memory P1o. Output to However, the frame memory P
The vertical and horizontal read start addresses of 1o are shifted by the value of the vertical difference signal VOFF and the horizontal difference signal HOFF input from the screen size generation circuit P1r. 22). The read address generation circuit P1p sets the signal HFUL to "H" level in synchronization with the reading of the last pixel data in the horizontal direction from the frame memory P1o, and outputs the signal HFUL to the data processing circuit P1q. The read address generation circuit P1p outputs the signal VF in synchronization with the reading of the last pixel data of the last line in one screen of the frame memory P1o.
UL is set to the “H” level and output to the data processing circuit P1q.

The signal HFUL changes to "L" level immediately before the start of reading the first pixel of the next line based on the horizontal scanning reference timing signal HDR. The signal VFUL becomes the “L” level immediately before the start of reading the first pixel of the next screen based on the vertical scanning reference timing signal VDR. The data processing circuit P1q provided as data processing means is basically a circuit for linearly correcting the relationship between an input image signal and an actual display image on the liquid crystal panel P1g. This data processing circuit P1q receives the basic clock TCK output from the synchronization signal generation circuit P1n.
When the signals HFUL and VFUL output from the read address generation circuit P1p are both at the "L" level, the digital image signals DRr, DGr, and DBr output from the frame memory P1o are input and processed. If either HFUL or signal VFUL is at "H" level, black image data is output. As a result, the screen is shifted in the peripheral direction, and the remaining portion is substantially displayed as a black image.

The corrected output image data DRo, DGo, and DBo corrected by the data processing circuit P1q are input to the D / A converter P1s, and the analog signal AR
o, AGo, and AGo. In this case, the data processing circuit P1q has a function of cutting out the peripheral portion of the original divided image and adjusting the size of each divided projected image. Further, the liquid crystal drive control signal generation circuit P1t includes a basic clock TCK output from the synchronization signal generation circuit P1n,
A control signal LCD for driving the liquid crystal panel P1g (see FIG. 2) is generated and output based on the vertical scanning reference timing signal VDR and the horizontal scanning reference timing signal HDR. This control signal LCD, together with the analog signals ARo, AGo, and ABo output from the D / A converter P1s,
Output to the liquid crystal panel P1h. The D / A converter P1s and the liquid crystal drive control signal generation circuit P1t constitute driving means for image projection means (corresponding to claims 8 and 18).

The other divided projectors P2 to P4 are similarly constructed and controlled, and as a result, on the screen 2, as shown in FIG. One high quality enlarged display image without overlapping and gaps is obtained. Next, the configuration of the data processing circuit P1q will be described with reference to FIG. FIG. 4 is a block diagram showing the internal configuration of the data processing circuit P1q (corresponding to claim 14). The signal HFUL output from the read address generation circuit P1p shown in FIG.
When VFUL is input to the OR circuit P1q1,
The selection signal SEL is input to the selection circuit P1q2. The selection circuit P1q2 includes the frame memory P1o shown in FIG.
, The digital image data DRr, DGr,
DBr, and the black data DRb, Db output from the black data output circuit P1q3.
Gb and DBb are also input.

The selection signal SEL input to the selection circuit P1q2 is a logical sum of the signal HFUL and the signal VFUL, that is, a signal that has passed through the OR circuit P1q1, and the selection signal SEL is input to the selection circuit P1q1. When the selection signal SEL is at "L" level, the selection circuit P1q1 selects and passes the digital image data DRr, DGr, DBr from the frame memory P1o. The digital image data DRr, DGr, DBr that has passed through the selection circuit P1q1 is input to the image processing circuit P1q4. When the selection signal SEL is at the “H” level, the selection circuit P1q2 selects the black data DRb, DGb, DBb output from the black data output circuit P1q3, and sends it to the image processing circuit P1q4. Image processing circuit P1
Q4 is the digital image data DRr, DGr, DBr input from the selection circuit P1q2 and the liquid crystal panel P1g.
Then, the relationship with the actual display image displayed on the screen 2 (on the screen 2) is linearized and corrected and output to the D / A converter P1s shown in FIG.

Next, a description will be given of a second embodiment of the projector and the image forming method according to the present invention. FIG.
Is a block diagram illustrating a configuration of an adjusting unit that adjusts the size of the divided image, and illustrates the adjusting unit in the divided projector P1 among the divided projectors P1 to P4 as a representative.
7, the same parts as those of the adjusting means shown in FIG. 3 are denoted by the same reference numerals. The portion of the writing means by the address generation circuit P1m is the same as that of the first embodiment, and the illustration of the portion is omitted. In FIG. 7, the main differences from FIG. 3 are that the arithmetic processing circuit P1u as the arithmetic processing is provided including the function of the synchronization signal generating circuit P1n shown in FIG. 3, and the interpolation table P1v is newly added. It is provided in. The arithmetic processing circuit P1u receives the horizontal synchronizing signal HD1 and the vertical synchronizing signal VD1 included in the analog image signal S1, and inputs a basic clock signal TCK of a reading system of the frame memory P1o, a vertical scanning reference timing signal VDR, and a horizontal scanning. Reference timing signal HD
R is generated and output.

The basic clock signal TCK is sent to a read address generation circuit P1p, a data processing circuit P1q, and a liquid crystal drive control signal generation circuit P1t. The vertical scanning reference timing signal VDR and the horizontal scanning reference timing signal HDR are sent to a read address generation circuit P1p and a liquid crystal drive control signal generation circuit P1t, respectively. Also,
The arithmetic processing circuit P1u receives the horizontal difference output signal HOFF and the vertical difference output signal VOFF from the screen size generation circuit P1r, and determines the size based on the horizontal difference output signal HOFF and the vertical difference output signal VOFF. The adjusted number of pixels is made to correspond to the original number of display pixels of the liquid crystal panel P1g, and the number of display pixels of the liquid crystal panel P1g is mapped to the coordinate system of the image after the size adjustment and coordinate-converted. Is generated and output.
Table data WD output from arithmetic processing circuit P1u
Are sequentially written to the dedicated memory of the interpolation table P1v according to the write address WATD output from the arithmetic processing circuit P1u and the write control signal WT.

The table data WD written in the interpolation table P1v is converted into image data TD according to the read address RTAD output from the data processing circuit P1q.
And input to the data processing circuit P1q.
(Corresponding to claim 3, claim 11, claim 25, claim 28, and claim 31). FIG. 8 shows the pixels S00 to S11 of the adjusted image when each display pixel of the liquid crystal panel P1g is mapped to the coordinate system of the image after the size adjustment, and the liquid crystal panel P1g.
Of the display pixel Sxy. FIG. 9 shows a table data format for the display pixel value Sxy. The “ADS” in FIG.
"00" is coordinate data on the image after the size adjustment of the pixel S00 of the adjusted image shown in FIG. 8, and "x1" and "x
"2", "y1", and "y2" are coordinate data of the display pixel value Sxy as shown in FIG. Here, returning to FIG. 7, the data processing circuit P1q in FIG. 7 generates a read address RTAD and outputs it to the interpolation table P1v.

The data processing circuit P1q sequentially reads out the image data TD from the interpolation table P1v based on the read address RTAD, and inputs the image data TD to the data processing circuit P1q. From S11, the difference between the gradation levels of the two pixels closest to the display pixel is obtained. The data processing circuit P1q calculates a display pixel value by a process according to the obtained difference between the gradation levels. The data processing circuit P1q
With respect to the pixel data of the calculated pixel display value, the relationship between the pixel data and the actual display pixel is linearized and output. The address data DAD corresponding to the pixel data output from the data processing circuit P1q is also output and sent to the liquid crystal drive control signal generation circuit P1t (corresponding to claims 15 and 34). Subsequent operations are the same as those in FIG. The detailed internal configuration of the data processing circuit P1q in the adjustment means shown in FIG. 7 is shown as a block diagram in FIG.

In FIG. 10, the line buffer P1
q5 is a digital image signal DRr, DG read from the frame memory P1o based on the basic clock TCK output from the arithmetic processing circuit P1u shown in FIG.
r and DBb are sequentially accumulated for three lines. Further, the control circuit P1q6 sequentially reads the image data TD of the display pixels corresponding to the two lines of images previously stored in the line buffer P1q5 from the interpolation table P1v based on the read address signal RAD input from the read address generation circuit P1p. Read, and the coordinate data AD in the image data TD.
The corresponding four pixels from S00 are transferred to the line buffer P1q.
5, pixel data SR (red), SG from the line buffer P1q5 based on the read address LBAD for
(Green) and SB (blue) are read out. This pixel data SR,
SG and SB are collective outputs of pixel data of four pixels of red, green and blue, respectively. The pixel data SR, SG, and SB read from the line buffer P1q5 are input to the interpolation processing circuit P1q7.

The interpolation processing circuit P1q7 sets the display pixel value based on the linear interpolation method. That is, the corresponding display pixel value Sxy is Sxy =
S00 · x2 · y2 + S10 · x1 · y2 + S01 · x
It can be obtained by 2 · y1 + S11 · x1 · y1.
Pixel data interpolated by the interpolation processing circuit P1q7 is
Sent to the image processing circuit P1q8,
In 1q8, the actual liquid crystal panel P1g (hence,
Linearization processing is performed on the relationship with the display image on the screen 2), and correction processing output image data DRo, DGo, and DBo are output. The correction processing output image data DRo, DGo,
Address data DAD corresponding to reading of DBo is:
By inputting the read address signal RAD of the interpolation table P1v to the timing adjustment circuit P1q9 by the read address generation circuit P1p, the timing adjustment circuit P1
The timing is appropriately adjusted at 1q9 and output in synchronization with the correction processing output image data DRo, DGo, DBo.
(Corresponding to claim 16 and claim 32).

Next, a third embodiment of the projector and the image forming method according to the present invention will be described. FIG.
FIG. 13 to FIG. 13 are diagrams showing the configuration of the third embodiment.
Of the plurality of image projection means, the divided projector P1 is shown as a representative. 11 to 13, FIG.
FIG. 1 is a block diagram illustrating a configuration of an adjusting unit that adjusts the size of each divided projection image in the divided projector P1.
FIG. 2 is an explanatory diagram showing a configuration of an illumination optical system in the divided projector P1. FIG. 13 is an explanatory diagram of a configuration of a rotation detector of a polygon motor in the illumination optical system shown in FIG. In FIG. 11, as in the case of FIG. 7, illustration of the writing means by the video amplifier P1i, the synchronization signal extraction circuit P1k, the write address generation circuit P1m, and the A / D converter P1j shown in FIG. 3 is omitted. In addition, the same reference numerals are given to the same portions as those in FIG.

In FIG. 11, the arithmetic processing circuit P1u
And the read address generation circuit P1p constitute an arithmetic processing means of a read system of the frame memory P1o.
(Corresponding to claim 12). The horizontal synchronization signal HD1, the vertical synchronization signal VD1, the horizontal difference signal HOFF and the vertical difference signal VOFF output from the screen size generation circuit P1r are input to the arithmetic processing circuit P1u. You. Based on the horizontal synchronization signal HD1, the vertical synchronization signal VD1, the horizontal direction difference signal HOFF, and the vertical direction difference signal VOFF, the arithmetic processing circuit P1u calculates the basic clock TCK of the readout system of the frame memory P1o having a cycle suitable for the screen size. , Horizontal scanning reference timing signal HDR and vertical scanning reference timing signal VD
R is generated and output. The basic clock TCK output from the arithmetic processing circuit P1u includes a read address generation circuit P1p, an image processing circuit P1q8, and a horizontal drive circuit P1w.
Sent to The horizontal scanning reference timing signal HDR output from the arithmetic processing circuit P1u is sent to the read address generation circuit P1p and the horizontal drive circuit P1w.

Further, the vertical scanning reference timing signal VD
R is sent to the read address generation circuit P1p and the vertical drive circuit P1x. In the case of an optical scanning projector that forms an image by the split projector P1 scanning the output light power-modulated according to the input pixel data,
There is a characteristic that the resolution and the pixel density (screen size) can be arbitrarily changed by changing the modulation speed and the scanning speed of the scanning light. That is, even if the scanning speed is the same, when the modulation speed is made higher, the screen size becomes smaller (the pixel density increases). If the modulation speed is constant, the screen size can be reduced even if the scanning speed is reduced. Therefore, in the vertical direction of the screen size, the screen size is reduced by shortening the period of the vertical scanning reference timing signal VDR output from the arithmetic processing circuit P1u. In the horizontal direction of the screen size, the screen size is reduced by shortening the cycle of the basic clock TCK, which is a read clock for the frame memory P1o, or shortening the cycle of the horizontal scanning reference timing signal HDR. 4 to 7, and 24.
Corresponding to).

The basic clock TCK, vertical scanning reference timing signal VDR, horizontal scanning reference timing signal H
For the generation of DR, for example, the horizontal difference signal H
This can be realized by controlling the voltage controlled oscillator by the D / A converter P1s whose output voltage changes in accordance with the OFF and vertical difference signal VOFF (corresponding to claim 13). The read address generation circuit P1p receives the horizontal scanning reference timing signal H output from the arithmetic processing circuit P1u.
DR, the basic clock TC output from the arithmetic processing circuit P1u based on the vertical scanning reference timing signal VDR.
A data read address signal RAD is generated from the frame memory P1o in synchronization with K, and based on the read address signal RAD, the digital image data DRr, DGr, and DBr are read from the frame memory P1o and sent to the image processing circuit P1q8.

The image processing circuit P1q8 receives the input image signal,
That is, the digital image data DRr, DGr, DBr
The digital image data DRr, DGr, and DBr output from the frame memory P1o are processed to linearize the relationship between the image data and the actual display image on the liquid crystal panel P1g.
The correction processing output image data DRo, DGo, and DBo are output.

This correction processing output image data DRo, DG
o and DBo are input to the D / A converter P1s, where they are converted into analog signals (corresponding to claim 17). D / A
Analog signals ARo, AG output from converter P1s
o and ABo are respectively input to the optical modulators 3R, 3G, and 3B of the illumination optical system in the divided projector shown in FIG. In FIG. 12, red, green, and blue laser light sources 4R, 4G, and 4B are light sources that continuously generate laser beams of three primary colors of red, green, and blue at a constant power. Note that the laser light sources 4R, 4G, 4B
However, the SHG element (Scond
(Harmonic Generation: second harmonic generation element), a gas laser, or the like, and need not be a laser diode. These laser light sources 4R, 4
The continuous light generated from G, 4B is transmitted to the optical modulators 3R, 3G,
3B.

As described above, the analog signals ARo, AGo, and ABo input from the D / A converter P1s are input to the optical modulators 3R, 3G, and 3B. In 3G and 3B, continuous lights generated from laser light sources 4R, 4G and 4B are modulated based on analog signals ARo, AGo and ABo, respectively. The continuous light modulated by the optical modulators 3R, 3G, 3B is reflected by mirrors 5R, 5G (5G is not shown) and 5B,
Further, the laser beam 7 is synthesized by the synthesizing prism 6 to form one laser beam 7.
become. The method of synthesizing the single laser beam 7 is not limited to the synthesizing method using the synthesizing prism 6 as described above. The combined laser light 7 is incident on a polygon mirror 8. The polygon mirror 8 is a polygon mirror that rotates in the horizontal direction with respect to the incident laser light 7, and thus reflects and scans the incident laser light 7 in the horizontal direction. The laser light 7 reflected by the polygon mirror 8 is incident on the galvano mirror 9.

The galvanomirror 9 reflects the incident laser light 7
Is a mirror that reciprocates in the vertical direction, so that the laser beam 7 incident by the galvanometer mirror 9 is reflected and scanned in the vertical direction. The laser beam 7 reflected by the galvanometer mirror 9 is projected on the screen 2, and as a result, an image is displayed on the screen 2. Next, a drive system of the polygon mirror 8 and the galvanometer mirror 9 will be described. First, the polygon mirror 8 is connected to a polygon motor 10 and is driven to rotate by the polygon motor 10. As shown in FIG.
Are driven by the polygon motor drive signal PMD output from the horizontal drive circuit P1w shown by. The horizontal driving circuit P1w includes a basic clock TCK and a horizontal scanning reference timing signal HD output from the arithmetic processing circuit P1u.
The polygon motor drive signal PMD is output based on R and supplied to the polygon motor 10 as described above to drive the polygon motor 10.

The horizontal drive circuit P1w and the vertical drive circuit P1t
Thus, the driving means for the image projecting means is constituted (corresponding to claim 20). Although not shown in FIG. 12, the polygon motor 10 is provided with a rotation detector described later with reference to FIG. The polygon motor 10 is driven by this rotation detector.
Is detected, and a rotation speed detection signal is output. FIG. 13 is an explanatory diagram of the configuration of the polygon mirror 8 and the galvanometer mirror 9 as viewed from a direction along the vertical scanning direction of the laser beam 7 by the galvanometer mirror 9. As apparent from FIG. 13, the rotation detector includes a laser diode 11 and a photodiode 12. The polygon mirror 8 is continuously irradiated with light from the laser diode 11, and the reflected light from the polygon mirror 8 is received by the photodiode 12. Each time the angle formed by the above becomes a predetermined value, the irradiation light is received by the photodiode 12, converted into an electric signal by the photodiode 12, and output as the rotation speed detection signal PMRD.

This rotation speed detection signal PMRD is
Is sent to the horizontal drive circuit P1w indicated by. Accordingly, the horizontal drive circuit P1w controls the polygon motor drive signal PMD so as to synchronize with a predetermined timing relationship with the horizontal scan reference timing signal HDR input from the arithmetic processing circuit P1u, and supplies the signal to the polygon motor 10. I do. A vertical drive circuit P1 for supplying a drive current to a galvano motor 13 for driving the galvanometer mirror 9
As shown in FIG. 11, t generates a galvano motor drive signal GMD based on the vertical scanning reference timing signal VDR input from the arithmetic processing circuit P1u, and controls the drive of the galvano motor 13. It should be noted that the adjusting means for adjusting the size of each divided projection image can be realized by, for example, changing the magnification of a lens. The present invention is not limited to the embodiment described above and shown in the drawings, and can be implemented with various modifications without departing from the scope of the invention.

[0064]

As described above, according to the first aspect of the present invention, in a projector that forms one display image by dividing and projecting one screen into a plurality of divided images, a plurality of divided projected images are A plurality of image projection units arranged so as to form one display image by being projected so as to partially overlap each other on the screen, and a configuration including an adjustment unit for adjusting the size of each of the divided projection images; As a result, it is possible to improve the quality of the display screen by eliminating the overlap and gaps between the adjacent borders of the divided images displayed on the screen, and to maximize the display performance to achieve excellent cost performance. A projector can be provided. According to the second aspect of the present invention, the size of the divided image is adjusted by cutting out the peripheral portion having low importance as information, so that the processing is very easily realized, and the cost is further reduced. The projector which can be provided can be provided. According to the third aspect of the present invention, since the size of the divided image is configured by performing resolution conversion, the original image information preservability such as a linear interpolation method or a cubic convolution interpolation method is excellent as an interpolation process in the resolution conversion. Provided is a projector which can be realized by adopting a method, and which is particularly suitable for displaying an image such as a text or a drawing in which loss of information is not allowed in a method using a spatial light modulation element such as a liquid crystal. be able to.

According to the fourth aspect of the present invention, the size of the divided image is adjusted by changing the pixel density with high original image information preservability, so that loss of the image is prevented and the input image quality is reduced. It is possible to provide a high-definition and low-cost projector for a wide range of applications, while being able to cope with holding. According to the fifth aspect of the present invention, in an optical scanning projector that forms an image by scanning output light that has been power-modulated in accordance with input pixel data, the output light scan is used as a means for changing the pixel density. Since the means for changing the speed is adopted, it is possible to respond to an image input of any pixel density while maintaining its image quality, and to provide a high-definition and low-cost projector for a wide range of applications. According to the invention of claim 6, in the optical scanning type projector that forms an image by scanning output light power-modulated according to input pixel data, the means for changing the pixel density includes: Since the modulation speed is changed, the size of the divided image can be arbitrarily adjusted by changing the pixel density with high original image information preservation, and the image quality can be adjusted for any resolution image input. , And a high-definition and low-cost projector can be provided in a wide range of applications.

According to the seventh aspect of the present invention, the size of each of the divided projection images is individually and arbitrarily adjusted, so that the user can flexibly cope with any situation arbitrarily according to the situation of the screen. It is possible to provide a projector applicable to a wider range of applications. According to the eighth aspect of the present invention, the adjusting means synchronizes the digital image signal with the synchronous clock generated by the horizontal synchronizing signal and the vertical synchronizing signal for each of the divided projection images, and adjusts the number of scanning lines in one vertical period. Writing means for writing with a write address generated based on the number of effective pixels within one horizontal period from the synchronous clock; a frame memory for writing the digital image signal in synchronization with the synchronous clock according to the write address; A screen size generation circuit for generating a horizontal difference output signal and a vertical difference output signal of a difference between the screen size after adjustment by the size adjustment signal of the divided projection image and the screen size of each original divided projection image; Only the value of the direction difference output signal and the value of the vertical direction difference output signal are written into the frame memories in the horizontal and vertical directions. The read start address of the digital image signal is shifted, and the digital image written in the frame memory by the basic clock generated from the horizontal synchronization signal and the vertical synchronization signal, the vertical scanning reference timing signal, and the horizontal scanning reference timing signal. An arithmetic processing means for reading out a signal; and a signal synchronized with the reading of the last pixel data in the horizontal direction of the frame memory by the arithmetic processing means, based on the horizontal scanning reference timing signal, to start reading the first pixel of the next line. A signal synchronized with the reading of the last pixel data of the last line of one screen at the immediately preceding “L” level and the “L” immediately before the reading of the first pixel of the next screen is started based on the vertical scanning reference timing signal. Level, the data read from the frame memory is read. The linear image correction processing is performed on the relationship between the input image signal and the actual display image with respect to the digital image signal, and when one of the horizontal scanning reference timing signal and the vertical scanning reference timing signal is at “H” level, Data processing means for obtaining output image data corrected so as to output black image data; and driving the image projection means by the basic clock, the horizontal scanning reference timing signal, and the vertical scanning reference timing signal to drive the data. The image processing device is provided with a driving device for image projection device that supplies correction processing output image data output from the processing device to the image projection device. Can prevent the image quality from deteriorating, and can easily and arbitrarily adjust the screen size by the user. Can be provided.

According to the ninth aspect of the present invention, the writing means includes: a synchronization signal extracting circuit for generating the synchronization clock based on the horizontal synchronization signal and the vertical synchronization signal for each of the divided projection images; An analog / digital converter for converting an analog image signal of the divided projection image into a digital image signal in synchronism with the digital image signal;
A write address generation circuit for detecting the number of scanning lines from the horizontal synchronization pulse in the vertical period and detecting the number of effective pixels in one horizontal period from the synchronization clock to generate a write address; An analog image signal of the divided image thus divided can be written to the frame memory with a simple configuration. According to the tenth aspect of the present invention, the arithmetic processing unit generates a basic clock, a horizontal scanning reference timing signal, and a vertical scanning reference timing signal from the horizontal synchronization signal and the vertical synchronization signal; Based on a horizontal scanning reference timing signal and the vertical scanning reference timing signal, a read address of the digital image signal is generated from the frame memory in synchronization with the basic clock, and a read address of the horizontal difference signal and the vertical difference signal is generated. A read address generation circuit for shifting the read start address of the digital image signal in the horizontal and vertical directions by a value, so that when the image signal is read from the frame memory, the difference between the horizontal difference signal and the vertical difference signal is obtained. Value The read start address can be shifted in the horizontal and vertical directions. The overlapping of the adjacent portion of the divided projection image can be provided a projector that can reliably prevented.

According to the eleventh aspect of the present invention, the arithmetic processing means generates the basic clock, the horizontal scanning reference timing signal, and the vertical scanning reference timing signal from the horizontal synchronization signal and the vertical synchronization signal. The number of pixels whose size has been adjusted based on the horizontal direction difference signal and the vertical direction difference signal and the original number of display pixels in the image projection means, and the display pixels in the image projection means have the coordinates of the image after size adjustment. To an interpolation processing table data generated after the conversion, a write control signal, a calculation processing circuit for generating a write address, and the horizontal scanning reference timing signal and the vertical scanning reference timing signal output from the calculation processing circuit. Reads a digital image signal from the frame memory in synchronization with the basic clock A read address generation circuit that generates an address signal and shifts a read start address of the digital image signal written in the frame memory in the horizontal direction and the vertical direction by the value of the horizontal difference signal and the vertical difference signal. And an interpolation table for writing the interpolation processing table data in accordance with the write address and the write control signal, so that when reading an image signal from the frame memory, the value of the horizontal difference signal and the vertical difference signal is used. It is possible to provide a projector capable of shifting the read start address in the horizontal direction and the vertical direction, preventing loss of image information, and adjusting the size of the divided projection image while maintaining the input image quality.

According to the twelfth aspect of the invention, the arithmetic processing means reduces the horizontal screen size based on the horizontal synchronization signal, the vertical synchronization signal, the horizontal difference signal, and the vertical difference signal. A basic clock for reading a digital image signal from the frame memory with a shorter period, a horizontal scanning reference timing signal,
An arithmetic processing circuit for generating a vertical scanning reference timing signal whose cycle is shortened in order to shorten the vertical screen size, the basic clock output from the arithmetic processing circuit, the horizontal scanning reference timing signal, and the vertical scanning A read address generation circuit that outputs a read address signal that reads a digital image signal from the frame memory in synchronization with a basic clock output from the frame memory based on a reference timing signal in the arithmetic processing circuit. The resolution and pixel density of the displayed image in the optical scanning projector can be changed arbitrarily.
A projector capable of easily adjusting the size of an image can be provided.

According to a thirteenth aspect of the present invention, the arithmetic processing means converts the basic clock, the horizontal scanning reference timing signal, and the vertical scanning reference timing signal into the horizontal difference output signal and the vertical difference signal, respectively. The voltage controlled oscillator is controlled by the output of the digital-to-analog converter whose output voltage changes according to the output of the digital clock. Thus, it is possible to provide a projector capable of obtaining a stable display screen with a small change in size after the screen size is adjusted. According to the fourteenth aspect of the present invention, the data processing means obtains a logical sum of a signal synchronized with the reading of the frame memory and a signal synchronized with the reading of the last pixel data of the last line of the one screen to generate a selection signal. O to output
An R circuit for selecting and outputting the digital image signal output from the frame memory when the selection signal is at "L" level, and outputting a black signal from the black data output circuit when the selection signal is at "H"level; The configuration includes a selection circuit for selecting and outputting data, and an image processing circuit for linearizing and correcting the relationship between the digital image signal output from the selection circuit and the actual image and outputting the result. It is possible to provide a projector which does not substantially display the black image in the peripheral portion of the image and hardly affects the lack of the peripheral portion in the divided image.

According to the fifteenth aspect of the present invention, the data processing means reads the interpolation table data written in the interpolation table and sets the corresponding display pixel to the nearest one of the four adjacent pixels. A gradation level difference is obtained for the pixel, a display pixel value is calculated by a process according to the gradation level difference, and a relationship between the calculated display pixel value and an actual display pixel is linearized. It is excellent in preservation of the information of the original image, and is suitable for displaying images such as texts and drawings where the loss of information such as text and drawings is not allowed by using a spatial light modulator such as liquid crystal. A projector can be provided. According to a sixteenth aspect of the present invention, the data processing means stores a line buffer for storing three lines of digital image signals read from the frame memory, and an image for two lines stored before the line buffer. A control circuit that reads display pixel data corresponding to the pixel data from the interpolation table and reads four corresponding pixels from the line buffer from the coordinate data in the data, and inputs image data read from the line buffer and performs linear interpolation An interpolation processing circuit that sets a display pixel value that has been subjected to interpolation processing based on a method, and corrects the output pixel data that has been subjected to the interpolation processing by linearizing and correcting the relationship between the display pixel value data and the actual display image. An image processing circuit that outputs the correction processing output image data based on the read address of the interpolation table. It is equipped with a timing adjustment circuit that adjusts the timing, so it is excellent in preserving the information of the original image and displaying images such as text and drawings in which loss of information such as text and drawings is not allowed by using a spatial light modulation element such as liquid crystal Thus, it is possible to provide a projector suitable for such purposes.

According to a seventeenth aspect of the present invention, the data processing means inputs a digital image signal output from the frame memory which is read out in synchronization with the basic clock output from the arithmetic processing circuit and receives an input image signal. By configuring the image processing circuit to linearize the relationship between the signal and the actual display image, it is possible to prevent loss of image information and adjust the size of the divided projection image while maintaining the input image quality. Thus, it is possible to provide a projector suitable for displaying an image in which loss of information such as text and drawings is not allowed. According to the eighteenth aspect of the present invention, the image projection means driving means converts the corrected output image data output from the data processing circuit into an analog signal and supplies the analog signal to the image projection means. A liquid crystal drive control signal generation circuit that outputs a control signal for controlling the driving of the image projection unit based on the basic clock, the horizontal scan reference timing signal, and the vertical scan reference timing signal output from the read processing unit; Therefore, it is possible to provide a projector capable of performing light modulation and driving of a liquid crystal panel with a simple configuration.

According to the nineteenth aspect of the present invention, the driving means for the image projecting means comprises: a rotation speed detection signal of an illumination optical system of the image projecting means; a basic clock output from the arithmetic processing circuit; A horizontal drive circuit for horizontally driving the illumination optical system of the image projection means with a timing signal; and a vertical drive for vertically driving the illumination optical system of the image projection means based on a vertical scanning reference timing signal output from the arithmetic processing means. With the configuration including the driving circuit, it is possible to provide a projector that can easily perform horizontal scanning and vertical scanning of modulated light by performing horizontal driving and vertical driving of the illumination optical system. According to the twentieth aspect, the image projecting means modulates the light of the three primary colors with an analog image signal, and a light source that continuously generates light of the three primary colors of red, green, and blue at a constant power. An optical modulator, a unit for combining light modulated by the optical modulator into one light, a polygon motor driven by an output of a horizontal drive circuit in the adjusting unit, and the adjusting unit A galvano motor driven by the output of the vertical drive circuit, a polygon mirror rotated by the polygon motor and reflected in the horizontal direction when the synthesized light is incident, and a polygon mirror driven by the galvano motor in the vertical direction. When the reflected light of the polygon mirror is incident by reciprocating motion, the reflected light is reflected and scanned in the vertical direction and guided to the screen, thereby displaying the image on the screen. Since a configuration and a galvanometer mirror for forming an optical modulation by the analog image signal the modulated horizontal scanning of light, it is possible to provide a projector that the vertical scanning may readily performed.

According to the twenty-first aspect of the invention, in a projector for forming one display image by dividing and projecting one screen by a plurality of image projecting means, each divided projected image from the plurality of image projecting means is A first step of arranging the plurality of image projecting means for projecting a part of the image onto the screen so as to partially overlap each other, and any one of the image projections for each pixel of the divided image of the overlapping part on the screen And a second step of adjusting the size of each of the divided projected images by the adjusting means so as to project only the image from the means. The image quality can be prevented from deteriorating, and the display performance can be maximized. It is possible to provide an image forming method of the injector. According to the twenty-second aspect of the present invention, the size of each of the divided projection images is adjusted by cutting off a peripheral portion of an image having low importance as information, so that image quality does not deteriorate. In addition, it is possible to provide an image forming method in which processing can be realized very easily and cost can be reduced.

According to the twenty-third aspect of the present invention, the size of each of the divided projection images is adjusted by converting the resolution of the original divided image. It can be realized by adopting a method excellent in preserving original image information such as a cubic convolution interpolation method, and a method using a spatial light modulation element such as a liquid crystal cannot lose information such as text and drawings. An image forming method particularly suitable for displaying an image can be provided. According to the twenty-fourth aspect of the present invention, the size of each of the divided projection images is adjusted by changing the pixel density of the original divided image, thereby preventing loss of the image and maintaining the input image quality. The size of the divided projection image can be adjusted, and an image forming method suitable for displaying an image in which loss of information such as text or drawing is not allowed can be provided.

[Brief description of the drawings]

FIG. 1 is a configuration explanatory diagram showing a schematic configuration of a first embodiment of a projector according to the present invention.

FIG. 2 is an explanatory diagram of a configuration of an illumination optical system according to the first embodiment of the projector according to the present invention.

FIG. 3 is a block diagram illustrating a configuration of an adjustment unit that adjusts the size of a divided projection image in the first embodiment of the projector according to the present invention.

FIG. 4 is a block diagram showing an internal configuration of a data processing circuit in the adjustment means of FIG. 3;

FIG. 5 is an explanatory diagram showing a state in which divided images displayed on a screen by a conventional projector overlap images at mutually adjacent boundaries.

FIG. 6 is an explanatory diagram showing a state in which adjacent borders of divided images displayed on a screen by the projector according to the present invention do not overlap with each other.

FIG. 7 is a block diagram illustrating a configuration of an adjustment unit that adjusts the size of a divided projection image in a second embodiment of the projector according to the present invention.

FIG. 8 illustrates a relationship between pixels of an adjusted image and display pixels of a liquid crystal panel when each display pixel of a liquid panel is mapped to a coordinate system of an image after size adjustment in a second embodiment of the projector according to the present invention. FIG.

9 is an explanatory diagram of a table data format for a display pixel Sxy shown in FIG.

FIG. 10 is a block diagram showing an internal configuration of a data processing circuit in the adjustment means of FIG. 7;

FIG. 11 is a block diagram illustrating a configuration of an adjusting unit that adjusts the size of a divided projection image in a third embodiment of the projector according to the present invention.

FIG. 12 is a configuration explanatory view showing a schematic configuration of a divided projector in a third embodiment of the projector according to the present invention.

13 is an explanatory diagram showing a configuration of a rotation detector of a polygon motor used in the divided projector shown in FIG.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Image division circuit 2 Screen 3R, 3G, 3B Light modulator 4R, 4G, 4B Laser light source 5R, 5G, 5B Mirror 6 Synthetic prism 7 Laser light 8 Polygon mirror 9 Galvanometer 10 Galvanometer motor 11 Laser diode 12 Photodiode 13 Galvanometer motor F1 to F4 Divided projection image P1 to P4 Divided projector P1g Liquid crystal panel P1i Video amplifier P1j A / D converter P1k Synchronization signal extraction circuit P1m Write address generation circuit P1n Synchronization signal generation circuit P1o Frame memory P1p Read address generation circuit P1q Data processing Circuit P1q1 OR circuit P1q2 Selection circuit P1q3 Black data output circuit P1q4, P1q8 Image processing circuit P1q5 Line buffer P1q6 Control circuit P1q7 Interpolation processing circuit P1q9 Thailand Ring adjustment circuit P1r screen size generating circuit P1s D / A converter P1t LCD drive control signal generating circuit P1u arithmetic processing circuit P1v interpolation table P1w horizontal driving circuit P1 vertical drive circuit

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H04N 5/74 G09G 5/36 520E F-term (Reference) 5C058 BA23 BA25 BB11 BB17 BB19 EA03 EA26 5C068 HB03 HB04 HB06 LA01 LA09 LA11 MA03 5C080 AA18 BB05 CC02 CC07 DD01 EE21 JJ01 JJ02 JJ06 5C082 AA34 BA12 BD02 BD07 CA32 MM07 MM10

Claims (24)

[Claims] 1. A projector for forming one display image by dividing and projecting one screen into a plurality of divided images, wherein a plurality of divided projection images are projected on a screen so as to partially overlap each other to form one display image. A projector comprising: a plurality of image projection units arranged to form a display image; and an adjustment unit for adjusting the size of each of the divided projection images. 2. The projector according to claim 1, wherein said adjusting means includes means for cutting out a peripheral portion of the original divided image. 3. The projector according to claim 1, wherein said adjusting means includes means for converting the resolution of the original divided image. 4. The projector according to claim 1, wherein said adjusting means includes means for changing a pixel density of the original divided image. 5. An optical scanning projector for forming an image by scanning output light power-modulated in accordance with input pixel data, wherein the means for changing the pixel density includes a scanning speed of the output light. The projector according to claim 4, further comprising means for changing. 6. An optical scanning projector that forms an image by scanning output light that has been power-modulated in accordance with input pixel data, wherein the means for changing the pixel density includes a modulation speed for the output light. The projector according to claim 4, further comprising a changing unit. 7. The projector according to claim 1, wherein the adjustment unit is capable of individually and arbitrarily adjusting the size of each of the divided projection images. 8. The synchronizing means for synchronizing a digital image signal with the number of scanning lines in one vertical period and the synchronizing clock in synchronization with a synchronizing clock generated by a horizontal synchronizing signal and a vertical synchronizing signal for each of the divided projection images. A writing means for writing with a write address generated based on the number of effective pixels within one horizontal period, a frame memory for writing the digital image signal in synchronization with the synchronization clock according to the write address, A screen size generation circuit for generating a horizontal difference output signal and a vertical difference output signal of a difference between the screen size adjusted by the size adjustment signal and the screen size of each of the original divided projection images; and the horizontal difference output signal And the vertical direction difference output signal is written in the horizontal and vertical frame memories by the value of the vertical difference output signal. The read start address of the digital image signal is shifted, and the digital image signal written to the frame memory by the basic clock generated from the horizontal synchronization signal and the vertical synchronization signal, the vertical scanning reference timing signal, and the horizontal scanning reference timing signal is shifted. An arithmetic processing means for reading, and a signal synchronized with the reading of the last pixel data in the horizontal direction of the frame memory by the arithmetic processing means, based on the horizontal scanning reference timing signal, immediately before the reading of the first pixel of the next line is started. The signal synchronized with the reading of the last pixel data of the last line of one screen at the “L” level and the “L” level immediately before the reading of the first pixel of the next screen is started based on the vertical scanning reference timing signal The digital image read from the frame memory The relationship between the input image signal and the actual display image is linearly corrected with respect to the signal, and when one of the horizontal scanning reference timing signal and the vertical scanning reference timing signal is at “H” level, a black image is generated. Data processing means for obtaining correction processing output image data so as to output data; driving the image projection means by the basic clock, the horizontal scanning reference timing signal, and the vertical scanning reference timing signal, and 2. A projector according to claim 1, further comprising: a driving unit for an image projection unit that supplies the correction processing output image data output from the image projection unit to the image projection unit. 9. A synchronizing signal extracting circuit for generating the synchronizing clock based on the horizontal synchronizing signal and the vertical synchronizing signal for each of the divided projection images, and the divisional projection in synchronization with the synchronizing clock signal. An analog / digital converter for converting an analog image signal of an image into a digital image signal; detecting the number of scanning lines from a horizontal synchronization pulse within one vertical period for writing the digital image signal into the frame memory; 9. The projector according to claim 8, further comprising: a write address generation circuit that detects a number of effective pixels within one horizontal period from a clock and generates a write address. 10. The arithmetic processing means includes: a synchronization signal generating circuit for generating a basic clock, a horizontal scanning reference timing signal, and a vertical scanning reference timing signal from the horizontal synchronization signal and the vertical synchronization signal; A read address of the digital image signal is generated from the frame memory in synchronization with the basic clock based on the signal and the vertical scanning reference timing signal. 9. The projector according to claim 8, further comprising: a read address generation circuit for shifting a read start address of the digital image signal in a vertical direction. 11. The arithmetic processing means generates the basic clock, the horizontal scanning reference timing signal and the vertical scanning reference timing signal from the horizontal synchronization signal and the vertical synchronization signal, and generates the horizontal difference signal and Interpolation generated after converting the display pixels in the image projection means into the coordinates of the image after the size adjustment by associating the number of pixels whose size has been adjusted based on the vertical difference signal with the original number of display pixels in the image projection means. An arithmetic processing circuit for generating processing table data, a write control signal, and a write address; and synchronizing with the basic clock based on the horizontal scanning reference timing signal and the vertical scanning reference timing signal output from the arithmetic processing circuit. Read out digital image signals from the above frame memory to generate address signals A read address generation circuit for shifting a read start address of the digital image signal written in the frame memory in the horizontal and vertical directions by the value of the horizontal difference signal and the vertical difference signal; 9. The projector according to claim 8, further comprising: an interpolation table for writing the interpolation processing table data according to the writing control signal. 12. The arithmetic processing means according to claim 1, wherein a period is reduced to reduce a horizontal screen size based on the horizontal synchronization signal, the vertical synchronization signal, the horizontal difference signal, and the vertical difference signal. An arithmetic processing circuit for generating a basic clock for reading a digital image signal from a frame memory, a horizontal scanning reference timing signal, and a vertical scanning reference timing signal having a shorter period for shortening the vertical screen size; Based on the basic clock output from the arithmetic processing circuit, the horizontal scanning reference timing signal, and the vertical scanning reference timing signal, a digital image is output from the frame memory in synchronization with the basic clock output from the arithmetic processing circuit from the frame memory. Read address to output read address signal to read signal The projector according to claim 8, comprising: a generating circuit. 13. The arithmetic processing means according to claim 6, wherein said basic clock, said horizontal scanning reference timing signal, and said vertical scanning reference timing signal are output voltage in accordance with the output of said horizontal difference output signal and said vertical difference signal, respectively. The projector according to any one of claims 10 to 12, wherein the voltage is obtained by controlling a voltage-controlled oscillator by an output of a digital / analog converter in which the voltage varies. 14. An OR circuit for outputting a selection signal by taking a logical sum of a signal synchronized with reading of the frame memory and a signal synchronized with reading of last pixel data of the last line of one screen. And selecting and outputting the digital image signal output from the frame memory when the selection signal is at "L" level, and outputting black data from the black data output circuit when the selection signal is at "H" level. A selection circuit for selecting and outputting, and an image processing circuit for performing a linearization correction process on a relationship between the digital image signal output from the selection circuit and an actual image and outputting the result. 8. The projector according to 8. 15. The data processing means reads out the interpolation processing table data written in the interpolation table, and sets the corresponding display pixel to the gradation level of two pixels closest to the display pixel among the four adjacent pixels. Find the difference,
A display pixel value is calculated by a process according to the difference between the gradation levels, and a data processing circuit is configured to perform a linearization correction process on a relationship between the calculated display pixel value and an actual display pixel. The projector according to claim 8, wherein 16. The data processing means comprises: a line buffer for accumulating three lines of digital image signals read from the frame memory; and a display corresponding to an image of two lines accumulated before the line buffer. A control circuit for reading pixel data from the interpolation table and reading four corresponding pixels from the coordinate data in the data from the line buffer; and inputting the image data read from the line buffer and performing a linear interpolation method. An interpolation processing circuit for setting an interpolated display pixel value, and an image for linearizing and correcting the relationship between the interpolated display pixel value data and an actual display image to output correction processing output image data A processing circuit for reading the corrected output image data based on the read address of the interpolation table; The projector according to claim 8, comprising a timing adjustment circuit for grayed adjustment,. 17. The data processing means inputs a digital image signal output from the frame memory read out in synchronization with a basic clock output from the arithmetic processing circuit, and receives the input image signal and an actual display. 9. The projector according to claim 8, wherein the projector is an image processing circuit for linearizing a relationship with an image. 18. A digital / analog converter for converting image data output from the data processing circuit into an analog signal and supplying the analog signal to the image projecting means, wherein the driving means for the image projecting means comprises: A liquid crystal drive control signal generation circuit that outputs a control signal for controlling the drive of the image projection means based on the basic clock, the horizontal scan reference timing signal, and the vertical scan reference timing signal output from the processing means. 9. The projector according to claim 8, wherein: 19. The image projection means driving means according to claim 1, wherein said image projection means includes a rotation speed detection signal of an illumination optical system of said image projection means, a basic clock output from said arithmetic processing circuit, and said horizontal scanning reference timing signal. A horizontal drive circuit for horizontally driving the illumination optical system of the means, and a vertical drive circuit for vertically driving the illumination optical system of the image projection means based on a vertical scanning reference timing signal output from the arithmetic processing means. The projector according to claim 8, wherein: 20. The image projection means according to claim 1, wherein said image projection means comprises three of red, green, and blue.
A light source that continuously generates light of primary colors at a constant power, an optical modulator that modulates the light of the three primary colors with an analog image signal, and a light that is modulated by the light modulator to form one light Means for synthesizing light, a polygon motor driven by an output of a horizontal drive circuit in the adjustment means, a galvano motor driven by an output of a vertical drive circuit in the adjustment means, and the synthesis by being rotated by the polygon motor A polygon mirror that reflects in the horizontal direction when the reflected light is incident, and a vertical mirror driven by the galvano motor and reciprocates in the vertical direction. A galvanomirror for forming a display image on the screen by guiding the light to the screen by performing reflection scanning on the screen. The placement of the projector. 21. A projector for forming one display image by dividing and projecting one screen by a plurality of image projecting means, wherein each of the divided projected images from the plurality of image projecting means partially overlaps on a screen. A first step of arranging the plurality of image projecting means for projecting so as to overlap each other, and projecting only an image from any one of the image projecting means on each pixel of the divided image of the overlapping portion on the screen A second step of adjusting the size of each of the divided projection images by an adjustment unit so as to perform the above operation. 22. The image forming method according to claim 21, wherein the size of each of the divided projection images is adjusted by cutting off a peripheral portion of the original divided image. 23. The image forming method according to claim 21, wherein the size of each of the divided projection images is adjusted by converting the resolution of the original divided image. 24. The image forming method according to claim 21, wherein the size of each of the divided projection images is adjusted by changing the pixel density of the original divided image.