JP2002270858A - Semiconductor device and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the capacity deviation among a plurality of diode elements formed on one semiconductor wafer. SOLUTION: After an n-type semiconductor region 8A is formed by introducing an n-type impurity ion, an n-type semiconductor region 8B is formed by introducing an n-type impurity ion at a region that is adjacent to the n-type semiconductor region 8A. Then, an n-type semiconductor region 8C is formed by introducing an n-type impurity ion into a region that is adjacent to the n-type semiconductor region 8B. In this case, the concentration of impurities in the n-type semiconductor region 8B becomes lower than that of impurities in the n-type semiconductor region 8A, and the concentration of impurities in the n-type semiconductor region 8C becomes smaller than that of impurities in the n-type semiconductor region 8B.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device manufacturing technique and a semiconductor device, and more particularly to a technique effective when applied to the manufacture of a semiconductor device having a diode element.

[0002]

2. Description of the Related Art In recent years, mobile communication devices such as digital cellular phones and high-speed data communication devices have become smaller and smaller.
There is a demand for a thinner and lighter weight. for that reason,
High-frequency modules such as an antenna switch module and a voltage-controlled oscillator module, which constitute key components of the above-described mobile communication device and high-speed data communication device, are being reduced in size, thickness, and weight.

In response to the miniaturization of the high-frequency module described above, the miniaturization of diodes used in the high-frequency module is also required. 2. Description of the Related Art Conventionally, as a package of a diode, for example, a lead frame in which an anode side and a cathode side are paired is prepared, and the back surface of a semiconductor chip on which a diode element (pn junction) having a vertical (planar or mesa) structure is formed. The electrodes are bonded to the inner (tab) of the lead frame on the anode or cathode side, and the surface electrode of the semiconductor chip and the inner (post) of the other lead frame are bonded by wire bonding using a wire such as Au (gold). After connection, the semiconductor chip, wires, and lead frame were resin-sealed with an epoxy resin material to form a resin package.

The structure of the above-mentioned resin-sealed diode is described in, for example, May 20, 1984, published by Dempa Shimbun, edited by the Japan Electronic Machinery Manufacturers Association, "Comprehensive Electronic Parts Handbook", p. 179. is there.

[0005]

However, the present inventors have found that the above-mentioned resin-sealed type diode has the following problems.

That is, when the surface electrode of the semiconductor chip on which the diode element is formed and the post side of the lead frame are connected by wire bonding, a wire loop shape is formed in which the wire bulges upward. Furthermore, since the semiconductor chip, wires, and lead frame are sealed with resin, the wire loop-shaped wire and the resin material used for resin sealing prevent the package size of the diode from being reduced in the height direction. There is a problem.

Here, for the purpose of reducing the package size of the diode in the height direction, the present inventors formed both anode and cathode electrodes on the same surface of a semiconductor chip, and formed the anode and cathode electrodes on the same surface. A diode used by connecting both electrodes directly to the mounting substrate by face-down bonding was studied.
However, the present inventors have found that such a diode has the following problems.

That is, in a semiconductor chip, pn
The junction is formed in the vertical direction with respect to the element formation surface of the semiconductor substrate. Therefore, in a diode used by directly connecting to a mounting substrate by face-down bonding, a conductive layer extending from the diode element to the surface of the semiconductor chip must be separately formed in order to bring out diode characteristics to the outside of the semiconductor chip. There is a problem that must not be.

In forming a vertical diode device on an n-type silicon substrate, a plurality of diode devices are formed on an epitaxial layer grown on a semiconductor wafer (silicon substrate). At this time, since the capacitance characteristics of the individual diode elements are affected by the structure of the epitaxial crystal constituting the epitaxial layer, there is a problem that the capacitance characteristics of the individual diode elements, particularly, the capacitance characteristics in a high bias region are varied. is there. Therefore, for example, a voltage control type transmitter (VoltageControlle
When manufacturing a varicap diode used for a d Oscillator (VCO), a narrow capacitance deviation of about 3% or less between each diode may be required. May not be able to answer.

Further, the n-type semiconductor region which is to be a part of the diode element is formed by diffusing an n-type impurity by heat treatment. This heat treatment also causes a capacitance deviation (variation in capacitance characteristics) between the plurality of diode elements formed on the semiconductor wafer.

An object of the present invention is to provide a technique capable of reducing a capacitance deviation between a plurality of diode elements formed on one semiconductor wafer.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0013]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

That is, the present invention provides a step of forming a second semiconductor layer of a first conductivity type by introducing an impurity of a first conductivity type into a first region of a main surface of a semiconductor substrate; By introducing an impurity of the first conductivity type into the second region adjacent to or partially overlapping with the second region, the first semiconductor layer is adjacent to or partially overlaps with the second semiconductor layer, and has a lower impurity concentration than the second semiconductor layer. Forming a conductive type third semiconductor layer, wherein the concentration of the first conductive type impurity in the third semiconductor layer decreases in a direction from the first region to the third region. is there.

Further, according to the present invention, there is provided a step of forming a first semiconductor layer of a first conductivity type on a semiconductor substrate of a first conductivity type, and a step of forming an impurity of the first conductivity type in a first region of the first semiconductor layer. Forming a second semiconductor layer of the first conductivity type by introducing the first conductivity type, and introducing an impurity of the first conductivity type into the second region of the first semiconductor layer to be adjacent to or adjacent to the second semiconductor layer. Forming a third semiconductor layer of a first conductivity type, part of which overlaps and has a lower impurity concentration than in the second semiconductor layer;
Forming a first conductivity type fourth semiconductor layer electrically connected to the third semiconductor layer by introducing a first conductivity type impurity into a third region of the first semiconductor layer; A fifth semiconductor layer of a second conductivity type is adjacent to the second semiconductor layer in a fourth region of the first semiconductor layer adjacent to the first region and separated from the second region and the third region. Forming the semiconductor layer and the fourth semiconductor layer apart from each other, wherein the concentration of the impurity of the first conductivity type in the third semiconductor layer is from the first region toward the third region. The concentration of the first conductivity type impurity in the fourth semiconductor layer is equal to or less than the concentration of the first conductivity type impurity in the second semiconductor layer and the first conductivity type impurity in the third semiconductor layer. The concentration of the impurity of the conductivity type is higher than the concentration of the highest region. That.

The present invention also provides (a) a semiconductor substrate having a second semiconductor layer of a first conductivity type in a first region on a main surface of the semiconductor substrate;
A first conductive type third semiconductor layer having a lower impurity concentration than the second semiconductor layer is provided in a second region adjacent to or partially overlapping the first region in a direction along a main surface of the semiconductor substrate. And the concentration of the impurity of the first conductivity type in the third semiconductor layer decreases from the first region toward the third region.

[0017]

Embodiments of the present invention will be described below in detail with reference to the drawings. In all the drawings for describing the embodiments, members having the same functions are denoted by the same reference numerals, and the repeated description thereof will be omitted.

(Embodiment 1) FIGS. 1 to 1 show a method of manufacturing a varicap diode which is a semiconductor device according to Embodiment 1.
This will be described with reference to FIG.

First, as shown in FIG. 1, a semiconductor substrate 1 having an n-type conductivity (first conductivity type) is doped with boron which is a p-type (second conductivity type) impurity. By performing annealing, B (boron) is diffused to form a p-type diffusion layer 2P. Next, the semiconductor substrate 1
An n-type impurity ion (for example, P (phosphorus) or As
After implanting (arsenic)), the semiconductor substrate 1 is annealed to diffuse impurity ions, thereby forming an n-type base diffusion layer 2N (first semiconductor layer).

Subsequently, after an insulating film 3 is formed by oxidizing the surface of the semiconductor substrate 1, a region where an n-type semiconductor region to be described later is formed (first region) is formed using a photoresist film.
The opening 4 is formed by etching the insulating film 3 on the (region). After that, a thin oxide film 5 is formed on the surface of the n-type base diffusion layer 2N at the bottom of the opening 4. By forming this oxide film 5, it is possible to reduce damage to the semiconductor substrate 1 and adjust the depth at which impurity ions are implanted in the next step of implanting impurity ions.

Next, as shown in FIGS. 2 and 3, a photoresist film 6A is formed on the surfaces of the insulating film 3 and the oxide film 5 by photolithography. FIG. 3 is a sectional view taken along line AA in FIG. Subsequently, the n-type semiconductor region 8A (second semiconductor layer) is formed by implanting n-type impurity ions (for example, P or As) into the semiconductor substrate 1 through the opening 7A selectively formed in the photoresist film 6A. Form.

At this time, the actual implantation depth of the n-type impurity ions has a normal distribution in which a predetermined implantation depth μ is an average value and σ is a standard deviation. When this is converted into a standard normal distribution, the above implantation depth is from μ-3σ to μ
The probability of falling between + 3σ is about 99.73%. That is, by setting the implantation depth μ such that the position of μ−3σ is deeper than the surface of the n-type base diffusion layer 2N, it becomes possible to implant impurity ions of a desired concentration. Further, by setting the implantation depth μ as described above, in the varicap diode according to the first embodiment, adverse effects such as surface breakdown in the n-type semiconductor region 8A can be prevented.

Next, after removing the photoresist film 6A, as shown in FIGS. 4 and 5, in the same step as the step of forming the n-type semiconductor region 8A, the n-type semiconductor region 8A is adjacently formed. N-type semiconductor region 8B in the region (second region)
(Third semiconductor layer) is formed. At this time, the concentration of the implanted n-type impurity ions is lower than the concentration of the impurity ions implanted when forming the n-type semiconductor region 8A. The n-type semiconductor region 8A and the n-type semiconductor region 8B are formed so as to be in contact with each other.

Subsequently, after removing the photoresist film used to form the n-type semiconductor region 8B, the n-type semiconductor region 8A was formed using the photoresist film 6B in which the opening 7B was selectively opened. In a step similar to the above step, an n-type semiconductor region 8C (third semiconductor layer) is formed in a region (second region) adjacent to the n-type semiconductor region 8B. At this time, the concentration of the implanted n-type impurity ions is lower than the concentration of the impurity ions implanted when forming the n-type semiconductor region 8B. The n-type semiconductor region 8B and the n-type semiconductor region 8C are formed so as to be in contact with each other.

As described above, in the first embodiment, the impurity concentration in n-type semiconductor region 8B is lower than in n-type semiconductor region 8A, and the impurity concentration in n-type semiconductor region 8C is lower than in n-type semiconductor region 8B. Since the concentration becomes lower, a concentration gradient of the n-type impurity is formed from the n-type semiconductor region 8A to the n-type semiconductor region 8C. Thereby, a concentration gradient of the n-type impurity can be formed without using heat treatment. When an n-type impurity is diffused by heat treatment to form a concentration gradient of the n-type impurity, a plurality of diode elements formed on the semiconductor substrate 1 (semiconductor wafer) due to the variation in the diffusion of the n-type impurity are formed. However, according to the method of manufacturing the semiconductor device of the first embodiment, such variation can be prevented. That is,
By using the method for manufacturing a semiconductor device according to the first embodiment, it becomes possible to manufacture a varicap diode that meets a narrow capacitance deviation requirement.

The n-type semiconductor region 8A and the n-type semiconductor region 8B are formed so as to be in contact with each other.
And n-type semiconductor region 8C are formed so as to be in contact with each other, but they may be formed so as to partially overlap each other.
Thereby, the concentration gradient of the n-type impurity in the n-type semiconductor regions 8A to 8C can be made close to linear. That is, it is possible to easily form an impurity profile that matches the capacitance characteristics required for the varicap diode of the first embodiment. Also, in the first embodiment, n
Although the case where the concentration gradient of the n-type impurity is formed by forming the n-type semiconductor regions 8A to 8C has been described as an example, the n-type semiconductor region is not limited to the three regions 8A to 8C, but may be applied to more regions. The concentration gradient may be formed by dividing. Thereby, the concentration gradient of the n-type impurity in the n-type semiconductor region can be made more linear.

Here, the junction between the p-type semiconductor region and the n-type semiconductor region formed in a later step depends on the vertical dimension t of the opening 4 in FIG. 2 and the implantation depth of the n-type impurity ions. The capacity is determined. That is, its p
Since the junction capacitance is proportional to the junction area between the n-type semiconductor region and the n-type semiconductor region, the capacitance value of the varicap diode according to the first embodiment is determined by the dimension t and the implantation depth of the n-type impurity ions. Thereby, it is possible to adjust to a desired value.

In the first embodiment, no epitaxial layer is formed on the semiconductor substrate 1. for that reason,
Variations in the capacitance characteristics of the individual diode elements due to the structure of the epitaxial crystal constituting the epitaxial layer, particularly in the high bias region, can be prevented. Further, in the case of using a semiconductor substrate on which an epitaxial layer is formed, since the epitaxial layer occupies about 80% of the material cost, the method for manufacturing a semiconductor device according to the first embodiment is used. Costs can be reduced to about 20%.

A p-type diffusion layer 2P is formed below the n-type base diffusion layer 2N in which the n-type semiconductor regions 8A to 8C are formed. Therefore, the n-type base diffusion layer 2N, p
Since the p-type diffusion layer 2P and the n-type semiconductor substrate 1 form a transistor structure, and the p-type diffusion layer 2P serves as a channel stopper layer, the depletion layer is more p-type than the n-type semiconductor regions 8A to 8C. Spreading in the direction toward the diffusion layer 2P can be prevented.

Next, after removing the photoresist film 6B, as shown in FIGS. 6 and 7, the surfaces of the insulating film 3 and the oxide film 5 are formed in the same step as the step of forming the n-type semiconductor region 8A. Next, a photoresist film 6C is formed. Subsequently, an n-type impurity ion (for example, P or As) is implanted into the semiconductor substrate 1 through an opening 7C selectively formed in the photoresist film 6C, thereby forming a region adjacent to the n-type semiconductor region 8C (third region) Region) in the n-type semiconductor region 8D
(Fourth semiconductor layer) is formed. At this time, the concentration of the implanted n-type impurity ions is the same as the concentration of the impurity ions implanted when forming the n-type semiconductor region 8A.
Alternatively, the concentration may be close to the concentration of the impurity ions implanted when forming the n-type semiconductor region 8A, and may be higher than the concentration of the impurity ions implanted when forming the n-type semiconductor region 8B.

Next, after removing the photoresist film 6C, as shown in FIGS. 8 and 9, an insulating film 9 is formed on the surfaces of the n-type semiconductor regions 8A to 8D by a thermal oxidation method. By forming this insulating film 9, the n-type semiconductor region 8A
~ 8D surface can be protected. Note that FIG. 8 also shows n-type semiconductor regions 8A to 8D (hatched regions) below the insulating film 9 for explanation.

Subsequently, the opening 11 is formed by etching the insulating film 3 on a region where a p-type semiconductor region described later is to be formed using a photoresist film. Thereafter, a thin oxide film 12 is formed on the surface of the n-type base diffusion layer 2N at the bottom of the opening 11. By forming the oxide film 12, it is possible to reduce damage to the semiconductor substrate 1 and adjust the depth at which impurity ions are implanted in the next step of implanting impurity ions.

Next, a photoresist film 10 is formed on the surfaces of the insulating films 3 and 9 by a photolithography technique. Subsequently, p-type impurity ions (for example, B) are implanted into the semiconductor substrate 1 through the opening 11 selectively formed in the photoresist film 10, and are adjacent to the n-type semiconductor region 8A and are adjacent to the n-type semiconductor regions 8B to 8D. Area (4th
After the p-type semiconductor region 13 (fifth semiconductor layer) is formed in the (region), the p-type semiconductor region 13 is activated by performing a heat treatment on the semiconductor substrate 1.

10 to 12 show steps subsequent to the above steps. FIG. 10 is a plan view of a main part, FIG. 11 is a sectional view of the main part, and FIG. 12 is a perspective view of the main part.

After removing the photoresist film 10,
As shown in FIGS. 10 to 12, the oxide film 12 used for forming the p-type semiconductor region 13 is removed. Subsequently, by removing the insulating film 9 on the n-type semiconductor region 8D, the opening 14 is removed.
Is formed, an anode electrode 15 and a cathode electrode 16 are formed in the opening 11 and the opening 14, respectively. Aluminum can be exemplified as a material of the anode electrode 15 and the cathode electrode 16.

Thereafter, a bump electrode electrically connected to the anode electrode 15 and the cathode electrode 16 is formed on the anode electrode 15 and the cathode electrode 16. The material of the bump electrode can be selected according to the material of the electrode formed at the position where the varicap diode of the first embodiment is mounted. For example, the electrode at the mounting position is made of Au (gold). In this case, Au can be selected, and when the electrode at the mounting location is solder, solder can be selected.

Subsequently, the varicap diode of the first embodiment is manufactured by separating the semiconductor substrate 1 into individual semiconductor chips by dicing. The semiconductor chip 17 having the varicap diode of the first embodiment manufactured as described above is subjected to face-down bonding by connecting the bump electrode 18 to a predetermined position on the mounting board 19, as shown in FIG. It can be used by mounting. In addition, diode elements (n-type semiconductor regions 8A to 8D and p-type semiconductor region 1
Since (3) is formed in the lateral direction with respect to the element formation surface of the semiconductor substrate 1, it is possible to omit to separately form a conductive layer for extracting diode characteristics to the outside of the semiconductor chip.

Incidentally, the varicap diode according to the first embodiment can be used as a resin-sealed package. As shown in FIG. 14, by connecting bump electrodes 18 electrically connected to the anode electrode 15 and the cathode electrode 16 to the leads 20A and 20B, the semiconductor chip on which the varicap diode of the first embodiment is formed is formed. 17 can be electrically connected to the leads 20A and 20B. Thereafter, the semiconductor chip 17 and the lead 2 are made of, for example, an epoxy resin material 21.
A resin package can be obtained by sealing 0A and 20B with resin.

(Embodiment 2) In a semiconductor device of Embodiment 2, the n-type semiconductor regions 8A to 8D of the varicap diode of Embodiment 1 are formed by changing the cross-sectional shape from the anode electrode 15 to the cathode electrode 16. It is formed so as to become smaller. Other members and structures are the same as those of the varicap diode of the first embodiment.

Hereinafter, a method of manufacturing the varicap diode according to the second embodiment will be described with reference to FIGS.

The method of manufacturing the varicap diode according to the second embodiment is the same as that of the first embodiment up to the step of forming the opening 4 described with reference to FIG.

Thereafter, as shown in FIG. 15, an oxide film 5A is formed on the surface of the n-type base diffusion layer 2N at the bottom of the opening 4. Subsequently, the oxide film 5A on the regions where the n-type semiconductor regions 8A and 8D (see FIG. 7) are to be formed is thinned by using a photoresist film (not shown).

Next, after the photoresist film is removed, as shown in FIG. 16, a region where an n-type semiconductor region 8B (see FIG. 7) is formed using a new photoresist film (not shown). The upper oxide film 5A is etched and thinned. At this time, the thickness of the oxide film 5A on the region where the n-type semiconductor region 8B is formed is larger than the thickness of the oxide film 5A on the region where the n-type semiconductor regions 8A and 8D are formed. I do.

Subsequently, after removing the photoresist film, the oxide film 5A on the region where the n-type semiconductor region 8C (see FIG. 7) is to be formed using a new photoresist film (not shown). Etch and thin. At this time, the thickness of oxide film 5A on the region where n-type semiconductor region 8C is formed is the same as that of oxide film 5A on the region where n-type semiconductor region 8B is formed.
A is to be thicker than the film thickness of A.

Next, as shown in FIG. 17, a photoresist film 6 is formed on the surface of the insulating film 3 by photolithography.
Form D. Subsequently, n-type impurity ions (for example, P or As) are implanted into opening 4 using photoresist film 6D as a mask, to form n-type semiconductor regions 8A to 8D. At this time, the concentration and depth at which the impurity ions are implanted are determined by the thickness of the oxide film 5A on the opening 4. That is, in the second embodiment, n
The cross-sectional shape of the type semiconductor regions 8A to 8C can be reduced from the n-type semiconductor region 8A to the n-type semiconductor region 8C. Thereby, the concentration gradient of the n-type impurities in n-type semiconductor regions 8A to 8C can be made more linear than in the first embodiment. Note that the concentration and depth of the implanted impurity ions in the n-type semiconductor region 8D are the same as those in the n-type semiconductor region 8A.

In the second embodiment, the case where the concentration gradient of the n-type impurity is formed by forming the n-type semiconductor regions 8A to 8C has been exemplified. The type semiconductor region is not limited to the three regions 8A to 8C, but may be divided into more regions to form a concentration gradient. Thereby, the concentration gradient of the n-type impurity in the n-type semiconductor region can be made more linear.

In the second embodiment, the case where the concentration and depth at which impurity ions are implanted are determined by the thickness of oxide film 5A on opening 4 has been described. The implantation depth may be determined by changing.

Next, after removing the photoresist film 6D, the varicap diode of the second embodiment is manufactured by the same steps as those described in the first embodiment with reference to FIGS. I do.

(Embodiment 3) A semiconductor device according to Embodiment 3 has a pn structure including a p-type semiconductor region and an n-type semiconductor region.
In a varicap diode in which a junction is formed in a vertical direction with respect to an element formation surface of a semiconductor substrate, a concentration gradient of an n-type impurity is formed in an n-type semiconductor region.

FIG. 18 is a sectional view showing a varicap diode according to the third embodiment.

An n-type epitaxial layer 2N2 is formed on the main surface (element formation surface) of semiconductor substrate 1 having n-type conductivity.

In n-type epitaxial layer 2N2, n-type semiconductor region 8 is formed by introducing n-type impurity ions (for example, P or As). Above the n-type semiconductor region 8, p-type impurity ions (eg, B)
, A p-type semiconductor region 13 is formed. The p-type semiconductor region 13 and the n-type semiconductor region 8 form a diode element (pn junction).

An opening reaching the p-type semiconductor region 13 is formed in the insulating film 3 formed by oxidizing the surface of the semiconductor substrate 1. Also, p
An anode electrode 15 made of aluminum and connected to the mold semiconductor region 13 is formed. On the back surface of the semiconductor substrate 1, a cathode electrode 16A (back surface electrode) electrically connected to the n-type semiconductor region 8 is formed. Cathode electrode 1
6A is, for example, Au deposited by a sputtering method.
It can be formed from a (gold) film.

FIG. 19 is a cross-sectional view showing a main portion of the n-type semiconductor region 8 in an enlarged manner. In the n-type semiconductor region 8, n-type semiconductor regions 8A to 8D are sequentially formed from the upper part to the lower part. These n-type semiconductor regions 8A to 8A
D is an impurity ion having n-type conductivity (for example, P
Or by changing the driving strength and concentration of As)
It can be formed by introducing the impurity ions. Further, n-type semiconductor regions 8A to 8D have the same n-type impurity concentration as n-type semiconductor regions 8A to 8D in the first embodiment (see FIG. 7).

As described above, in the third embodiment, the n-type semiconductor region 8 is formed in the same manner as in the first embodiment.
Since the impurity concentration in the n-type semiconductor region 8B becomes lower than that in A and the impurity concentration in the n-type semiconductor region 8C becomes lower than that in the n-type semiconductor region 8B, the n-type semiconductor region 8A moves toward the n-type semiconductor region 8C. Thus, a concentration gradient of the n-type impurity is formed. Thus, a concentration gradient of the n-type impurity can be formed without using heat treatment, so that it is possible to prevent a variation in capacitance characteristics between a plurality of diode elements formed on the semiconductor substrate 1. That is, even when the method of manufacturing a semiconductor device according to the third embodiment is used, it is possible to manufacture a varicap diode that meets a narrow capacitance deviation requirement.

Further, in the third embodiment, the case where the concentration gradient of the n-type impurity is formed by forming the n-type semiconductor regions 8A to 8C has been described, but the same as in the first embodiment. And the n-type semiconductor region is not limited to the three regions 8A to 8C, but may be divided into more regions to form the concentration gradient. Thereby, the concentration gradient of the n-type impurity in the n-type semiconductor region can be made closer to linear.

(Embodiment 4) In the semiconductor device of Embodiment 4, the n-type semiconductor regions 8A to 8D in the varicap diode of Embodiment 3 are cut from the n-type semiconductor regions 8A to 8n by n-type. It is formed so as to become smaller toward the mold semiconductor region 8D. Other members and structures are the same as those of the varicap diode according to the third embodiment.

FIG. 20 is a cross-sectional view showing a varicap diode according to the third embodiment. FIG. 21 is a cross-sectional view showing a main portion of the n-type semiconductor region 8 shown in FIG. As in the case of the third embodiment, the n-type semiconductor region 8 includes n-type semiconductor regions 8A to 8A to
8D are formed in order.

FIG. 22 is a plan view of a main part showing a method of forming the n-type semiconductor regions 8A to 8D, and FIG. 23 is a cross-sectional view of the main part along line BB in FIG.

In forming the n-type semiconductor regions 8A to 8D, first, an opening 4A is formed in the insulating film 3 on the region where the n-type semiconductor regions 8A to 8D are formed. Subsequently, n-type impurity ions (for example, P or As) are implanted into the opening 4A using the photoresist film as a mask,
An n-type semiconductor region 8D is formed.

Next, after an oxide film 5B is formed on the surface of the n-type epitaxial layer 2N2 at the bottom of the opening 4A, an n-type semiconductor region 8C is formed using a photoresist film (see FIG. 21).
The oxide film 5B on the region where is formed is etched and thinned.

Next, after removing the photoresist film, the n-type semiconductor region 8 is formed using a new photoresist film.
The oxide film 5B on the region where B (see FIG. 21) is formed is etched and thinned. At this time, the thickness of the oxide film 5B on the region where the n-type semiconductor region 8B is formed is made larger than the thickness of the oxide film 5B on the region where the n-type semiconductor region 8C is formed.

Subsequently, after the photoresist film is removed, the oxide film 5 on the region where the n-type semiconductor region 8A (see FIG. 21) is to be formed using a new photoresist film.
B is thinned by etching. At this time, the n-type semiconductor region 8
The thickness of oxide film 5B on the region where A is formed is made larger than the thickness of oxide film 5B on the region where n-type semiconductor region 8B is formed.

Next, a photoresist film is formed on the surface of the insulating film 3 by a photolithography technique. Subsequently, n-type impurity ions (for example, P or As) are implanted into the opening 4A using the photoresist film as a mask, and n
The type semiconductor regions 8A to 8C can be formed. At this time, the concentration and depth at which the impurity ions are implanted are determined by the thickness of oxide film 5B over opening 4A. That is, in the fourth embodiment, the cross-sectional shape of n-type semiconductor regions 8A to 8C can be reduced from n-type semiconductor region 8A to n-type semiconductor region 8C. Thereby, n in the n-type semiconductor regions 8A to 8C
The concentration gradient of the type impurity can be made more linear than in the case of the third embodiment. The n-type semiconductor region 8D
The concentration of the impurity ions in the inside is set to be the same as the concentration of the impurity ions in the n-type semiconductor region 8A. Alternatively, the concentration may be close to the concentration of the impurity ions in the n-type semiconductor region 8A, and may be higher than the concentration of the impurity ions in the n-type semiconductor region 8B.

In the fourth embodiment, the case where the concentration gradient of the n-type impurity is formed by forming the n-type semiconductor regions 8A to 8C has been exemplified. However, similar to the case of the first embodiment, And the n-type semiconductor region is not limited to the three regions 8A to 8C, but may be divided into more regions to form the concentration gradient. Thereby, the concentration gradient of the n-type impurity in the n-type semiconductor region can be made more linear.

Although the invention made by the inventor has been specifically described based on the embodiments of the present invention, the present invention is not limited to the above-described embodiments, and various modifications may be made without departing from the spirit of the invention. Needless to say, it can be changed.

[0067]

The effects obtained by typical ones of the inventions disclosed by the present application will be briefly described as follows. (1) Since a concentration gradient of an n-type impurity in an n-type semiconductor region can be formed without using heat treatment, variation in capacitance characteristics among a plurality of diode elements formed on a semiconductor substrate (semiconductor wafer) is reduced. Can be prevented.

[Brief description of the drawings]

FIG. 1 is a fragmentary cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention;

FIG. 2 is a fragmentary plan view showing the method for manufacturing the semiconductor device according to one embodiment of the present invention;

3 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 1;

FIG. 4 is an essential part plan view of the semiconductor device during a manufacturing step following that of FIG. 2;

5 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 3;

6 is a fragmentary plan view of the semiconductor device during a manufacturing step following that of FIG. 4;

7 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 5;

8 is a fragmentary plan view of the semiconductor device during a manufacturing step following that of FIG. 6;

9 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 7;

10 is a fragmentary plan view of the semiconductor device during a manufacturing step following that of FIG. 8;

11 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 9;

FIG. 12 is an essential part perspective view showing the method for manufacturing the semiconductor device according to one embodiment of the present invention;

FIG. 13 is a cross-sectional view showing a state in which the semiconductor device according to one embodiment of the present invention is mounted on a mounting substrate.

FIG. 14 is a cross-sectional view of a case where a semiconductor device according to an embodiment of the present invention is used with resin sealing.

FIG. 15 is a fragmentary cross-sectional view showing the method for manufacturing the semiconductor device according to another embodiment of the present invention;

16 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 15;

17 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 16;

FIG. 18 is a fragmentary cross-sectional view showing a semiconductor device according to another embodiment of the present invention.

FIG. 19 is an essential part cross-sectional view showing an enlarged n-type semiconductor region included in the semiconductor device shown in FIG. 18;

FIG. 20 is a fragmentary cross-sectional view showing a semiconductor device according to another embodiment of the present invention;

21 is an enlarged cross-sectional view of a main part of an n-type semiconductor region included in the semiconductor device shown in FIG. 20;

FIG. 22 is an essential part plan view showing the method for forming the n-type semiconductor region included in the semiconductor device shown in FIG. 20;

23 is a fragmentary cross-sectional view showing the method for forming the n-type semiconductor region included in the semiconductor device shown in FIG. 20;

[Explanation of symbols]

 Reference Signs List 1 semiconductor substrate 2N n-type base diffusion layer (first semiconductor layer) 2P p-type diffusion layer 2N2 epitaxial layer 3 insulating film 4 opening 4A opening 5 oxide film 5A oxide film 5B oxide film 6A to 6D photoresist film 7A to 7C Opening 8 n-type semiconductor region 8A n-type semiconductor region (second semiconductor layer) 8B n-type semiconductor region (third semiconductor layer) 8C n-type semiconductor region (third semiconductor layer) 8D n-type semiconductor region (fourth semiconductor layer) 9) insulating film 10 photoresist film 11 opening 12 oxide film 13 p-type semiconductor region (fifth semiconductor layer) 14 opening 15 anode electrode 16 cathode electrode 17 semiconductor chip 18 bump electrode 19 mounting substrate 20A, 20B lead 21 resin material

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification code FI Theme coat ゛ (Reference)

Claims (5)

[Claims] (A) A first conductive type semiconductor substrate is provided on a first conductive type semiconductor substrate.
Forming a first conductivity type first semiconductor layer by introducing a conductivity type impurity, and (b) introducing the first conductivity type impurity into a first region of the first semiconductor layer.
Forming a second semiconductor layer of the first conductivity type; and (c) introducing an impurity of the first conductivity type into the second region of the first semiconductor layer so as to be adjacent to or part of the second semiconductor layer. Forming a third semiconductor layer of the first conductivity type having a lower impurity concentration than in the second semiconductor layer, and (d) introducing the first conductivity type impurity into the third region of the first semiconductor layer. Thereby, the first semiconductor layer electrically connected to the third semiconductor layer is formed.
Forming a conductive type fourth semiconductor layer; and (e) forming the first semiconductor layer.
By introducing an impurity of the second conductivity type into a fourth region of the first semiconductor layer adjacent to the region and separated from the second region and the third region, a fifth semiconductor layer of the second conductivity type is formed. Forming the third semiconductor layer adjacent to the second semiconductor layer and spaced apart from the third semiconductor layer and the fourth semiconductor layer, wherein the concentration of the first conductivity type impurity in the third semiconductor layer is The concentration of the impurity of the first conductivity type in the fourth semiconductor layer is reduced from the first region toward the third region.
A semiconductor device, wherein the concentration of the impurity of the first conductivity type in the second semiconductor layer is lower than the concentration of the impurity of the first conductivity type and the concentration of the impurity of the first conductivity type in the third semiconductor layer is higher than the concentration of the highest region. Manufacturing method. 2. (a) A first conductive type semiconductor substrate is formed on a first conductive type semiconductor substrate.
Forming a first conductivity type first semiconductor layer by introducing a conductivity type impurity, and (b) introducing the first conductivity type impurity into a first region of the first semiconductor layer.
Forming a second semiconductor layer of the first conductivity type; and (c) introducing an impurity of the first conductivity type into the second region of the first semiconductor layer so as to be adjacent to or part of the second semiconductor layer. Forming a third semiconductor layer of the first conductivity type having a lower impurity concentration than in the second semiconductor layer, and (d) introducing the first conductivity type impurity into the third region of the first semiconductor layer. Thereby, the first semiconductor layer electrically connected to the third semiconductor layer is formed.
Forming a conductive type fourth semiconductor layer; and (e) forming the first semiconductor layer.
By introducing an impurity of the second conductivity type into a fourth region of the first semiconductor layer adjacent to the region and separated from the second region and the third region, a fifth semiconductor layer of the second conductivity type is formed. Forming the second semiconductor layer adjacent to the second semiconductor layer and spaced apart from the third semiconductor layer and the fourth semiconductor layer;
In the step (c), the second region is divided into a plurality of regions from the first region toward the third region, and each of the plurality of regions has a different concentration of the first conductivity type. The third semiconductor layer is formed by introducing an impurity, and the concentration of the impurity of the first conductivity type in the third semiconductor layer is reduced from the first region toward the third region. The concentration of the first conductivity type impurity in the fourth semiconductor layer is equal to or less than the concentration of the first conductivity type impurity in the second semiconductor layer and the concentration of the first conductivity type impurity in the third semiconductor layer. A method for manufacturing a semiconductor device, wherein the concentration is higher than that of a region having the highest concentration. 3. A method according to claim 1, further comprising: (a) forming a first conductive type semiconductor substrate on the first conductive type semiconductor substrate;
Forming a first conductivity type first semiconductor layer by introducing a conductivity type impurity, and (b) introducing the first conductivity type impurity into a first region of the first semiconductor layer.
Forming a second semiconductor layer of the first conductivity type; and (c) introducing an impurity of the first conductivity type into the second region of the first semiconductor layer so as to be adjacent to or part of the second semiconductor layer. Forming a first conductivity type third semiconductor layer having a lower impurity concentration than the second semiconductor layer, and (d) introducing a first conductivity type impurity into the third region of the first semiconductor layer. Thereby, the first semiconductor layer electrically connected to the third semiconductor layer is formed.
Forming a conductive type fourth semiconductor layer; and (e) forming the first semiconductor layer.
By introducing an impurity of the second conductivity type into a fourth region of the first semiconductor layer adjacent to the region and separated from the second region and the third region, a fifth semiconductor layer of the second conductivity type is formed. Forming the second semiconductor layer adjacent to the second semiconductor layer and spaced apart from the third semiconductor layer and the fourth semiconductor layer;
The third semiconductor layer has a cross section that becomes narrower in the direction from the first region to the third region, and the concentration of the first conductivity type impurity in the third semiconductor layer is reduced from the first region to the third region. The concentration of the first conductivity type impurity in the fourth semiconductor layer is less than or equal to the concentration of the first conductivity type impurity in the second semiconductor layer, and the third semiconductor A method for manufacturing a semiconductor device, wherein the concentration of the impurity of the first conductivity type in a layer is higher than the concentration in a region where the concentration is highest. 4. A method according to claim 1, further comprising: (a) forming a first conductive type semiconductor substrate on the first conductive type semiconductor substrate;
Forming a first conductivity type first semiconductor layer by introducing a conductivity type impurity, and (b) introducing the first conductivity type impurity into a first region of the first semiconductor layer.
Forming a second semiconductor layer of the first conductivity type; and (c) introducing an impurity of the first conductivity type into the second region of the first semiconductor layer so as to be adjacent to or part of the second semiconductor layer. Forming a first conductivity type third semiconductor layer having a lower impurity concentration than the second semiconductor layer, and (d) introducing a first conductivity type impurity into the third region of the first semiconductor layer. Thereby, the first semiconductor layer electrically connected to the third semiconductor layer is formed.
Forming a conductive type fourth semiconductor layer; and (e) forming the first semiconductor layer.
By introducing an impurity of the second conductivity type into a fourth region of the first semiconductor layer adjacent to the region and separated from the second region and the third region, a fifth semiconductor layer of the second conductivity type is formed. Forming the second semiconductor layer adjacent to the second semiconductor layer and spaced apart from the third semiconductor layer and the fourth semiconductor layer;
In the step (c), the second region is divided into a plurality of regions from the first region toward the third region, and each of the plurality of regions has a different concentration of the first conductivity type. The third semiconductor layer is formed by introducing an impurity, and a cross section of the third semiconductor layer becomes narrower in a direction from the first region to the third region, and the third semiconductor layer in the third semiconductor layer becomes thinner. The concentration of the one-conductivity-type impurity is reduced from the first region toward the third region.
The concentration of the impurity of the first conductivity type in the semiconductor layer is equal to or less than the concentration of the impurity of the first conductivity type in the second semiconductor layer and the concentration of the impurity of the first conductivity type in the third semiconductor layer. A method for manufacturing a semiconductor device, wherein the concentration is higher than the highest region. 5. A semiconductor device according to claim 1, wherein a first conductive type first conductive type is formed on a main surface of the semiconductor substrate.
A semiconductor layer is formed, a second semiconductor layer of a first conductivity type is formed in a first region of the first semiconductor layer, and the first region is adjacent to or part of a direction along a main surface of the semiconductor substrate. Are formed in the second region where the third semiconductor layer of the first conductivity type having a lower impurity concentration than in the second semiconductor layer is formed, and is adjacent to or adjacent to the second region in the direction along the main surface of the semiconductor substrate. A fourth semiconductor layer of a first conductivity type that is electrically connected to the third semiconductor layer is formed in a third region where the third semiconductor layer partially overlaps;
A fifth semiconductor layer of a second conductivity type is formed in a fourth region adjacent to the first region and in a direction along a main surface of the semiconductor substrate and separated from the second region and the third region; The concentration of the impurity of the first conductivity type in the third semiconductor layer is the first conductivity type.
The concentration of the first conductivity type impurity in the fourth semiconductor layer is lower than the concentration of the first conductivity type impurity in the second semiconductor layer and is lower than the concentration of the first conductivity type impurity in the fourth semiconductor layer. A semiconductor device, wherein the concentration of the impurity of the first conductivity type in the three semiconductor layers is higher than the concentration in a region having the highest concentration.