JP2002270784A - Nonvolatile storage device and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a nonvolatile storage device which can prevent degradation of a transistor characteristic, and to provide a method of manufacturing the nonvolatile storage device. SOLUTION: A trench 9 is formed on a first interlayer insulating film 107, and a part of an n<+> impurity diffused region 5A is exposed. In succession, while a photoresist 8 and the film 107 are used as a mask, p-type dopant ions are ion-implanted, activation annealing operation is then executed, and a p-type diffused region 12 is formed in the lower part of the trench 9. After that, the gate region of a memory transistor 16 is formed, so as to be along the side face and the bottom face of the trench 9.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a nonvolatile memory device and a method for manufacturing the same.

[0002]

2. Description of the Related Art Conventionally, as a circuit configuration of a nonvolatile memory device in which memory cells each having a memory transistor and a selection transistor connected in series to this memory transistor are arranged in a matrix, for example,
No. 149 is disclosed.

FIG. 5 is an electric circuit diagram showing the above-mentioned circuit configuration. The nonvolatile memory device includes a plurality of memory cells MC _mn ,..., MC arranged in a matrix.
_{m + 1n + 1} ,... Each of the memory cells MC
_mn ,..., MC _{m + 1n + 1} ,... include a memory transistor MTr which is a ferroelectric gate type transistor,
A selection transistor STr for selecting the memory transistor MTr is provided. In the memory cells MC _mn ,..., MC _{m + 1n + 1} ,... In the same row, the gate of each select transistor STr is connected to the word line W _m ,.
, Wm _{+ 1} ,..., And the gate of each memory transistor MTr is connected to a control gate line CGL _m , CGL.
are connected in common by _{m + 1} ,. On the other hand, the memory cells MC _mn ,..., MC _{m + 1n + 1} ,... Aligned in the direction crossing the word lines W _m , W _{m + 1 ,.
, m + 1n + 1} ,..., each selection transistor ST
The drain of r is commonly connected by BL _n , BL _{n + 1} ,..., and the source of each memory transistor MTr is commonly connected by source lines SL _n , SL _{n + 1} ,. The source lines SL _n , SL _{n + 1} ,... Are also connected to the substrate.

[0004]

As a nonvolatile memory device as described above, an EEPROM having a floating gate structure is used.
(Electrically erasable writable read-only memory: Electric
ally Erasable and Programmable Read Only Memory)
Has been put to practical use.

FIG. 6 shows an example of an EEPR having a floating gate structure.
1 shows a cross-sectional view of an OM memory cell. In the EEPROM memory cell having the floating gate structure, a p-type semiconductor substrate 51;
The n ⁺ layers 52A, 5A formed on the p-type semiconductor substrate 51
2B and an insulating film 5 between these n ⁺ layers 52A and 52B.
A floating gate electrode 55 formed via the gate electrode 3 and a control gate electrode 56 formed on the floating gate electrode 55 via an insulating film 54 constitute a memory transistor. Further, the P-type semiconductor substrate 51, the n ⁺ layers 52B and 52C formed on the p-type semiconductor substrate 51, and a selection gate formed between the n ⁺ layers 52B and 52C via an insulating film 57. The electrode 58 forms a selection transistor.

An EEPROM having such a floating gate structure
Then, when forming the memory transistor and the selection transistor, the source / drain regions of the memory transistor and the selection transistor are formed in a self-aligned manner by ion-implanting impurities using each gate pattern of the memory transistor and the selection transistor as a mask. I have. Thereby, high integration of the memory transistor and the selection transistor is enabled.

However, when a ferroelectric gate type transistor is used as the memory transistor, after forming a ferroelectric gate of the transistor, a source gate
Since activation annealing is performed on the impurities in the drain region, some of the metal elements constituting the ferroelectric film of the ferroelectric gate diffuse into the semiconductor substrate, and the film characteristics of the ferroelectric film deteriorate. I do. In addition, when thermal stress is generated in the ferroelectric gate, cracks are generated and the shape of the ferroelectric gate changes. As a result, there is a problem that the characteristics of the ferroelectric gate type transistor are deteriorated.

Further, as the selection transistor, a MOS (Metal Oxide Semiconductor) using a conventional gate oxide film is used.
uctor) When a high-dielectric gate transistor is used instead of a transistor, deterioration of the film characteristics of the high-dielectric film and a change in the shape of the high-dielectric gate occur as in the case of the memory transistor described above. I will.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a nonvolatile memory device capable of preventing deterioration of transistor characteristics and a method of manufacturing the same.

[0010]

According to one aspect of the present invention, there is provided a nonvolatile memory device including a memory cell having a memory transistor and a select transistor connected to the memory transistor. A semiconductor substrate of a first conductivity type, a source region of the memory transistor formed on a surface layer of the semiconductor substrate and formed of an impurity diffusion region of a second conductivity type, and an interval between a source region of the memory transistor and A second conductive type connection impurity diffusion region that is formed in a surface layer of the semiconductor substrate, is a drain region of the memory transistor, and is a source region of the selection transistor, and is spaced apart from the connection impurity diffusion region. The select transistor formed on a surface layer of the semiconductor substrate and including a second conductivity type impurity diffusion region; A drain region, and an interlayer insulating film formed on a surface of the semiconductor substrate and having a trench located above between a source region of the memory transistor and the connection impurity diffusion region; Penetrating a film, the memory transistor includes a gate region formed along a side surface of the trench and a bottom surface of the trench, and formed after a heat treatment for activating impurities is performed; The selection transistor includes a gate region formed above the connection impurity diffusion region and a drain region of the selection transistor.

According to the nonvolatile memory device having the above structure, the gate region of the memory transistor is formed after the heat treatment for activating the impurity is performed.
For example, part of the metal element of the ferroelectric film provided in the gate region of the memory transistor does not diffuse into the semiconductor substrate by the heat treatment, and cracks due to thermal stress do not occur in the ferroelectric film, for example. Therefore, deterioration of transistor characteristics of the memory transistor can be prevented.

In this specification, the first conductivity type means P type or N type. The second conductivity type means N-type when the first conductivity type is P-type, and P-type when the first conductivity type is N-type.

[0013] In one embodiment of the present invention, the second conductive type impurity diffusion region having a lower impurity concentration than the source region of the memory transistor is adjacent to the source region of the memory transistor. A second conductivity type impurity diffusion region formed near the side surface and having a lower impurity concentration than the connection impurity diffusion region;
The trench is formed near the side surface of the trench so as to be adjacent to the connection impurity diffusion region.

According to the non-volatile memory device of one embodiment, the impurity diffusion region of the second conductivity type having a lower impurity concentration than the source region of the memory transistor is adjacent to the source region of the memory transistor and the connection impurity. Since the impurity diffusion region of the second conductivity type having a lower impurity concentration than the diffusion region is adjacent to the connection impurity diffusion region, the LDD (Ligh
The same effect as that of the tly-doped drain structure can be achieved, and a high breakdown voltage of the memory transistor can be realized.

In one embodiment, a ferroelectric film formed on a surface of the semiconductor substrate and a control film formed on the ferroelectric film are formed in the gate region of the memory transistor. There is a gate electrode.

In one embodiment, a buffer dielectric film formed on a surface of the semiconductor substrate and a strong dielectric formed on the buffer dielectric film are provided in the gate region of the memory transistor. There is a dielectric film and a control gate electrode formed on the ferroelectric film.

In one embodiment, the gate region of the memory transistor includes a gate insulating film formed on a surface of the semiconductor substrate and a floating gate formed on the gate region insulating film. An electrode; a ferroelectric film formed on the floating gate electrode; and a control gate electrode formed on the ferroelectric film.

In one embodiment, in the nonvolatile memory device, a tunnel insulating film formed on a surface of the semiconductor substrate and a floating gate electrode formed on the tunnel insulating film are provided in the gate region of the memory transistor. And an insulating film formed on the floating gate electrode, and a control gate electrode formed on the insulating film.

Further, the nonvolatile storage device of the present invention is a nonvolatile storage device comprising a memory cell having a memory transistor and a selection transistor connected to the memory transistor, wherein the semiconductor substrate of the first conductivity type comprises: A source region of the memory transistor formed on a surface layer of the semiconductor substrate, the source region including a second conductivity type impurity diffusion region, and a source region of the memory transistor; A second conductive type connection impurity diffusion region that is a drain region of a memory transistor and a source region of the selection transistor, and is formed on a surface layer of the semiconductor substrate at an interval from the connection impurity diffusion region; A drain region of the select transistor comprising a two-conductivity-type impurity diffusion region;
An interlayer insulating film formed on a surface of the semiconductor substrate and having a trench located above between the connection impurity diffusion region and a drain region of the select transistor;
The trench penetrates the interlayer insulating film, and the memory transistor includes a gate region formed to be located above a source region and a connection impurity diffusion region of the transistor. The select transistor is formed along a side surface of the trench and a bottom surface of the trench, and has a gate region formed after a heat treatment for activating impurities is performed. .

According to the nonvolatile memory device having the above configuration, the gate region of the select transistor is formed after the heat treatment for activating the impurity is performed.
For example, part of the metal element of the high dielectric film provided in the gate region of the select transistor does not diffuse into the semiconductor substrate by the heat treatment, and cracks due to thermal stress do not occur in the high dielectric film, for example. Therefore, it is possible to prevent the transistor characteristics of the selection transistor from deteriorating.

In one embodiment, the second conductivity type impurity diffusion region having a lower impurity concentration than the connection impurity diffusion region is adjacent to the side surface of the trench so as to be adjacent to the connection impurity diffusion region. And a second conductivity type impurity diffusion region having a lower impurity concentration than the drain region of the select transistor is formed near the side surface of the trench so as to be adjacent to the drain region of the select transistor. I have.

According to the nonvolatile memory device of the embodiment, the second conductivity type impurity diffusion region having a lower impurity concentration than the connection impurity diffusion region is adjacent to the connection impurity diffusion region, Since the impurity diffusion region of the second conductivity type having a lower impurity concentration than the drain region is adjacent to the drain region of the selection transistor, LD
The same effect as that of the D structure can be obtained, and a high breakdown voltage of the selection transistor can be realized.

In one embodiment, the gate region of the select transistor includes a gate insulating film formed on a surface of the semiconductor substrate, and a select gate electrode formed on the gate insulating film. There is.

In one embodiment of the present invention, in the nonvolatile memory device, a dielectric film formed on a surface of the semiconductor substrate and a select gate electrode formed on the dielectric film are provided in the gate region of the select transistor. There is.

In one embodiment of the present invention, in the nonvolatile memory device, a buffer dielectric film formed on a surface of the semiconductor substrate and a buffer dielectric film formed on the buffer dielectric film are formed in the gate region of the select transistor. There is a dielectric film and a select gate electrode formed on the high dielectric film.

In one embodiment, in the nonvolatile memory device, a gate insulating film formed on a surface of the semiconductor substrate and a floating gate electrode formed on the gate insulating film are provided in the gate region of the select transistor. A high-dielectric film formed on the floating gate electrode; and a select gate electrode formed on the high-dielectric film.

In one embodiment, the gate region of the select transistor includes a gate insulating film formed on a surface of the semiconductor substrate and a select gate electrode formed on the gate insulating film. And an insulating film formed on the select gate electrode, and an additional gate electrode formed on the insulating film.

In one embodiment, the additional gate electrode is in an electrically floating state.

In one embodiment, a predetermined constant voltage is supplied to the additional gate electrode.

In one embodiment, the additional gate electrode is electrically connected to the select gate electrode.

A method of manufacturing a nonvolatile memory device according to the present invention is directed to a method of manufacturing a nonvolatile memory device including a memory cell having a ferroelectric gate type memory transistor and a select transistor connected to the memory transistor. In the method, a first second conductivity type impurity diffusion region and a second second conductivity type impurity diffusion region are formed in a surface layer of a first conductivity type semiconductor substrate at an interval, and Forming a gate region of the select transistor above between the first second conductivity type impurity diffusion region and the second second conductivity type impurity diffusion region; and a surface of the semiconductor substrate and a gate of the select transistor. Forming an interlayer insulating film covering the region, forming a trench in the interlayer insulating film,
A step of exposing a part of the first second conductivity type impurity diffusion region and a step of activating the first conductivity type impurity after ion implantation of the first conductivity type impurity through the trench. Forming a first-conductivity-type impurity diffusion region below the trench by performing a heat treatment; and forming a gate region of the memory transistor along a side surface of the trench and a bottom surface of the trench. It is characterized by having.

According to the method of manufacturing a nonvolatile memory device having the above-described structure, the first and second conductive type semiconductor substrates are provided on the surface layer.
A second conductivity type impurity diffusion region, and
The second impurity diffusion region of the second conductivity type is covered with an interlayer insulating film. A trench is formed in the interlayer insulating film, and a first second
A part of the conductive impurity diffusion region is exposed. And
After the first conductivity type impurity is ion-implanted into a part of the first second conductivity type impurity diffusion region exposed from the trench, the impurity is activated by heat treatment. Then,
A first conductivity type impurity diffusion region is formed below the trench. At this time, the source region of the memory transistor is formed in a self-aligned manner, and the drain region of the memory transistor and the second conductive type connection impurity diffusion region serving as the source region of the select transistor are formed in a self-aligned manner. Thereafter, a gate region of the memory transistor is formed along the side and bottom surfaces of the trench.

As described above, since the gate region of the memory transistor is formed after the heat treatment, a part of the metal element of the ferroelectric film provided in the gate region, for example, does not diffuse into the semiconductor substrate and cracks due to thermal stress are generated. Does not occur in the ferroelectric film, for example. Therefore, deterioration of transistor characteristics of the memory transistor can be prevented.

Further, since the gate region of the memory transistor is formed along the side and bottom surfaces of the trench,
A ferroelectric gate is formed in a self-aligned manner with respect to the source region and the connection impurity diffusion region of the memory transistor. Therefore, miniaturization of the memory transistor can be realized.

Further, a method of manufacturing a nonvolatile memory device according to the present invention includes a memory cell having a ferroelectric gate type memory transistor and a high dielectric gate type select transistor connected to the memory transistor. In a method for manufacturing a nonvolatile memory device, a step of forming an impurity diffusion region of a second conductivity type in a surface layer of a semiconductor substrate of a first conductivity type; and a step of forming an interlayer insulating film covering a surface of the semiconductor substrate. Forming a first trench in the interlayer insulating film to expose a part of the second conductivity type impurity diffusion region; and ion-implanting a first conductivity type impurity through the first trench. Performing a heat treatment for activating the first conductivity type impurity to form a first first conductivity type impurity diffusion region below the first trench; Forming a second trench in the interlayer insulating film at a location different from that of the wrench to expose a part of the impurity diffusion region of the second conductivity type; and forming a first conductive layer through the second trench. Forming a second first conductivity type impurity diffusion region below the second trench by performing a heat treatment for activating the first conductivity type impurity after ion implantation of the first conductivity type impurity Forming a gate region of the select transistor along a side surface of the second trench and a bottom surface of the second trench; and forming a gate region of the select transistor along a side surface of the first trench and a bottom surface of the first trench. Forming a gate region of the memory transistor.

According to the method of manufacturing a nonvolatile memory device having the above structure, a second conductivity type impurity diffusion region is formed in a surface layer of the first conductivity type semiconductor substrate, and the second conductivity type impurity diffusion region is formed. Is covered with an interlayer insulating film. A first trench is formed in the interlayer insulating film to expose a part of the impurity diffusion region of the second conductivity type. Then, after the first conductivity type impurity is ion-implanted into a part of the second conductivity type impurity diffusion region exposed from the second trench, the impurity is activated by heat treatment. Then, a first first conductivity type impurity diffusion region is formed below the first trench.
At this time, the source region of the memory transistor is formed in a self-aligned manner. Next, a second trench is formed in the interlayer insulating film at a location different from the first trench, and a part of the impurity diffusion region of the second conductivity type is exposed. next,
After the first conductivity type impurity is ion-implanted into a part of the second conductivity type impurity diffusion region exposed from the first trench, the impurity is activated by heat treatment. Then,
A second first conductivity type impurity diffusion region is formed below the second trench. At this time, the drain region of the memory transistor and the connection impurity diffusion region serving as the source region of the selection transistor are formed in a self-alignment manner, and the drain region of the selection transistor is formed in a self-alignment manner. Thereafter, a gate region of the select transistor is formed along the side and bottom surfaces of the second trench, and a gate region of the memory transistor is formed along the side surface and bottom surface of the first trench.

As described above, since the gate region of the memory transistor is formed after the heat treatment, a part of the metal element of the ferroelectric film provided in the gate region, for example, does not diffuse into the semiconductor substrate, and cracks due to thermal stress are generated. It does not occur in the ferroelectric film. Therefore, deterioration of transistor characteristics of the memory transistor can be prevented.

Further, since the gate region of the select transistor is formed after the heat treatment, part of the metal element of the high dielectric film provided in the gate region, for example, does not diffuse into the semiconductor substrate, and cracks due to thermal stress are generated, for example. Does not occur in the dielectric film. Therefore, it is possible to prevent the transistor characteristics of the selection transistor from deteriorating.

Further, since the gate region of the memory transistor is formed along the side and bottom surfaces of the first trench, the gate region of the memory transistor is self-aligned with respect to the source region and the connection impurity diffusion region of the memory transistor. Formed consistently. Therefore, miniaturization of the memory transistor can be realized.

Further, since the high dielectric gate of the select transistor is formed along the side and bottom surfaces of the second trench, the gate region of the select transistor is connected to the connection impurity diffusion region and the drain region of the select transistor. Are formed in a self-aligned manner. Therefore, miniaturization of the selection transistor can be realized.

[0041]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a nonvolatile semiconductor device and a method of manufacturing the same according to the present invention will be described in detail with reference to the drawings.

(First Embodiment) FIGS. 1A to 1E
FIG. 4 is a manufacturing process diagram of the nonvolatile semiconductor device according to the first embodiment of the present invention. In FIG. 1E, reference numeral 16 denotes a ferroelectric gate type memory transistor, and reference numeral 6 denotes a selection transistor. More specifically, the selection transistor 6 is an n-channel MOS transistor.

Hereinafter, a method of manufacturing the nonvolatile semiconductor device will be described with reference to FIGS.

First, as shown in FIG. 1A, a field oxide film 2 made of SiO ₂ is formed on a predetermined region of a p-type silicon substrate 1 as a semiconductor substrate of the first conductivity type by LOCOS.
(Local oxidation of silicon) method.
Thereafter, the p without the field oxide film 2 is formed.
An n ⁺ impurity diffusion region 5A as a first second conductivity type impurity diffusion region and an n ⁺ impurity diffusion region 5B as a second second conductivity type impurity diffusion region are provided on the surface layer of the silicon substrate 1. Are formed at intervals. This n ⁺ impurity diffusion region 5B becomes a drain region of the selection transistor 6 (see FIG. 1E). Then, the n ⁺ impurity diffusion region 5
A gate oxide film 3 and a select gate electrode 4 are sequentially formed above the region between A and the n ⁺ impurity diffusion region 5B by using a known technique.

Next, as shown in FIG. 1B, a first interlayer insulating film 1007 made of SiO _{2 is formed} on the p-type silicon substrate 1 by the CVD method to form an n ⁺ impurity diffusion region 5A. , N ⁺ impurity diffusion region 5B and select gate electrode 4 are covered. Thereafter, the first interlayer insulating film 100
A photoresist 8 having a desired pattern is formed on 7.

Next, as shown in FIG. 1C, using the photoresist 8 as a mask, a first interlayer insulating film 107 is formed.
And an n ⁺ impurity diffusion region 5A (see FIG. 1B)
Is formed using a known technique. Thereby, a part of n ⁺ impurity diffusion region 5A is exposed from trench 9. Subsequently, using the photoresist 8 and the first interlayer insulating film 107 as a mask, the first
After ion implantation of a p-type dopant ion as a conductivity type impurity, activation annealing is performed so that the p-type impurity diffusion region 12 as a first conductivity type impurity diffusion region is formed in a region corresponding to the bottom of the trench 9. Form. That is, the activation annealing forms the p-type impurity diffusion region 12 below the trench 9. At this time, the trench 9
N ⁺ impurity diffusion region 10A is formed on one side of a region corresponding to the bottom of the substrate in a self-aligned manner. At the same time, on the other side of the region corresponding to the bottom of the trench 9, n ⁺
Connection impurity diffusion region 10B formed of an impurity diffusion region is formed in a self-aligned manner. The n ⁺ impurity diffusion region 10A
Is a source region of the memory transistor 16 (see FIG. 1E), and the n ⁺ impurity diffusion region 10B is
It serves as a drain region of the memory transistor 16 and serves as a source region of the selection transistor 6. Further, simultaneously with the formation of the n ⁺ impurity diffusion region 10A and the connection impurity diffusion region 10B, n ⁻ impurity diffusion regions 11A and 11B are formed. These n ⁻ impurity diffusion regions 11A and 11B are located near the substrate-side edge of trench 9 and are adjacent to both sides of p-type impurity diffusion region 12.

Next, Si ₃ N ₄ as a material of the buffer dielectric film 13 shown in FIG. 1D is laminated on the photoresist 8 and the p-type silicon substrate 1 by a CVD method. SrBi ₂ (TA _X N
B _1-X ) ₂ O ₉ (0 ≦ X ≦ 1) (hereinafter sometimes referred to as SBT) was converted to LSMCD (electrodeposition atomization: Liquid SourceM).
The Pt, which is a material of the control gate electrode 15, is further laminated by a vacuum deposition method. Then, by continuously patterning by lithography and dry etching, Si ₃ N
_{Then, a} buffer dielectric film 13 made of No. _{4, a} ferroelectric film made of SBT, and a control electrode 15 made of Pt are formed. Here, a buffer dielectric film 13, a ferroelectric film 14, and a control electrode 15 are provided in the gate region of the memory transistor 16. The buffer dielectric film 13, the ferroelectric film 14, and the control electrode 15 are formed along the side and bottom surfaces of the trench 9. That is, the gate region of the memory transistor 16 is formed along the side and bottom surfaces of the trench 9.

Next, as shown in FIG. 1 (e), SiO ₂
Forming a second interlayer insulating film 17 made of
The memory transistor 16 and the select transistor 6 are covered. Then, a first interlayer insulating film 7 and a second interlayer insulating film are provided above the source region (n ⁺ impurity diffusion region 10A) of the memory transistor 16 and the drain region (n ⁺ impurity diffusion region 5B) of the selection transistor. A contact hole penetrating the film 17 is formed by using a known technique. Finally, the contact holes are filled with a conductive material by a sputtering method to form a source electrode 18A and a drain electrode 18B.

As described above, since the buffer dielectric film 13, the ferroelectric film 14, and the control electrode 15 are formed after the activation annealing, the buffer dielectric film 1
3. Some of the elements constituting the ferroelectric film 14 and the control electrode 15 do not diffuse into the p-type silicon substrate 1, and cracks due to thermal stress cause the buffer dielectric film 13 and the ferroelectric film 14 to crack.
And does not occur on the control electrode 15. Therefore, deterioration of transistor characteristics of the memory transistor 16 can be prevented.

Since the buffer dielectric film 13, the ferroelectric film 14, and the control electrode 15 are formed along the side and bottom surfaces of the trench 9, the memory transistor 16
Source region (n ⁺ impurity diffusion region 10A), and
The gate region of the memory transistor 16 is formed in a self-aligned manner with respect to the drain region (connection impurity diffusion region 10B) of the memory transistor 16. Therefore, miniaturization of the memory transistor 16 can be realized.

Further, with the formation of the p-type impurity diffusion region 12, the n ⁻ impurity diffusion regions 11A and 11B are formed so as to be adjacent to both sides of the p-type impurity diffusion region 12, so that the same effect as in the LDD structure can be obtained. And the breakdown voltage of the memory transistor 16 can be improved.

In the first embodiment, the ferroelectric film 1
Although SBT was used as the material of No. 4, for example, (PB _X L
A _1-X ) (Zr _Y Ti _1-Y ) O ₃ (0 ≦ X ≦ 1,0
≦ Y ≦ 1), (BA _X Sr _1−X ) TiO ₃ (0 ≦ X ≦
1), BAMgF ₄ , Bi ₄ Ti ₃ O ₁₂ or the like may be used.

Although the dielectric buffer film 13 is made of Si ₃ N ₄ , for example, CeO ₂ , Y ₂
O ₃ , ZrO ₂ , MgO, SrTiO ₃ , Bi ₂ SiO
₅ , SiO ₂ or the like may be used.

Further, although Pt was used as the material of the control gate electrode 15, for example, Ir, Ru, Au, A
A metal material such as g, A1, Rh, and Os and an oxide material thereof, or polysilicon (poly-Si) may be used.

In the first embodiment, the buffer dielectric film 13, the ferroelectric film 14, and the control gate electrode 15 are provided in the gate region of the memory transistor 16. For example, the ferroelectric film And a control gate electrode formed on the ferroelectric film.

The gate region of the memory transistor 16 includes a gate insulating film, a floating gate electrode formed on the gate insulating film, a ferroelectric film formed on the floating gate electrode, and a ferroelectric film. And a control gate electrode formed on the film.

The gate region of the memory transistor 16 has a tunnel insulating film, a floating gate electrode formed on the tunnel insulating film, an insulating film formed on the floating gate electrode, and a gate insulating film formed on the insulating film. Control gate electrode.

Although the p-type silicon substrate 1 is used in the first embodiment, an n-type silicon substrate may be used.
The substrate is not limited to a silicon substrate, but may be any semiconductor substrate.

(Second Embodiment) FIGS.
(C), FIGS. 3 (a) to (c) and FIGS. 4 (a) to (d)
FIG. 9 is a manufacturing process diagram of the nonvolatile memory device according to the second embodiment of the present invention. In FIG. 4D, reference numeral 116 denotes a ferroelectric gate type memory transistor, and reference numeral 106 denotes a high dielectric gate type selection transistor.

Hereinafter, a method of manufacturing the nonvolatile memory device will be described with reference to FIGS. 2A to 2C, 3A to 3C, and 4A to 4D.

First, as shown in FIG. 2A, a field oxide film 22 made of SiO ₂ is formed on a predetermined region of a p-type silicon substrate 21 as a semiconductor substrate of the first conductivity type by LOC.
It is formed by using the OS method. Subsequently, using the field oxide film 22 as a mask, n-type dopant ions as impurities of the second conductivity type are ion-implanted into the surface layer of the p-type silicon substrate 21, and then activation annealing is performed. Thus, n ⁺ impurity diffusion region 23 as a second conductivity type impurity diffusion region is formed on the surface layer of p-type silicon substrate 21 on which field oxide film 22 is not provided.

Next, as shown in FIG. 2B, Si ⁺ is formed on the n ⁺ impurity diffusion region 23 and the field oxide film 22.
A first interlayer insulating film 10024 made of O _{2 is} formed by a CVD method. Further, the first interlayer insulating film 1002
4, a first photoresist 25 having a desired pattern is formed.

Next, as shown in FIG.
Using the photoresist 25 as a mask, the n ⁺ impurity diffusion region 23 (FIG. 2) penetrates the first interlayer insulating film 1024.
A first trench 26 reaching the surface of (b) is formed by using a known technique. As a result, a part of the n ⁺ impurity diffusion region 23 is exposed from the first trench 26. Subsequently, using the first photoresist 25 and the first interlayer insulating film 1024 as a mask, p-type dopant ions are implanted, and then activation annealing is performed.
Thus, a p-type impurity diffusion region 29 as a first first conductivity type impurity diffusion region is formed in a region corresponding to the bottom of the first trench 26. That is, a p-type impurity diffusion region 29 is formed below the first trench 26. At this time, n ⁺ is formed on both sides of the first trench 26.
Impurity diffusion regions 27A and 27B are formed in a self-aligned manner. The n ⁺ impurity diffusion region 27A serves as a drain region of the memory transistor 116 (see FIG. 4D). Further, the n ⁺ impurity diffusion regions 27A and 27B
Is formed, n ^- impurity diffusion regions 28A and 28B are formed. The n ^- impurity diffusion regions 28A and 28B
Are located near the substrate-side edge of the first trench 26 and are adjacent to both sides of the p-type impurity diffusion region 29.

Next, as shown in FIG. 3A, a second photoresist 30 having a desired pattern is formed on the p-type silicon substrate 21 and the first interlayer insulating film 1024.
To form

Next, as shown in FIG.
Using the photoresist 30 as a mask, the first interlayer insulating film 1
N through 24⁺The impurity diffusion region 27B (FIG. 3A)
The second trench 31 reaching the surface of
It is formed using. Thereby, the second trench 3
1 to n⁺Part of impurity diffusion region 27B is exposed. Pull
Continuing, the second photoresist 30 and the first layer
Using the inter-insulating film 124 as a mask, impurities of the first conductivity type
After implanting the same p-type dopant ions,
Annealing annealing makes it possible to expand the impurity of the second first conductivity type.
The p-type impurity diffusion region 34 serving as a diffusion region is
It is formed in a region corresponding to the bottom of the helix 31. That is,
Below the second trench 31, a p-type impurity diffusion region 34 is formed.
It is formed. At this time, at the bottom of the second trench 31
On one side of the corresponding area, n ⁺From impurity diffusion region
Connection impurity diffusion region 32A is formed in a self-aligned manner.
You. At the same time, it corresponds to the bottom of the second trench 31.
On the other side of the region⁺The impurity diffusion region 32B
It is formed in a self-aligned manner. The n⁺Impurity diffusion region 32
B is a drain of the selection transistor 106 (see FIG. 4D).
And a connection impurity diffusion region 32A.
Is the drain region of the memory transistor 116.
And the source region of the select transistor 106
It is what becomes. The connection impurity diffusion region 32
A, n⁺Simultaneously with the formation of the impurity diffusion region 32B, n⁻Unfortunate
Pure substance diffusion regions 33A and 33B are formed. This n⁻Unfortunate
The pure substance diffusion regions 33A and 33B are formed in the second trench 31.
The p-type impurity diffusion region is located near the edge on the substrate side.
34 on both sides.

Next, as shown in FIG. 3C, a third photoresist 35 is formed to cover the opening of the first trench 26.

Next, the p-type silicon substrate 21 and the third
On the photoresist 35 and the first interlayer insulating film 124
Next, the first buffer dielectric film 36 shown in FIG.
Material Si₃N₄Are stacked by the CVD method.
TA which is a material of the dielectric film 37 ₂O₅To LSMCD method
And a material for the selection gate electrode 38.
Pt is laminated by a vacuum deposition method. And lithograph
Patterning by dry and dry etching methods
The Si₃N₄A first battery
Fur dielectric film 36, TA₂O₅High dielectric film 3 made of
7 and Pt are formed.
Here, the gate region of the selection transistor 106 is
Are the first buffer dielectric film 36, the high dielectric film 37 and
And a select gate electrode 38. And the first bus
Buffer film 36, high dielectric film 37 and selective gate.
The electrode 38 extends along the side and bottom surfaces of the second trench 31.
It is formed as follows. That is, the selection transistor
The gate region of the gate 106 is formed on the side surface of the second trench 31,
It is formed along the bottom surface.

Next, as shown in FIG. 4B, a fourth photoresist 40 is formed to cover the high dielectric gate of the select transistor 39.

Next, on the p-type silicon substrate 21, the fourth photoresist 40 and the first interlayer insulating film 124, the Si, which is the material of the second buffer dielectric film 41 shown in FIG. ₃ N ₄ is deposited by the CVD method, then SBT, which is the material of the ferroelectric film 42, is deposited by the LSMCD method, and Pt which is the material of the control gate electrode 43 is further deposited.
Are laminated by a vacuum evaporation method. Thereafter, a second buffer dielectric film 41 made of Si ₃ N _{4, a} ferroelectric film 42 made of SBT, and a control gate electrode 43 made of Pt are formed by continuous patterning by lithography and dry etching. I do. Here, in the gate region of the memory transistor 116,
There is a second buffer dielectric film 41, a ferroelectric film 42, and a control gate electrode 43. The second buffer dielectric film 41, the ferroelectric film 42, and the control gate electrode 43 are formed along the side and bottom surfaces of the first trench 26. That is, the gate region of the memory transistor 116 is formed along the side and bottom surfaces of the first trench 26.

Next, as shown in FIG. 4 (d), SiO ₂
A second interlayer insulating film 45 is formed by CVD to cover the memory transistor 116 and the select transistor 106. Thereafter, the memory transistor 1
Above the 16 source regions (n ⁺ impurity diffusion regions 27A) and the drain regions (n ⁺ impurity diffusion regions 32B) of the selection transistors 39, the second interlayer insulating film 4
5 and a contact hole penetrating the first interlayer insulating film 24 is formed by using a known technique. Then, the source electrode 46A and the drain electrode 46B are formed by filling the contact hole with a conductive material by a sputtering method.

As described above, since the second buffer dielectric film 41, the ferroelectric film 42, and the control gate electrode 43 are formed after the activation annealing, the second buffer dielectric film 41, the ferroelectric Some of the elements constituting the body film 42 and the control gate electrode 43 do not diffuse into the p-type silicon substrate 21, and cracks due to thermal stress occur, and the second buffer dielectric film 41 and the ferroelectric film 42 It does not occur on the gate electrode 43. Therefore, deterioration of the transistor characteristics of the memory transistor 116 can be prevented.

Since the first buffer dielectric film 36, the high dielectric film 37 and the select gate electrode 38 are formed after the activation annealing, the first buffer dielectric film 36, the high dielectric film 37 and some of the elements constituting the select gate electrode 38 do not diffuse into the p-type silicon substrate 21, and cracks due to thermal stress cause cracks in the first buffer dielectric film 36, high dielectric film 37, and select gate electrode 38. Does not occur. Therefore, deterioration of the transistor characteristics of the selection transistor 106 can be prevented.

Further, since the second buffer dielectric film 41, the ferroelectric film 42 and the control gate electrode 43 are formed along the side and bottom surfaces of the first trench 26, the source region of the memory transistor 116 ( ⁺ Impurity diffusion region 27A) and the drain region (connection impurity diffusion region 32A) of memory transistor 116, the gate region of memory transistor 116 is formed in a self-aligned manner. Therefore, miniaturization of the memory transistor 116 can be realized.

Further, since the first buffer dielectric film 36, the high dielectric film 37 and the select gate electrode 38 are formed along the side and bottom surfaces of the second trench 31, the source region of the select transistor 106 ( The gate region of the selection transistor 106 is formed in a self-alignment manner with respect to the connection impurity diffusion region 32A) and the drain region ( ⁺ impurity diffusion region 32B) of the selection transistor 106.
Therefore, miniaturization of the selection transistor 106 can be realized.

Further, with the formation of the p-type impurity diffusion region 29, the n ⁻ impurity diffusion regions 28A and 28B are formed so as to be adjacent to both sides of the p-type impurity diffusion region 29, so that the same effect as in the LDD structure is obtained. And the breakdown voltage of the memory transistor 116 can be improved.

In addition, with the formation of the p-type impurity diffusion region 34, the n ⁻ impurity diffusion regions 33A and 33B are formed so as to be adjacent to both sides of the p-type impurity diffusion region 34. And the breakdown voltage of the memory transistor 116 can be improved.

In the second embodiment, the high dielectric film
And TA₂O₅Was used, but (PB _XLA_1-X) (Z
r_YTi_1-Y) O₃(0 ≦ X ≦ 1, 0 ≦ Y ≦ 1), B
A_XLA_1-X(Zr_YTi_1-Y) O₃(0 ≦ X ≦
1, 0 ≦ Y ≦ 1), (BA_XSr_1-X) TiO₃(0
≦ X ≦ 1), Si₃N₄And so on.

Further, the first trench 26 and the second trench 31 are separately formed, and the memory transistor 116 is formed.
Although the source / drain regions of the above and the source / drain regions of the selection transistor 106 are formed separately, they may be formed simultaneously.

Although the memory transistor 116 is formed after the selection transistor 106 is formed, the memory transistor 116 may be formed in the reverse order or simultaneously.

In the second embodiment, the second buffer dielectric film 41, the ferroelectric film 42, and the control gate electrode 43 are provided in the gate region of the memory transistor 116. There may be a dielectric film and a control gate electrode formed on the ferroelectric film.

The gate region of the memory transistor 116 includes a gate insulating film, a floating gate electrode formed on the gate insulating film, a ferroelectric film formed on the floating gate electrode, and a ferroelectric film. And a control gate electrode formed on the film.

The gate region of the memory transistor 116 includes a tunnel insulating film, a floating gate electrode formed on the tunnel insulating film, an insulating film formed on the floating gate electrode, and a gate region formed on the insulating film. Control gate electrode.

In the second embodiment, the first buffer dielectric film 36, the high dielectric film 37 and the select gate electrode 3 are provided in the gate region of the select transistor 106.
8, the gate insulating film, the floating gate electrode formed on the gate insulating film, the high dielectric film formed on the floating gate electrode, and the high dielectric film formed on the high dielectric film There may be a select gate electrode.

The gate region of the select transistor 106 may have a gate insulating film and a select gate electrode formed on the gate insulating film.

The gate region of the select transistor 106 may have a dielectric film and a select gate electrode formed on the dielectric film.

The gate region of the select transistor 106 includes a gate insulating film, a select gate electrode formed on the gate insulating film, an insulating film formed on the select gate electrode, And an additional gate electrode formed on the substrate. In this case, the additional gate electrode may be in an electrically floating state. Further, a predetermined constant voltage may be supplied to the additional gate electrode. Further, the additional gate electrode may be electrically connected to a select gate electrode.

Although the p-type silicon substrate 21 is used in the second embodiment, an n-type silicon substrate may be used. The substrate is not limited to a silicon substrate, but may be any semiconductor substrate.

[0088]

As is clear from the above, according to the nonvolatile memory device of the present invention, the gate region of the memory transistor is formed after the heat treatment for activating the impurity is performed. For example, part of the metal element of the ferroelectric film provided in the gate region does not diffuse into the semiconductor substrate, and cracks due to thermal stress do not occur in the ferroelectric thin film, for example. As a result, deterioration of transistor characteristics of the memory transistor can be prevented.

In one embodiment of the nonvolatile memory device, the impurity diffusion region of the second conductivity type having a lower impurity concentration than the source region of the memory transistor is adjacent to the source region of the memory transistor and is higher than the connection impurity diffusion region. Since the impurity diffusion region of the second conductivity type having a low impurity concentration is adjacent to the connection impurity diffusion region, the withstand voltage of the memory transistor can be increased.

According to the nonvolatile memory device of the present invention, since the gate region of the select transistor is formed after the heat treatment for activating the impurity is performed, for example, a high dielectric film provided in the gate region is provided. Does not diffuse into the semiconductor substrate, and cracks due to thermal stress do not occur in, for example, the high dielectric film. Therefore, it is possible to prevent the transistor characteristics of the selection transistor from deteriorating.

In one embodiment, the second conductive type impurity diffusion region having a lower impurity concentration than the drain region of the selection transistor is adjacent to the drain region of the selection transistor and the connection impurity diffusion region. Since the impurity diffusion region of the second conductivity type having a lower impurity concentration is adjacent to the connection impurity diffusion region, the withstand voltage of the selection transistor can be increased.

The method of manufacturing the nonvolatile memory device according to the present invention
After the heat treatment for activating the first conductivity type impurities, the gate region of the memory transistor is formed. Therefore, for example, a part of the metal element of the ferroelectric film provided in the gate region is removed from the semiconductor substrate. Therefore, cracks due to thermal stress do not occur in, for example, the ferroelectric film, and deterioration of transistor characteristics of the memory transistor can be prevented.

Since the gate region of the memory transistor is formed along the side and bottom surfaces of the trench, the gate region is formed in a self-aligned manner with respect to the source region and the connection impurity diffusion region of the memory transistor. Memory transistors can be miniaturized.

The method for manufacturing a nonvolatile memory device according to the present invention
After the heat treatment for activating the impurities of the first conductivity type, the gate region of the memory transistor is formed. For example, a part of the metal element of the ferroelectric film provided in the gate region is left in the semiconductor substrate. Without diffusion, cracks due to thermal stress do not occur in, for example, the ferroelectric film, and deterioration of transistor characteristics of the memory transistor can be prevented.

After the heat treatment for activating the first conductivity type impurities, the gate region of the select transistor is formed. Therefore, for example, one of the metal elements of the high dielectric film provided in the gate region is formed. The portion does not diffuse into the semiconductor substrate, cracks due to thermal stress do not occur in the high dielectric film, for example, and deterioration of transistor characteristics of the select transistor can be prevented.

Since the gate region of the memory transistor is formed along the side and bottom surfaces of the first trench, the gate region is formed in a self-aligned manner with respect to the source region and the connection impurity diffusion region of the memory transistor. Thus, miniaturization of the memory transistor can be realized.

Since the high dielectric gate region of the select transistor is formed along the side and bottom surfaces of the second trench, the gate region is self-aligned with the connection impurity diffusion region and the drain region of the select transistor. In this case, the selection transistor can be miniaturized.

[Brief description of the drawings]

FIGS. 1A to 1E are manufacturing process diagrams of a nonvolatile memory device according to a first embodiment of the present invention.

FIGS. 2A to 2C are views showing a manufacturing process of a nonvolatile memory device according to a second embodiment of the present invention.

FIG. 3A to FIG. 3C are manufacturing process diagrams of the nonvolatile memory device according to the second embodiment of the present invention.

FIGS. 4A to 4D are manufacturing process diagrams of the nonvolatile memory device according to the second embodiment of the present invention.

FIG. 5 is an electric circuit diagram of a conventional nonvolatile memory device.

FIG. 6 is a cross-sectional view of an EEPROM memory cell having a floating gate structure.

[Description of Signs] 1 p-type silicon substrate 3 gate oxide film, 4 selection gate electrode 5A, 5B n ⁺ impurity diffusion region 6 selection transistor 7 first interlayer insulating film 9 trench 5A, 5B impurity diffusion region 10A impurity diffusion region 10B Connection impurity diffusion region 11A, 11B n ^- impurity diffusion region 12 p-type impurity diffusion region 13 buffer dielectric film 14 ferroelectric film 15 control gate electrode 16 memory transistor 21 p-type silicon substrate 23 n ⁺ impurity diffusion region 24 first interlayer insulating film 26 first trench 27A, 27B ^{n +} impurity diffusion regions 28A, 28B n ^- impurity diffusion region 29 p-type impurity diffusion region 31 and the second trench 32A connected to the impurity diffusion region 32B ⁺ impurity diffusion regions 33A, 33B n ^- Impurity diffusion region 34 P-type impurity diffusion region 36 First buffer dielectric film 37 High dielectric film 38 Select gate electrode 41 Second buffer dielectric film 42 Ferroelectric film 43 Control gate electrode 106 Select transistor 116 Memory transistor

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 29/792 F-term (Reference) 5F083 EP22 EP33 EP49 EP63 EP68 FR05 FR06 GA09 GA27 JA06 JA14 JA15 JA17 JA19 JA32 JA36 JA38 JA56 PR29 PR33 PR36 5F101 BA62 BB02 BB08 BD07 BD22 BD37 BH09 BH16 BH19 5F140 AA00 AA19 AC32 BA01 BC09 BD01 BD07 BD12 BE09 BE10 BE20 BF01 BF05 BG27 BG38 BH15 BK03 BK13 BK21 BK25 CB01 CC01 CC03

Claims (18)

[Claims] 1. A non-volatile memory device comprising a memory cell having a memory transistor and a select transistor connected to the memory transistor, wherein the first conductive type semiconductor substrate is formed on a surface layer of the semiconductor substrate. A source region of the memory transistor formed of a second conductivity type impurity diffusion region, and a drain region of the memory transistor formed on a surface layer of the semiconductor substrate at an interval from a source region of the memory transistor; A second conductivity type connection impurity diffusion region which is a source region of the selection transistor; and a second conductivity type impurity diffusion region formed on the surface layer of the semiconductor substrate at a distance from the connection impurity diffusion region. A drain region of the select transistor; a memory region formed on a surface of the semiconductor substrate; An interlayer insulating film having a trench located above between the source region of the transistor and the connection impurity diffusion region, wherein the trench penetrates the interlayer insulating film, and the memory transistor has a side surface of the trench. And a gate region formed along the bottom surface of the trench and formed after a heat treatment for activating an impurity is performed. The selection transistor includes the connection impurity diffusion region and the selection transistor. A non-volatile memory device, comprising: a gate region formed above the drain region of the non-volatile memory device. 2. The non-volatile memory device according to claim 1, wherein a second conductivity type impurity diffusion region having a lower impurity concentration than the source region of the memory transistor is adjacent to the source region of the memory transistor. And a second conductivity type impurity diffusion region having a lower impurity concentration than the connection impurity diffusion region is formed near the side surface of the trench so as to be adjacent to the connection impurity diffusion region. A non-volatile memory device characterized by being formed in a non-volatile memory device. 3. The non-volatile memory device according to claim 1, wherein the gate region of the memory transistor includes a ferroelectric film formed on a surface of the semiconductor substrate, and the ferroelectric film. A nonvolatile memory device, comprising: a control gate electrode formed thereon. 4. The non-volatile memory device according to claim 1, wherein the gate region of the memory transistor includes a buffer dielectric film formed on a surface of the semiconductor substrate, and the buffer dielectric film. A nonvolatile memory device comprising: a ferroelectric film formed thereon; and a control gate electrode formed on the ferroelectric film. 5. The non-volatile memory device according to claim 1, wherein the gate region of the memory transistor includes: a gate insulating film formed on a surface of the semiconductor substrate; A non-volatile memory device, comprising: a floating gate electrode formed on the ferroelectric film; a ferroelectric film formed on the floating gate electrode; and a control gate electrode formed on the ferroelectric film. 6. The nonvolatile memory device according to claim 1, wherein the gate region of the memory transistor includes a tunnel insulating film formed on a surface of the semiconductor substrate; A nonvolatile memory device comprising: a formed floating gate electrode; an insulating film formed on the floating gate electrode; and a control gate electrode formed on the insulating film. 7. A non-volatile memory device including a memory cell having a memory transistor and a select transistor connected to the memory transistor, wherein the semiconductor substrate is of a first conductivity type and is formed on a surface layer of the semiconductor substrate. A source region of the memory transistor including a second conductivity type impurity diffusion region; and a drain region of the memory transistor formed in a surface layer of the semiconductor substrate with an interval from the source region of the memory transistor; A second conductivity type connection impurity diffusion region which is a source region of the selection transistor; and a second conductivity type impurity diffusion region formed on the surface layer of the semiconductor substrate at a distance from the connection impurity diffusion region. A drain region of the select transistor; and a connection impurity formed on a surface of the semiconductor substrate. An interlayer insulating film having an upper trench between the diffusion region and the drain region of the select transistor, wherein the trench penetrates the interlayer insulating film; A gate region formed above a region between the region and the connection impurity diffusion region; the select transistor is formed along a side surface of the trench and a bottom surface of the trench; A non-volatile memory device having a gate region formed after a heat treatment for activating the semiconductor device. 8. The non-volatile memory device according to claim 7, wherein said second conductivity type impurity diffusion region having a lower impurity concentration than said connection impurity diffusion region is adjacent to said connection impurity diffusion region. A second conductivity type impurity diffusion region having a lower impurity concentration than the drain region of the select transistor is formed near the side surface of the trench and adjacent to the side surface of the trench so as to be adjacent to the drain region of the select transistor. A non-volatile memory device characterized by being formed in a non-volatile memory device. 9. The nonvolatile memory device according to claim 7, wherein the gate region of the select transistor includes a gate insulating film formed on a surface of the semiconductor substrate, and a gate insulating film formed on the gate insulating film. A nonvolatile memory device characterized by having a formed select gate electrode. 10. The nonvolatile memory device according to claim 7, wherein the gate region of the select transistor includes: a dielectric film formed on a surface of the semiconductor substrate; A nonvolatile memory device comprising a formed select gate electrode. 11. The nonvolatile memory device according to claim 7, wherein a buffer dielectric film formed on a surface of the semiconductor substrate is provided in the gate region of the select transistor; A nonvolatile memory device comprising: a high dielectric film formed thereon; and a select gate electrode formed on the high dielectric film. 12. The nonvolatile memory device according to claim 7, wherein a gate insulating film formed on a surface of the semiconductor substrate and a gate insulating film formed on the gate insulating film in the gate region of the select transistor. A floating gate electrode, a high dielectric film formed on the floating gate electrode, and a select gate electrode formed on the high dielectric film. 13. The nonvolatile memory device according to claim 7, wherein the gate region of the select transistor includes a gate insulating film formed on a surface of the semiconductor substrate, and a gate insulating film formed on the gate insulating film. A nonvolatile memory device comprising: a formed select gate electrode; an insulating film formed on the select gate electrode; and an additional gate electrode formed on the insulating film. 14. The nonvolatile memory device according to claim 13, wherein said additional gate electrode is in an electrically floating state. 15. The nonvolatile memory device according to claim 13, wherein a predetermined constant voltage is supplied to said additional gate electrode. 16. The nonvolatile memory device according to claim 13, wherein said additional gate electrode is electrically connected to said select gate electrode. 17. A method for manufacturing a nonvolatile memory device including a memory cell having a ferroelectric gate type memory transistor and a select transistor connected to the memory transistor, comprising: a first conductive type semiconductor substrate; In the layer, a first second conductivity type impurity diffusion region and a second second conductivity type impurity diffusion region are formed at an interval, and the first second conductivity type impurity diffusion region and the first Forming a gate region of the selection transistor above the second diffusion region of the second conductivity type; and forming an interlayer insulating film covering the surface of the semiconductor substrate and the gate region of the selection transistor; Forming a trench in the interlayer insulating film;
Exposing a part of the conductive type impurity diffusion region; and ion-implanting the first conductive type impurity through the trench, and then performing a heat treatment for activating the first conductive type impurity. Forming a first conductivity type impurity diffusion region below the trench; and forming a gate region of the memory transistor along a side surface of the trench and a bottom surface of the trench. Of manufacturing a nonvolatile memory device. 18. A method of manufacturing a nonvolatile memory device including a memory cell having a ferroelectric gate type memory transistor and a high dielectric gate type select transistor connected to the memory transistor, comprising the steps of: Forming a second conductivity type impurity diffusion region in a surface layer of a semiconductor substrate of a mold type; forming an interlayer insulating film covering a surface of the semiconductor substrate; forming a first trench in the interlayer insulating film And the second
A step of exposing a part of the impurity diffusion region of the conductivity type, and a heat treatment for activating the impurity of the first conductivity type after ion-implanting the impurity of the first conductivity type through the first trench. Forming a first first-conductivity-type impurity diffusion region below the first trench; and forming a second trench in the interlayer insulating film at a location different from the first trench. Exposing a portion of the second conductivity type impurity diffusion region; and ion-implanting the first conductivity type impurity through the second trench, and then activating the first conductivity type impurity. Forming a second first-conductivity-type impurity diffusion region below the second trench by performing a heat treatment for forming a second conductive impurity diffusion region below the second trench. Along the selection transistor Forming a gate region of the memory transistor along a side surface of the first trench and a bottom surface of the first trench. A method for manufacturing a nonvolatile memory device.