JP2002270610A - Method of manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a technique which can prevent polishing remainder of copper, by reducing the swell of the copper in a plating growth operation in a dual-damascene process. SOLUTION: By an electrolytic plating method, a copper-plated layer is formed over the whole face of a semiconductor substrate, including the inside of a wiring groove and a connecting hole. At this time, when it is subjected to electrolytic plating so as to be divided into two or more operations, swelling of the copper generated on the wiring groove is reduced, and the polishing remainder of the copper in subsequent CMP processes is prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device manufacturing technique, and more particularly, to a dual damascen.
e) A technology effective when applied to a semiconductor device having wiring.

[0002]

2. Description of the Related Art In a dual damascene method, after a wiring metal having copper as a main conductor layer is formed on the entire surface of a semiconductor substrate including the inside of a wiring groove and a connection hole formed in an insulating layer, a wiring metal other than the wiring groove and the connection hole is formed. Of copper in the area of chemical mechani
This is a method in which a wiring is formed inside the wiring groove by removing using a cal polishing method, and at the same time, a connection member formed integrally with the wiring is buried inside the connection hole.

The copper constituting the main conductor layer of the wiring can be simultaneously buried in the wiring groove and the connection hole by electrolytic plating after forming a copper seed layer on the entire surface of the semiconductor substrate by sputtering, for example.

A dual damascene using an electrolytic plating method for forming copper constituting a main conductor layer of a wiring,
For example, the press journal "Semiconductor World", published in December 1997
It is described in FIG.

[0005]

In order to make it possible to uniformly bury copper in wiring grooves and connection holes with a high aspect ratio, a plating solution used in electrolytic plating contains an additive. Examples of the additive include a first component having a function of suppressing plating growth, a second component having a function of promoting plating growth, and a third component having a function of suppressing growth of corners of an opening. By selectively using these components, it is possible to preferentially grow the plating from the bottom of the connection hole without closing the opening. In other words, by relatively reducing the size of the molecules constituting the second component, the second component is collected at the bottom of the connection hole to promote plating growth, and is preferentially placed inside the wiring groove and the connection hole. Copper is embedded.

However, the present inventor has studied and found that copper buried in the wiring groove and the connection hole rises on the wiring groove, and as a result, the copper formed on the entire surface of the semiconductor substrate is removed by the CMP method. It became clear that polishing residue of copper was generated in the polishing step.

An object of the present invention is to provide a technique capable of reducing the swelling of copper in plating growth in a dual damascene process and preventing the unpolished copper.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0009]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

According to the present invention, electrolytic plating is performed twice or more,
A plating layer forming a main conductor layer of the wiring is formed on the entire surface of the semiconductor substrate including the inside of the wiring groove and the connection hole forming the dual damascene.

[0011]

Embodiments of the present invention will be described below in detail with reference to the drawings. In all the drawings for describing the embodiments, members having the same functions are denoted by the same reference numerals, and the repeated description thereof will be omitted.

A procedure of an electrolytic plating method according to an embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a schematic diagram showing a plating apparatus used for the electrolytic plating method, FIG. 2 is a process diagram showing a procedure of the electrolytic plating method, FIG. 3 is a layout view of a semiconductor substrate in the plating apparatus, and FIG. FIG. 4 is a cross-sectional view of a main part of a semiconductor substrate showing copper grown by a plating method.

As shown in FIG. 1, a plating apparatus 1 includes a plating solution 2 and electrodes (a cathode electrode 3a, an anode electrode 3).
b), constituted by the semiconductor substrate 4. The plating solution 2 is usually a solution (eg, CuSO
₄ ), an auxiliary electrolytic solution for obtaining the conductivity of the solution, and an additive, and the plating solution 2 stored in the plating tank 5 is introduced into the cell 7 of the plating apparatus 1 using the pump 6. You. In the drawing, the flow of the plating solution 2 is indicated by arrows.
The cathode electrode 3a is installed on the upper part of the plating apparatus 1, and the anode electrode 3b is installed on the lower part of the plating apparatus 1.

The formation of the copper plating layer by the electrolytic plating method is performed, for example, as follows. First, the semiconductor substrate 4 is placed on the cathode electrode 3a of the plating apparatus 1 with the surface on which the plating layer is to be formed facing downward (Step 10 in FIG. 2).
0). Although not shown, an insulating layer in which wiring grooves and connection holes are formed is provided on the semiconductor substrate 4, and further on the insulating layer including the inside of the wiring grooves and connection holes,
A seed layer is formed by a directional sputtering method.
Further, as shown in FIG. 3A, the semiconductor substrate 4 has the notch 8 arranged in a certain direction, for example, facing the front panel side of the plating apparatus.

Next, after introducing the plating solution 2 into the cell 7 and filling the inside of the cell 7 with the plating solution 2 (step 101 in FIG. 2),
An electric current flows through the cathode electrode 3a on which the semiconductor substrate 4 is installed as a negative electrode and the anode electrode 3b as a positive electrode,
The first electrolytic plating is performed. Thereby, the copper ions generated in the plating solution 2 are attracted to the cathode electrode 3a, and the growth of copper starts using the seed layer as a seed. By performing the first electrolytic plating for about 1 to 2 minutes, the first electrolytic plating is performed on the flat surface of the substrate.
A copper plating layer having a thickness of about 2 to 0.4 μm can be formed on the seed layer (step 102 in FIG. 2). A direct current having a current density of 1.0 A / cm ² can be used as the current flowing during plating growth.

As shown in FIG. 4A, the insulating layer 9 formed on the semiconductor substrate 4 is formed by the first electrolytic plating.
For example, a groove 10 having a depth of about 1 μm and a width of about 0.25 μm
Can be completely embedded with the copper plating layer 11a. However, it is not possible to completely prevent the copper plating layer 11a from rising on the groove 10 due to a component having a function of promoting plating growth. As the plating time becomes longer, the bulge becomes remarkable, so that the first electrolytic plating is completed when copper is buried in all of the plurality of grooves 10 formed in the insulating layer 9 and the plating layer 11a It is desirable to minimize the excitement of

Next, the semiconductor substrate 4 is taken out of the plating apparatus 1, and thereafter, the semiconductor substrate 4 is subjected to a washing process (step 103 in FIG. 2), and subsequently a drying process (step 104 in FIG. 2).

Next, in order to change the contact position between the semiconductor substrate 4 and the cathode electrode 3a of the plating apparatus 1, for example, as shown in FIG. 3B, the arrangement shown in FIG. Rotating the semiconductor substrate 4 by 180 degrees, or FIG.
As shown in FIG. 2C, the semiconductor substrate 4 is rotated by 90 degrees with respect to the arrangement shown in FIG.
5). Note that, without rotating the semiconductor substrate 4,
The arrangement may be the same as the arrangement shown in FIG.

Next, the cathode electrode 3a of the plating apparatus 1
After the semiconductor substrate 4 is installed (step 106 in FIG. 2), a second electrolytic plating is performed in the same manner as the first electrolytic plating (step 107 in FIG. 2). By performing the second electroplating for about 1 to 2 minutes, 0.2 to 0.4 μm on the copper plating layer formed by the first electroplating on the substrate plane.
It is possible to form a copper plating layer having a thickness of about one. As the current flowing during plating growth, a DC current having a current density of 1.0 A / cm ² can be used as in the first electrolytic plating.

As shown in FIG. 4B, a copper plating layer 11b is further formed on the plating layer 11a formed by the first electrolytic plating by the second electrolytic plating.
However, in the second electrolytic plating, the swelling of the copper plating layer 11b on the groove 10 by the additive having a function of promoting the growth of plating hardly occurs.

Next, the semiconductor substrate 4 is taken out of the plating apparatus 1, and thereafter, the semiconductor substrate 4 is subjected to a water-washing process (step 108 in FIG. 2) and subsequently a drying process (step 109 in FIG. 2).

The washing and drying treatments were performed after the first electrolytic plating and after the second electrolytic plating, respectively, as shown in the steps indicated by the dotted arrows in FIG. Alternatively, electrolytic plating and rinsing may be performed twice consecutively, followed by drying. Alternatively, electrolytic plating may be performed twice consecutively, followed by rinsing and drying.

Table 1 summarizes the thickness of the copper plating layer grown by electrolytic plating, the thickness uniformity (1σ), and the swelling thickness. The thickness of each copper plating layer in the first and second electrolytic plating is the thickness on the substrate plane, and the thickness of the swelling of the plating layer is the difference between the thickness on the substrate plane and the thickness on the groove. It is. The evaluation sample had an aspect ratio of about 1 μm and a width of about 0.25 μm.
An 8-inch semiconductor wafer having a plurality of grooves formed in an insulating layer was used.

[0024]

[Table 1]

The sample (No. 2 to No. 8) in which the plating layer was formed by two times of electrolytic plating was compared with the sample (No. 1) in which the plating layer was formed by one time of electrolytic plating. It can be seen that the uniformity of the thickness of the layer is improved and the rise of the plating layer is reduced to about half. Further, the samples (Nos. 3, 5) in which the contact position between the semiconductor substrate and the cathode electrode in the first electrolytic plating and the contact position between the semiconductor substrate and the cathode electrode in the second electrolytic plating were changed. , 6, 8), the uniformity of the thickness of the plating layer is improved as compared with the samples (No. 2, 4, 7) in which the plating layer is formed without changing the contact position.

Next, an example of a method of manufacturing a semiconductor device according to an embodiment of the present invention will be described in the order of steps with reference to the cross-sectional views of essential parts of a semiconductor substrate shown in FIGS.

First, as shown in FIG. 5, a semiconductor substrate 21 made of, for example, p ^- type single crystal silicon is prepared, and an element isolation region 22 is formed on the main surface of the semiconductor substrate 21.
Next, impurities are ion-implanted using the patterned photoresist film as a mask to form a p-well 23 and an n-well 24. An impurity having a p-type conductivity, for example, boron (B) is ion-implanted into the p-well 23, and an impurity having an n-type conductivity, for example, phosphorus (P) is ion-implanted into the n-well 24. Thereafter, MI is added to each well region.
SFET (metal insulator semiconductor field effe
An impurity for controlling the threshold value of the ct transistor may be ion-implanted.

Next, a silicon oxide film serving as the gate insulating film 25, a polycrystalline silicon film serving as the gate electrode 26, and a silicon oxide film serving as the cap insulating film 27 are sequentially deposited to form a laminated film. The laminated film is etched using the resist film as a mask. Thus, a gate insulating film 25, a gate electrode 26, and a cap insulating film 27 are formed. The gate insulating film 25 can be formed by, for example, a thermal CVD method, and the gate electrode 26
Can be formed by, for example, a CVD method.

Next, for example, a CV
After a silicon oxide film is deposited by the method D, the silicon oxide film is anisotropically etched to form the gate electrode 26.
Is formed on the side wall of the substrate. Thereafter, using the photoresist film as a mask, an n-type impurity (for example, phosphorus or arsenic (As)) is ion-implanted into the p-well 23 to form an n-type semiconductor region 29 on both sides of the gate electrode 26 on the p-well 23. The n-type semiconductor region 29 is formed in a self-aligned manner with respect to the gate electrode 26 and the sidewall spacer 28, and functions as a source and a drain of the n-channel MISFET. Similarly, using the photoresist film as a mask, p-type impurities (for example, boron fluoride (BF ₂ )) are ion-implanted into n-well 24 to form p-type semiconductor regions 30 on both sides of gate electrode 26 on n-well 24. I do. The p-type semiconductor region 30 is formed in a self-aligned manner with respect to the gate electrode 26 and the sidewall spacer 28, and functions as a source and a drain of the p-channel MISFET.

Next, as shown in FIG.
After a silicon oxide film is deposited thereon by a sputtering method or a CVD method, the silicon oxide film is polished by, for example, a CMP method, so that the surface of the interlayer insulating film 31 is planarized.
To form

Next, a connection hole 32 is formed in the interlayer insulating film 31 by etching using the patterned photoresist film as a mask. The connection hole 32 is formed in a necessary portion on the n-type semiconductor region 29 or the p-type semiconductor region 30 or the like.

Next, a titanium nitride film is formed on the entire surface of the semiconductor substrate 21 including the inside of the connection hole 32 by, for example, a CVD method, and a tungsten film for filling the connection hole 32 is formed by, for example, a CVD method. Thereafter, the titanium nitride film and the tungsten film in the region other than the connection hole 32 are removed by, for example, a CMP method, and the plug 33 is inserted into the connection hole 32.
To form

Subsequently, the interlayer insulating film 31 and the plug 33
A stopper insulating film 34 is formed thereon, and further an insulating film 35 for forming a wiring is formed. The stopper insulating film 34 is a film serving as an etching stopper when a groove is formed in the insulating film 35, and is made of a material having an etching selectivity with respect to the insulating film 35. The stopper insulating film 34 is, for example, a silicon nitride film, and the insulating film 35 is, for example, a silicon oxide film. Note that a first wiring layer described below is formed on the stopper insulating film 34 and the insulating film 35. Therefore, the total film thickness is determined by the design film thickness required for the first wiring layer. In consideration of reducing the wiring capacitance, the stopper insulating film 3 made of a silicon nitride film having a relatively high relative dielectric constant is used.
The film thickness of 4 is desirably as thin as possible if it is a film thickness sufficient to achieve the stopper function. Next, a wiring groove 36 is formed in a predetermined region of the stopper insulating film 34 and the insulating film 35 by etching using the patterned photoresist film as a mask.

Next, the wiring 37 of the first wiring layer is formed inside the wiring groove 36. First, for example, a tungsten film is formed on the entire surface of the semiconductor substrate 21 including the inside of the wiring groove 36. For example, a CVD method is used to form the tungsten film. After that, the tungsten film in the region other than the wiring groove 36 is removed by, for example, the CMP method to form the wiring 37 of the first wiring layer.

Next, a third wiring layer is formed by a dual damascene method. First, as shown in FIG. 7, a cap insulating film 38, an interlayer insulating film 39, and a stopper insulating film 40 for forming a wiring are sequentially formed on the insulating film 35 and the wiring 37 of the first wiring layer.

Cap insulating film 38 and interlayer insulating film 39
Is formed with a connection hole as described later. The cap insulating film 38 is made of a material having an etching selectivity with respect to the interlayer insulating film 39, and may be, for example, a silicon nitride film. The silicon nitride film is formed by, for example, a plasma CVD method, and its thickness can be, for example, about 50 nm.

The interlayer insulating film 39 is made of, for example, a silicon oxide film, and its thickness can be, for example, about 450 nm. The silicon oxide film is, for example, TE
OS (tetra ethyl ortho silicate: Si (OC
Plasma CV using ₂ H ₅ )) and ozone as source gas
It is composed of a TEOS oxide film formed by the D method.

The stopper insulating film 40 is made of an insulating material having an etching selectivity with respect to the interlayer insulating film 39 and an insulating film for wiring formation deposited later on the stopper insulating film 40. can do. The silicon nitride film is formed by, for example, a plasma CVD method, and its thickness can be, for example, about 50 nm.

Next, a photoresist film 41 patterned into a hole pattern is formed on the stopper insulating film 40,
Using the photoresist film 41 as a mask, the stopper insulating film 40 is etched by, for example, a dry etching method.

Next, as shown in FIG. 8, after removing the photoresist film 41, an insulating film 42 for forming a wiring is formed on the stopper insulating film 40. The insulating film 42 is made of, for example, a silicon oxide film and has a thickness of, for example, 400
nm. The silicon oxide film,
For example, it is composed of a TEOS oxide film formed by a plasma CVD method using TEOS and ozone as a source gas. Note that a wiring groove in which a second wiring layer described below is buried is formed in the stopper insulating film 40 and the insulating film 42, and the total film thickness is determined by a design film thickness required for the second wiring layer.

Next, as shown in FIG. 9, a photoresist film 43 patterned into a groove pattern is formed on the insulating film 42, and the photoresist film 43 is used as a mask.
For example, the insulating film 42 is etched by a dry etching method. At this time, the stopper insulating film 40 functions as an etching stopper layer.

Subsequently, as shown in FIG. 10, the stopper insulating film 40 and the photoresist film 43 are used as masks.
For example, the interlayer insulating film 39 is etched by a dry etching method. At this time, the cap insulating film 38 functions as an etching stopper layer.

Next, after removing the photoresist film 43, the exposed cap insulating film 38 is removed by, for example, a dry etching method. At the same time as the cap insulating film 38 is removed, the stopper insulating film 40 is also removed.
As shown in FIG. 3, the cap insulating film 38 and the interlayer insulating film 3
9, a connection hole 44 is formed, and a wiring groove 45 is formed in the stopper insulating film 40 and the insulating film 42.

Next, a wiring of the second wiring layer is formed inside the connection hole 44 and the wiring groove 45. The wiring of the second wiring layer is
A connection member that is made of a barrier metal layer and a copper film that is a main conductive layer and that connects this wiring and the wiring 37 of the first wiring layer that is the lower wiring is formed integrally with the wiring of the second wiring layer.
The method of forming the wiring of the second wiring layer is performed, for example, as follows.

First, as shown in FIG. 12, a barrier metal layer 46 is formed on the entire surface of the semiconductor substrate 21 including the insides of the connection holes 44 and the wiring grooves 45. The barrier metal layer 46
For example, it is made of a tantalum film, and its thickness can be, for example, about 50 nm on the substrate plane. The tantalum film is formed by, for example, a sputtering method. The barrier metal layer 46 may be made of titanium nitride, tantalum nitride, or the like.

Next, as shown in FIG. 13, a copper seed layer 47 is formed on the barrier metal layer 46. Seed layer 47
Is formed by, for example, a CVD method or a sputtering method, and its film thickness is, for example, about 100 nm on a substrate plane.

Next, as shown in FIG. 14, the seed layer 47 is formed by the electrolytic plating method described with reference to FIGS.
A copper plating layer 48a is formed thereon. The thickness of the plating layer 48a is, for example, about 600 nm on the substrate plane.
Thereby, the connection hole 44 and the wiring groove 45 are buried at the same time, and the swelling of the plating layer 48 a on the wiring groove 45 can be suppressed.

Next, as shown in FIG. 15, the plating layer 48a and the seed layer 47 are polished by the CMP method. Since the polishing rate of copper is high, the copper portion is removed first. Further, polishing is continued, and the barrier metal layer 46 on the insulating film 42 is also removed. Thereby, the copper film (plating layer 48a and seed layer 47) and the barrier metal layer 46 in the region other than the wiring groove 45 are removed, and the wiring 48 formed integrally with the connection member is formed.

Thereafter, although not shown, a further upper layer wiring is formed, and the entire surface of the semiconductor substrate 21 is covered with a passivation film, whereby the semiconductor device is substantially completed.

As described above, according to the present embodiment, the electrolytic plating is performed twice to form the copper plating layer, so that the wiring groove of the dual damascene structure formed in the insulating layer on the semiconductor substrate is formed. The rise of copper can be reduced as compared with a single electrolytic plating. Thereby, it is possible to prevent the unpolished copper from remaining in the polishing process performed on the copper plating layer by the CMP method.

Although the invention made by the inventor has been specifically described based on the embodiments of the present invention, the present invention is not limited to the above embodiments, and various modifications may be made without departing from the gist of the invention. Needless to say, it can be changed.

For example, in the above-described embodiment, the number of times of electrolytic plating is set to two times. However, the number of times of electrolytic plating is not limited to this.

[0053]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

It is possible to reduce the swelling of copper during the plating growth in the dual damascene process and prevent the unpolished copper.

[Brief description of the drawings]

FIG. 1 is a schematic diagram showing a plating apparatus used for an electrolytic plating method according to an embodiment of the present invention.

FIG. 2 is a process chart showing a procedure of an electrolytic plating method according to an embodiment of the present invention.

FIG. 3 is a layout view of a semiconductor substrate in a plating apparatus according to an embodiment of the present invention.

FIG. 4 is a cross-sectional view of a main part of a semiconductor substrate showing copper grown by an electrolytic plating method according to an embodiment of the present invention.

FIG. 5 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor device according to one embodiment of the present invention;

FIG. 6 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor device according to one embodiment of the present invention;

FIG. 7 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor device according to one embodiment of the present invention;

FIG. 8 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor device according to one embodiment of the present invention;

FIG. 9 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor device according to one embodiment of the present invention;

FIG. 10 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor device according to one embodiment of the present invention;

FIG. 11 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor device according to one embodiment of the present invention;

FIG. 12 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor device according to one embodiment of the present invention;

FIG. 13 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor device according to one embodiment of the present invention;

FIG. 14 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor device according to one embodiment of the present invention;

FIG. 15 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor device according to one embodiment of the present invention;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Plating apparatus 2 Plating solution 3a Cathode electrode 3b Anode electrode 4 Semiconductor substrate 5 Plating tank 6 Pump 7 Cell 8 Notch 9 Insulation tank 10 Groove 11a Plating layer 11b Plating layer 21 Semiconductor substrate 22 Element isolation region 23 p-well 24 n-well 25 gate Insulating film 26 gate electrode 27 cap insulating film 28 sidewall spacer 29 n-type semiconductor region 30 p-type semiconductor region 31 interlayer insulating film 32 connection hole 33 plug 34 stopper insulating film 35 insulating film 36 wiring groove 37 wiring 38 cap insulating film 39 interlayer Insulating film 40 Stopper insulating film 41 Photoresist film 42 Insulating film 43 Photoresist film 44 Connection hole 45 Wiring groove 46 Barrier metal layer 47 Seed layer 48a Plating layer 48 Wiring

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Kazuya Kawakami 6-chome, Shinmachi, Ome-shi, Tokyo 3 Inside the Device Development Center, Hitachi, Ltd. (72) Inventor Akira Sato 5-chome, Josuihoncho, Kodaira-shi, Tokyo No. 22 No. 1 F-term (reference) in Hitachi Super-LSI Systems, Ltd. 4K024 AA09 AB02 BA15 BB12 BC10 CA02 CA06 CB08 CB26 GA16 4M104 AA01 BB04 DD52 HH12 5F033 HH11 HH19 HH21 HH32 HH33 JJ01 JJ19 JJ19 JJ19 JJ19 JJ19 JJ19 JJ33 KK01 KK19 MM01 MM02 MM12 MM13 NN06 NN07 PP06 PP15 PP27 QQ09 QQ25 QQ35 QQ37 QQ48 RR04 RR06 SS04 SS08 SS11 SS15 TT02 XX01

Claims (5)

[Claims] 1. A plating layer forming a main conductor layer of a wiring is formed on an entire surface of a semiconductor substrate including a wiring groove and a connection hole forming a dual damascene by performing electrolytic plating twice or more. Manufacturing method of a semiconductor device. 2. A semiconductor device according to claim 1, wherein electroplating is performed twice or more to form a plating layer forming a main conductor layer of the wiring on the entire surface of the semiconductor substrate including the inside of the wiring groove and the connection hole forming the dual damascene. A method of manufacturing a semiconductor device, comprising: sequentially performing electrolytic plating, a washing process, and a drying process two or more times. 3. A semiconductor device in which electrolytic plating is performed two or more times to form a plating layer constituting a main conductor layer of a wiring on the entire surface of a semiconductor substrate including wiring grooves and connection holes constituting a dual damascene. A method for manufacturing a semiconductor device, comprising: performing electrolytic plating and rinsing treatment twice or more sequentially, and then performing drying treatment. 4. A semiconductor device in which a plating layer constituting a main conductor layer of a wiring is formed on an entire surface of a semiconductor substrate including wiring grooves and connection holes constituting a dual damascene by performing electrolytic plating twice or more. A method for manufacturing a semiconductor device, comprising: performing electrolytic plating twice or more, and then sequentially performing a water washing process and a drying process. 5. A semiconductor device in which electrolytic plating is performed twice or more to form a plating layer forming a main conductor layer of a wiring on the entire surface of a semiconductor substrate including wiring grooves and connection holes forming a dual damascene. A method of manufacturing a semiconductor device, comprising: changing a contact position between the semiconductor substrate and a cathode electrode of a plating apparatus for each electrolytic plating.