JP2002009146A - Method for manufacturing semiconductor integrated circuit device, and semiconductor integrated cuircuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent an electromigration of copper in an interface between a plug and a lower layer wiring that are manufactured in a wiring forming process by using a damascene method. SOLUTION: A buried wiring 23 which forms a junction hole 25a, is formed with the pattern enlarged in the length direction, and thus a margin in the neighborhood of the junction part between the junction hole 25a and the buried wiring 23 is enlarged.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device and a manufacturing technique thereof, and more particularly, to a semiconductor integrated circuit device in which a conductive film filling a trench formed in an insulating film is a copper film. It is about effective technology.

[0002]

2. Description of the Related Art As a method of forming wiring of a semiconductor integrated circuit,
There is a process called the Damascene method.
According to this method, after a wiring groove or a connection hole is formed in an insulating film, a conductive film for forming a wiring or a plug is deposited on the main surface of the semiconductor substrate, and further, a region other than the wiring groove or the connection hole is formed. The conductive film is chemically and mechanically polished (CMP; Ch
This is a method of forming a buried wiring in a wiring groove or a plug in a connection hole by removing the wiring by emical mechanical polishing. This method is particularly suitable as a method for forming an embedded wiring made of a copper-based conductor material (copper or copper alloy), which is difficult to perform fine etching.

[0003] As an application of the damascene method, there is a dual-damascene method. According to this method, after forming a groove for forming a wiring and a connection hole for making a connection with a lower layer wiring in an insulating film, a conductive film for forming a wiring is deposited on a main surface of the semiconductor substrate, and the groove is further formed. By removing the conductive film in a region other than the region by CMP, a buried wiring is formed in a wiring forming groove and a plug is formed in a connection hole. In the case of this method, particularly in a semiconductor integrated circuit having a multilayer wiring structure, the number of steps can be reduced, and the wiring cost can be reduced.

A technique for forming a wiring using such a damascene method is disclosed in, for example, Japanese Patent Application Laid-Open No. 10-135153.
In the publication, after forming a wiring groove in an insulating film, a barrier conductor film is formed inside the wiring groove by a sputtering method or a C method.
It is deposited by a VD method, and copper, silver, gold or an alloy thereof is buried in a wiring groove by a sputtering method or a CVD method.
There is a description of a method of forming a wiring by removing excess copper, silver, gold or an alloy thereof outside a wiring groove by polishing using a polishing method.

[0005]

In the embedded wiring technique, the following problems occur when the margin between the lower wiring and the plug connecting the lower wiring and the upper wiring is small.

That is, if the margin of the lower wiring to which the plug is connected is small, the frequency of collision of electrons and copper atoms due to the electric field concentration at the interface between the plug and the lower wiring increases, and the copper atoms move. By becoming easier,
There is a problem that voids are generated at the interface due to electromigration. In particular, when the plug and the lower wiring are out of alignment, the tendency for copper atoms to move easily becomes significant.

In the case where the plug and the lower wiring are separated from each other, the area of the contact portion between the plug and the lower wiring is reduced. Therefore, there is a problem that the resistance value at the interface between the plug and the lower wiring increases. Further, when the resistance value at the interface between the plug and the lower wiring increases, the wiring may be melted off due to Joule heat generated at the interface.

SUMMARY OF THE INVENTION An object of the present invention is to provide a technique for improving an unsightly margin between a lower wiring and a plug connecting the lower wiring and the upper wiring.

Another object of the present invention is to provide a technique for preventing generation of voids due to electromigration at an interface between a plug and a lower wiring.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0011]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

That is, the present invention provides a process of forming a wiring groove by etching a first insulating film deposited on a main surface of a semiconductor substrate, and an upper part of the first insulating film including an inside of the wiring groove. Depositing a first conductive film in the wiring groove, and chemically and mechanically polishing the first conductive film outside the wiring groove to leave the first conductive film in the wiring groove. Forming a first wiring, depositing a second insulating film on the first insulating film and the first wiring, and etching the second insulating film to reach the first wiring. Forming one connection hole, wherein the first wiring is formed by enlarging at least one of a length direction and a width direction at an interface with the first connection hole.

Further, the present invention provides a method of forming a wiring groove by etching a first insulating film deposited on a main surface of a semiconductor substrate;
Depositing a first conductive film on top of an insulating film; and chemically and mechanically polishing the first conductive film outside the wiring groove to form the first conductive film in the wiring groove. Forming a first wiring, depositing a second insulating film over the first insulating film and the first wiring, and etching the first insulating film by etching the second insulating film. Forming a first connection hole reaching the wiring,
The first wiring and the plug formed in the first connection hole contain copper as a main component.

Further, according to the present invention, a first insulating film is deposited on a main surface of a semiconductor substrate, and the first conductive film is formed by embedding a first conductive film in a wiring groove formed in a part of the first insulating film. And a first connection hole formed in a part of the first insulation film and a second insulation film deposited on the first wiring, wherein the first connection hole is formed by the first connection hole. At least one of the first wiring is expanded in the length direction and the width direction at the interface with the first connection hole.

According to the present invention, in the vicinity of the connection between the plug formed in the first connection hole and the first wiring, the first wiring is enlarged in at least one of its length direction and width direction. Therefore, disconnection when connecting the plug to the first wiring can be prevented.

Further, according to the present invention described above, since the uncovered margin of the first wiring, which is the lower wiring that drops the first connection hole, is increased, the first wiring is formed in the first wiring and the first connection hole. Electromigration of copper constituting the plug can be prevented.

Further, according to the present invention, since the contact area between the plug formed in the first connection hole and the first wiring can be increased, the connection area between the plug and the first wiring can be increased. The generation of Joule heat can be prevented.

Further, according to the present invention, since the generation of Joule heat at the connection between the plug formed in the first connection hole and the first wiring can be prevented, the plug caused by the Joule heat can be prevented. Electromigration of copper at the interface between the metal and the first wiring can be prevented.

[0019]

Embodiments of the present invention will be described below in detail with reference to the drawings. In all the drawings for describing the embodiments, members having the same functions are denoted by the same reference numerals, and the repeated description thereof will be omitted.

(Embodiment 1) In Embodiment 1, for example, an n-channel MISFE is formed in a p-type well of a semiconductor substrate.
T (Metal Insulator Semiconductor Field Effect Tra
The present invention is applied to a method for manufacturing a semiconductor integrated circuit device on which a Qn is formed.

Hereinafter, a method of manufacturing the above-described semiconductor integrated circuit device will be described in the order of steps with reference to FIGS.

First, as shown in FIG.
semiconductor substrate 1 made of single-crystal silicon
A heat treatment is performed at about 0 ° C. to form a thin silicon oxide film (pad oxide film) having a thickness of about 10 nm on the main surface, and then a silicon nitride film having a thickness of about 120 nm is formed on the silicon oxide film by CVD (Chemical). After deposition by a vapor deposition method, the silicon nitride film and the silicon oxide film in the element isolation region are removed by dry etching using a photoresist film as a mask. The silicon oxide film is formed for the purpose of relieving stress applied to the substrate when densifying (burning) the silicon oxide film embedded in the element isolation trench in a later step. In addition, since the silicon nitride film has the property of being hardly oxidized, the lower portion (active region)
Is used as a mask to prevent oxidation of the substrate surface.

Subsequently, the semiconductor substrate 1 in the element isolation region has a depth of 3 by dry etching using a silicon nitride film as a mask.
After forming a groove of about 50 nm, the semiconductor substrate 1 is heat-treated at about 1000 ° C. to remove a damaged layer formed on the inner wall of the groove by etching, and a thin silicon oxide film 4 of about 10 nm thickness is formed on the inner wall of the groove. To form

Subsequently, a film thickness of 380 nm is formed on the semiconductor substrate 1.
A silicon oxide film 5 is deposited by a CVD method, and then the semiconductor substrate 1 is formed in order to improve the film quality of the silicon oxide film 5.
Is heat-treated to densify (bake) the silicon oxide film 5. Thereafter, chemical mechanical polishing (C) using the silicon nitride film as a stopper is performed.
The silicon oxide film 5 is polished by the MP) method and is left inside the groove, thereby forming the element isolation groove 6 having a flattened surface.

Subsequently, after the silicon nitride film remaining on the active region of the semiconductor substrate 1 is removed by wet etching using hot phosphoric acid, the n-channel MISF of the semiconductor substrate 1 is removed.
B (boron) is ion-implanted into the region where
A mold well 7 is formed.

Subsequently, after the silicon oxide film of the p-type well 7 is removed using a HF (hydrofluoric acid) -based cleaning solution, the semiconductor substrate 1 is wet-oxidized to form a film having a thickness of 3.5 nm on the surface of the p-type well 7. A relatively clean gate oxide film 9 is formed.

Next, a film having a thickness of 90-100
A non-doped polycrystalline silicon film of about nm is deposited by a CVD method. Subsequently, using a mask for ion implantation, for example, P (phosphorus) is ion-implanted into the non-doped polycrystalline silicon film on the p-type well 7 to form an n-type polycrystalline silicon film. Further, a silicon oxide film is deposited on the surface of the n-type polycrystalline silicon film to form a laminated film, and the laminated film is etched using a resist patterned by photolithography as a mask to form a gate electrode 10 and a cap insulating film 11a. To form Incidentally, the upper portion of the gate electrode _{10 WSi x, MoSi x, TiSi} x, TaS
a refractory metal silicide film such as i _x or CoSi _x may be laminated. The cap insulating film 11a is made of, for example, CV
It can be formed by Method D.

Next, after removing the photoresist film used for processing the gate electrode 10, an n-type impurity, for example, P (phosphorus) is ion-implanted into the p-type well 7 to form the gate electrode 1.
The n ⁻ -type semiconductor region 12 is formed in the p-type well 7 on both sides of “0”.

Next, a silicon oxide film having a thickness of about 100 nm is deposited on the semiconductor substrate 1 by a CVD method, and the silicon oxide film is anisotropically etched by a reactive ion etching (RIE) method. n-channel MIS
A sidewall spacer 11b is formed on the side wall of the gate electrode 10 of the FET. Subsequently, an n-type impurity, for example, As (arsenic) is ion-implanted into the p-type well 7 to form an n ⁺ -type semiconductor region 13 (source, drain) of the n-channel MISFET. Thereby, the n-channel type MISFE
Source and drain regions having an LDD (Lightly Doped Drain) structure are formed in TQn, and an n-channel MISFE is formed.
TQn is completed.

Next, after a silicon oxide film is deposited on the semiconductor substrate 1 by the CVD method, for example, the silicon oxide film is
By polishing by the P method, the insulating film 14 whose surface is flattened is formed. Furthermore, n of the main surface of the semiconductor substrate 1
^A connection hole 15 is formed in the insulating film 14 on the ⁺ type semiconductor region 13 by using a photolithography technique.

Next, a barrier conductor film 16 made of, for example, titanium nitride is formed on the semiconductor substrate 1 by sputtering.
Then, a conductive film 16b of, for example, tungsten is deposited by blanket CVD.

Next, the barrier conductor film 16a and the conductive film 16b on the insulating film 14 other than the connection holes 15 are formed, for example, by CM.
The plug 16 is removed by the P method.

Next, a silicon nitride film is deposited on the semiconductor substrate 1 by, for example, a plasma CVD method to a thickness of about 10
An etch stopper film (first insulating film) 17 of 0 nm is formed. The etch stopper film 17 is used to prevent the lower layer from being damaged by excessive excavation and to prevent the processing dimensional accuracy from deteriorating when a trench or a hole for forming a wiring is formed in the insulating film on the upper layer. Things.

Next, as shown in FIG. 2, for example, a silicon oxide film is deposited on the surface of the etch stopper film 17 by a CVD method, and an insulating film (first insulating film) 18 having a thickness of about 400 nm is formed.
Is deposited. The insulating film 18 is made of a SOG (Spin On Glass) film deposited by a coating method, and a CVD to which fluorine is added.
It may be a low dielectric constant film such as an oxide film, a silicon nitride film, or a combination of a plurality of types of insulating films. When a low dielectric constant film is used, the wiring of a semiconductor integrated circuit device may be reduced. It is possible to lower the overall dielectric constant,
Wiring delay can be improved.

Next, as shown in FIG. 3, the etch stopper film 17 and the insulating film 18 are processed by using the photolithography technique and the dry etching technique to form the wiring groove 19.
To form The width of the wiring groove 19 is, for example, about 0.5.
The depth can be, for example, about 0.25 μm to about 0.5 μm.
At this time, the wiring groove 19 is designed so as to have a structure enlarged in the length direction of the wiring in order to take a margin for unsightly contact with a connection hole 25a described later. This will be described later in detail with reference to FIG.

Subsequently, in order to remove the reaction layer on the surface of the plug 16 exposed at the bottom of the wiring groove 19, argon (A) was used.
r) Surface treatment of the semiconductor substrate 1 is performed by sputter etching in an atmosphere.

Next, as shown in FIG. 4, a tantalum nitride film, for example, a tantalum nitride film to be a barrier conductor film (first conductive film) 20 of an embedded wiring 23 described later is formed on the entire surface of the semiconductor substrate 1. Is deposited by performing reactive sputtering in an argon / nitrogen mixed atmosphere. This tantalum nitride film is deposited to improve the adhesion of the copper film deposited in the subsequent steps and to prevent the diffusion of copper, and its thickness is about 30 nm. In the first embodiment, the barrier conductor film 20 is exemplified by a tantalum nitride film, but may be a metal film such as tantalum, a titanium nitride film, or a laminated film of a metal film and a nitride film. When the barrier conductor film is tantalum or tantalum nitride, the adhesion to the copper film is better than when titanium nitride is used. When the barrier conductor film 20 is a titanium nitride film, the surface of the titanium nitride film can be sputter-etched immediately before the formation of the conductive film 21 in the subsequent step. By such sputter etching, water, oxygen molecules, and the like adsorbed on the surface of the titanium nitride film can be removed, and the adhesiveness of the conductive film 21 can be improved. This technique is particularly effective when the conductive film 21 is formed by exposing the surface to the atmosphere by vacuum breaking after the deposition of the titanium nitride film. This technique is effective not only for the titanium nitride film but also for the tantalum nitride film, although the effect is different.

Subsequently, for example, a copper film or a copper alloy film serving as a seed film is deposited on the entire surface of the semiconductor substrate 1 on which the barrier conductor film 20 is deposited. If the seed film is a copper alloy film, the alloy should contain about 80% by weight or more of copper (Cu). The seed film is deposited by a long-distance sputtering method.
9 on the surface of the barrier conductor film 20 excluding the inside of
It is set to about 2,000 to 2,000, preferably about 1,500. In the first embodiment, a case where a long-distance sputtering method is used for depositing a seed film is illustrated. However, an ionized sputtering method in which Cu sputtering atoms are ionized to increase the directivity of sputtering may be used. The seed film is deposited by CVD.
The high vacuum state can be maintained as long as the CVD film forming unit is connected to the chamber for forming the barrier conductor film 20, so that the surface of the deposited barrier conductor film 20 can be prevented from being oxidized. .

Next, the semiconductor substrate 1 on which the seed film is deposited
A conductive film made of, for example, a copper film is formed on the entire surface of
Is embedded so that the conductive film and the above-described seed film are combined to form a conductive film (first conductive film) 21. The conductive film filling the wiring groove 19 is formed by, for example, an electrolytic plating method. As a plating solution, for example, sulfuric acid (H ₂ SO ₄ ) in 10% copper sulfate (CuSO ₄ ) and a copper film for improving the coverage. Is used. When an electroplating method is used to form a conductive film that fills the wiring groove 19, the growth rate of the conductive film can be electrically controlled, so that the coverage of the conductive film inside the wiring groove 19 is improved. Can be. In the first embodiment, the case where the electroplating method is used for depositing the conductive film filling the wiring groove 19 is exemplified, but the electroless plating method may be used. Since the application of an electric field is not required when using the electroless plating method, damage to the semiconductor substrate 1 due to the application of the electric field can be reduced as compared with the case where the electrolytic plating method is used.

Further, following the step of forming the conductive film 21, the copper film is fluidized by an annealing treatment, so that the filling property of the conductive film 21 into the wiring groove 19 can be further improved.

Next, by removing the excess barrier conductor film 20 and conductive film 21 on the insulating film 18 and leaving the barrier conductor film 20 and conductive film 21 in the wiring groove 19, the buried wiring (first wiring ) 23 is formed. The removal of the barrier conductor film 20 and the conductive film 21 is performed by polishing using a CMP method.

Subsequently, the abrasive grains and copper adhered to the surface of the semiconductor substrate 1 are removed by two-step brush scrub cleaning using, for example, a 0.1% aqueous ammonia solution and pure water, and then shown in FIG. As described above, a silicon nitride film is deposited on the buried wiring 23 and the insulating film 18 to form a barrier insulating film 24a. The deposition of this silicon nitride film
For example, a plasma CVD method can be used, and its film thickness is about 50 nm. The barrier insulating film 24a has a function of suppressing diffusion of copper constituting the conductive film 21 of the embedded wiring 23. This prevents copper from diffusing into the insulating films 14 and 18 together with the barrier conductor film 20 and the insulating film 24 described later, retains their insulating properties, and improves the reliability of the semiconductor integrated circuit device. The barrier insulating film 24a also functions as an etch stopper layer when performing etching in a later step.

Next, an insulating film 24b having a thickness of about 400 nm is deposited on the surface of the barrier insulating film 24a. The insulating film 24b is a SOG film deposited by a coating method, a low dielectric constant film (SiOF) such as a CVD oxide film doped with fluorine, a silicon nitride film, or a combination of a plurality of types of insulating films. When a low dielectric constant film is used, the overall dielectric constant of the wiring of the semiconductor integrated circuit device can be reduced, and the wiring delay can be improved.

Next, a silicon nitride film is deposited on the surface of the insulating film 24b by, for example, a plasma CVD method, and an etch stopper film 24c having a thickness of about 50 nm is deposited. The etch stopper film 24c avoids damaging the lower layer and deteriorating the processing dimensional accuracy due to excessive digging when forming a groove or hole for forming a wiring in the insulating film 24 described later. It is for.

Subsequently, an SOG film having a thickness of about 300 nm is deposited on the surface of the etch stopper film 24c by a coating method, an insulating film 24d is deposited, and an insulating film (second insulating film) 24 is formed.
Is formed. The insulating film 24d may be a low dielectric constant film such as a CVD oxide film to which fluorine is added, a silicon nitride film, or a combination of a plurality of types of insulating films. When the insulating film 24d is an SOG film, for example, TEOS (Tetr
A silicon oxide film having a thickness of about 100 nm is deposited by a plasma CVD method using an aethoxysilane gas. This silicon oxide film has a function of ensuring the mechanical strength of the insulating film 24d, which is an organic film.

Next, as shown in FIGS. 6A and 6B, connection for connecting the embedded wiring 23 as a lower layer wiring and the embedded wiring 28 as an upper layer wiring formed in a later step. A hole (first connection hole) 25a is formed. The connection hole 25a is formed in the insulating film 24 by a photolithography process.
A photoresist film having the same shape as a connection hole pattern for connecting to the embedded wiring 23 is formed on d, and a connection hole pattern is formed by a dry etching process using the photoresist film as a mask. At this time, the diameter of the connection hole 25a can be set to, for example, about 0.25 μm, and the depth can be set to about 0.75 μm to 1 μm.

Subsequently, the photoresist film is removed, a photoresist film having the same shape as the wiring groove pattern is formed on the insulating film 24d by a photolithography process, and the wiring groove 25b is formed by a dry etching process using the photoresist film as a mask.
To form FIG. 6A is a cross-sectional view taken along the line AA in FIG. 6B. In FIG. 6B, the relationship between the wiring groove 19 and the connection hole 25a can be easily described. For simplicity, the illustration of the wiring groove 25b is omitted.

At this time, as shown in FIG. 6B, the buried wiring 23 has a structure in which the buried wiring 23 is enlarged in the length direction at a connection portion between the connection hole 25a and the buried wiring 23. I have. In other words, the margin of the embedded wiring 23, which is the lower wiring that drops the connection hole 25a, is large. Therefore, when the connection hole 25a is formed, it is possible to reduce the possibility that the bottom surface of the connection hole 25a misses the embedded wiring 23. Further, at the interface between the embedded wiring 23 and the embedded wiring 28 formed in a later step, it is possible to suppress an increase in the frequency of collision between electrons and copper due to electric field concentration. By suppressing an increase in the frequency of collisions between electrons and copper, it is possible to prevent the movement of copper constituting the embedded wiring, so that the electromigration resistance at the interface between the embedded wiring 23 and the embedded wiring 28 can be improved. it can.

Further, even if copper migrates due to electromigration at the interface between the buried wiring 23 and a buried wiring 28 described later,
Since the opening margin with respect to the connection hole 25a is large, conduction can be maintained by the extra copper in the opening margin. That is, as a result, the electromigration resistance can be improved.

Next, as shown in FIGS. 7A and 7B, a barrier conductor film 26 is deposited by a process similar to the process of depositing the barrier conductor film 20. This barrier conductor film 2
6 can be, for example, a tantalum nitride film, and its thickness can be about 30 nm. In the first embodiment, the barrier conductor film 26 is exemplified by a tantalum nitride film, but may be a metal film such as tantalum, a titanium nitride film, or a stacked film of a metal film and a nitride film. When the barrier conductor film 26 is a titanium nitride film, the surface of the titanium nitride film can be sputter-etched immediately before the formation of the conductive film 27 in the subsequent step.

Subsequently, for example, a copper film or a copper alloy film serving as a seed film is deposited on the entire surface of the semiconductor substrate 1 on which the barrier conductor film 26 is deposited. If the seed film is a copper alloy film, the alloy should contain about 80% by weight or more of copper (Cu). The seed film is deposited by a long-distance sputtering method.
Barrier conductor film 2 excluding 5a and the inside of wiring groove 25b
At the surface of 0, the angle is about 1000 ° to 2000 °, preferably about 1500 °. In the first embodiment, a case where a long-distance sputtering method is used for depositing a seed film is illustrated. However, an ionized sputtering method in which Cu sputtering atoms are ionized to increase the directivity of sputtering may be used. The seed film may be deposited by a CVD method.

Next, the semiconductor substrate 1 on which the seed film is deposited
A conductive film made of, for example, a copper film is formed on the entire surface of
a and the wiring groove 25b are buried, and the conductive film and the above-described seed film are combined to form a conductive film 27. The conductive film filling the connection holes 25a and the wiring grooves 25b is formed by, for example, an electrolytic plating method. In the first embodiment, the case where the electroplating method is used for depositing the conductive film filling the connection holes 25a and the wiring grooves 25b is illustrated, but the electroless plating method may be used. Since the application of an electric field is not required when using the electroless plating method, damage to the semiconductor substrate 1 due to the application of the electric field can be reduced as compared with the case where the electrolytic plating method is used.

Further, following the step of forming the conductive film 27, the copper film is fluidized by annealing, so that the connection holes 25 a and the wiring grooves 25 of the conductive film 27 are formed.
The embedding property in b can also be improved.

Next, the excess barrier conductor film 26 and the conductive film 27 on the insulating film 24 are removed, and the barrier conductor film 25a and the conductive film 2 are formed in the connection holes 25a and the wiring grooves 25b.
The buried wiring 28 is formed by leaving 6b. The removal of the barrier conductor film 26 and the conductive film 27 is performed by polishing using a CMP method.

Subsequently, the abrasive grains and copper adhering to the surface of the semiconductor substrate 1 are removed by a two-stage brush scrub cleaning using, for example, a 0.1% aqueous ammonia solution and pure water. Is manufactured.

FIG. 7A is a sectional view taken along the line AA in FIG. 7B. In FIG. 7B, the relationship between the wiring groove 19 and the connection hole 25a is shown. The illustration of the wiring groove 25b is omitted for ease of explanation.

As shown in FIGS. 8A and 8B, near the contact portion between the connection hole 25a and the buried wiring 23, the buried wiring 23 is formed not only in its length direction but also in its width direction. Alternatively, the structure may be enlarged.
That is, the margin of the embedded wiring 23, which is a lower layer wiring for dropping the connection hole 25a, is expanded not only in the wiring length direction but also in the wiring width direction. Therefore, when the connection hole 25a is formed, it is possible to reduce the possibility that the bottom surface of the connection hole 25a becomes unsightly from the embedded wiring 23 as compared with the case where the embedded wiring 23 is expanded only in the wiring length direction. Further, at the interface between the buried wiring 23 and the buried wiring 28, it is possible to suppress an increase in the frequency of collision between electrons and copper caused by the electric field concentration, as compared with the case where the buried wiring 23 is expanded only in the wiring length direction. . By suppressing the increase in the frequency of collisions between electrons and copper as compared with the case where the embedded wiring 23 is expanded only in the wiring length direction, the movement of copper constituting the embedded wiring can be further prevented. Electromigration resistance at the interface between the semiconductor device and the embedded wiring 28 can be further improved.

The embedded wiring 23 and the embedded wiring 2
Even when copper migrates due to electromigration at the interface with
Since the margin for the gap 5a is increased not only in the wiring length direction but also in the wiring width direction, it is possible to further improve the maintenance of conduction due to the extra copper in the margin margin. That is, as a result, the electromigration resistance can be further improved.

FIG. 8A is a cross-sectional view taken along line AA in FIG. 8B. In FIG. 8B, the relationship between the wiring groove 19 and the connection hole 25a is shown. The illustration of the wiring groove 25b is omitted for ease of explanation.

(Embodiment 2) In Embodiment 2, the connection hole 25a described in Embodiment 1 with reference to FIGS. 6 to 8 is extended to the inside of the buried wiring 23 by over-etching. The present invention is applied to a method of manufacturing a semiconductor integrated circuit device formed as described above. Other members and manufacturing steps are the same as those in the first embodiment, and a description of those same members and steps will be omitted.

Next, a method of manufacturing the above-described semiconductor integrated circuit device will be described in the order of steps with reference to FIGS. In addition,
9 to 12, only the wiring groove 19 and the vicinity of the connection hole 25a are enlarged and illustrated for the description of the second embodiment.

The method of manufacturing the semiconductor integrated circuit device of the second embodiment is the same as that of the first embodiment up to the steps shown in FIGS.

Thereafter, as shown in FIG. 9, a connection hole 25 for connecting a buried wiring 23 as a lower layer wiring and a buried wiring 28 as an upper layer wiring formed in a later step.
a is formed. In the connection hole 25a, a photoresist film having the same shape as the connection hole pattern for connecting to the embedded wiring 23 is formed on the insulating film 24d by a photolithography process, and the connection hole pattern is formed by a dry etching process using the photoresist film as a mask. I do. In the dry etching process at this time, over-etching is performed so that the connection hole 25a reaches the inside of the embedded wiring without stopping when the connection hole 25a reaches the embedded wiring 23.

In FIG. 9, a plug (buried wiring 2
8) shows a case where the portion connected to the embedded wiring 23 is the end of the embedded wiring 23. However, since the plug (embedded wiring 28) reaches the inside of the embedded wiring 23, the plug (embedded wiring 23) 28) and the contact area between the buried wiring 23 and the buried wiring 23 have a shape which is larger than that of the first embodiment. Therefore, the plug (embedded wiring 2
At the interface between 8) and the embedded wiring 23, the current density can be reduced. As the current density decreases, Joule heat generated at the interface between the plug (embedded wiring 28) and the embedded wiring 23 can be reduced. This makes it possible to prevent electromigration at the interface between the plug (buried wiring 28) and the buried wiring 23 due to Joule heat.

Further, since the contact area between the plug (embedded wiring 28) and the embedded wiring 23 becomes larger than that of the first embodiment, it is formed in the embedded wiring 23 and a later step. Plug (Embedded wiring 2
At the interface with 8), it is possible to suppress an increase in the frequency of collision between electrons and copper due to electric field concentration. By suppressing the increase in the frequency of collision between electrons and copper, it is possible to prevent the movement of copper constituting the embedded wiring, so that the electromigration resistance at the interface between the embedded wiring 23 and the plug (embedded wiring 28) is improved. can do.

In the second embodiment, the point where the plug (embedded wiring 28) is connected to the embedded wiring 23 is as follows.
Although the case of the end portion of the buried wiring 23 is illustrated, the buried wiring 23 at the connection location is formed in the wiring length direction and the wiring width in the same manner as in the first embodiment described with reference to FIGS. Magnification margins may be taken in the direction or in both directions (FIG. 10). The connection hole 25a is formed by over-etching so as to reach the inside of the buried wiring 23, and by taking an extra margin, the plug (buried wiring 28) and the buried wiring 2 are formed.
3 can be further increased than the case described with reference to FIG. This makes it possible to further suppress electromigration at the interface between the plug (embedded wiring 28) and the embedded wiring 23.

As shown in FIGS. 11 and 12,
A structure in which a portion of the plug (embedded wiring 28) connected to the embedded wiring 23 may be partially out of view may be employed. At this time, a part of the bottom of the connection hole 25a reaches the inside of the embedded wiring 23, and another part of the bottom of the connection hole 25a is
The over-etching for forming the connection hole 25a is performed so as to reach the inside of the substrate or the etch stopper film 17.
Thereby, the contact area between the plug (embedded wiring 28) and the embedded wiring 23 can be formed in a shape that is larger than that in the first embodiment. Therefore, as in the case described with reference to FIGS. 9 and 10, at the interface between the plug (embedded wiring 28) and the embedded wiring 23,
The current density can be reduced. As the current density decreases, Joule heat generated at the interface between the plug (embedded wiring 28) and the embedded wiring 23 can be reduced. That is, it is possible to prevent electromigration at the interface between the plug (buried wiring 28) and the buried wiring 23 due to Joule heat.

Further, as in the case described with reference to FIGS. 9 and 10, the contact area between the plug (embedded wiring 28) and the embedded wiring 23 is larger than that in the first embodiment. As a result, it is possible to suppress an increase in the frequency of collision of electrons and copper due to electric field concentration at the interface between the embedded wiring 23 and a plug (embedded wiring 28) formed in a later step. By suppressing the increase in the frequency of collision between electrons and copper, it is possible to prevent the movement of copper constituting the embedded wiring, so that the electromigration resistance at the interface between the embedded wiring 23 and the plug (embedded wiring 28) is improved. can do.

(Embodiment 3) Embodiment 3 differs from Embodiment 1 and Embodiment 2 in that FIGS.
The present invention is applied to the method of manufacturing a semiconductor integrated circuit device in which the diameter of the plug (embedded wiring 28) is equal to or larger than the width of the embedded wiring 23, as described with reference to FIGS. 8 and 9 to 12, respectively. The other members and manufacturing steps are the same as those in the first embodiment or the second embodiment, and the description of the same members and steps will be omitted.

Next, a method of manufacturing the above-described semiconductor integrated circuit device will be described in the order of steps with reference to FIGS. 13 to 16, only the vicinity of the wiring groove 19 and the connection hole 25a is illustrated in an enlarged manner for the description of the third embodiment.

The method of manufacturing the semiconductor integrated circuit device according to the third embodiment is the same as the method described with reference to FIGS. 1 to 8 in the first embodiment, or FIGS. This is the same as the manufacturing method described above, except that the diameter of the plug (embedded wiring 28) is equal to or larger than the width of the embedded wiring 23, as shown in FIGS.

FIGS. 13 (a), 14 (a), 15
(A) and FIG. 16 (a) are cross-sectional views taken along line BB in FIG. 16 (b). In FIGS. 13 (b) to 16 (b), the insulating film 24 is illustrated for explanation. The illustration is omitted.

FIG. 13 shows a case where the bottom surface of the plug (embedded wiring 28) is circular and its diameter is larger than the width of the embedded wiring 23 (diameter of plug (embedded wiring 28)> width of embedded wiring 23). It is.

FIG. 14 shows a case where the shape of the bottom surface of the plug (embedded wiring 28) is elliptical and both the major axis and the minor axis are larger than the width of the embedded wiring 23 (the major axis of the plug (embedded wiring 28)> embedding). The width of the wiring 23, the minor diameter of the plug (embedded wiring 28)> the width of the embedded wiring 23).

FIG. 15 shows that the shape of the bottom surface of the plug (embedded wiring 28) is elliptical and its major axis is larger than the width of the embedded wiring 23 (the major axis of the plug (embedded wiring 28)> the width of the embedded wiring 23). The short diameter is the embedded wiring 2
3 (shorter diameter of plug (embedded wiring 28) ≦ width of embedded wiring 23). At this time, the minor diameter of the plug (embedded wiring 28) is set so that the bottom area of the plug (embedded wiring 28) is not smaller than the case shown in FIGS. 7 and 8 in the first embodiment. And

FIG. 16 shows a case where the bottom surface of the plug (embedded wiring 28) has an elliptical shape and its major axis direction is orthogonal to the wiring length direction of the embedded wiring 23. The major axis of the plug (embedded wiring 28) is larger than the width of the embedded wiring 23 (the major axis of the plug (embedded wiring 28)> the width of the embedded wiring 23), and the minor axis is equal to or less than the width of the embedded wiring 23 (plug (embedded wiring 28)). Minor diameter of wiring 28) ≦ width of embedded wiring 23). At this time, the minor diameter of the plug (embedded wiring 28) is set so that the bottom area of the plug (embedded wiring 28) is not smaller than the case shown in FIGS. 7 and 8 in the first embodiment. And

In the third embodiment, FIGS.
6B, as shown in FIG.
If the shape of the bottom surface of 8) is circular, the diameter is larger than the width of the embedded wiring 23. In the case where the shape of the bottom surface of the plug (embedded wiring 28) is elliptical, at least its long diameter is equal to that of the embedded wiring 23.
Is larger than the width. Therefore, the contact area between the plug (embedded wiring 28) and the embedded wiring 23 can be increased as compared with the case of the first embodiment. As a result, the plug (embedded wiring 28) and the embedded wiring 23
At the interface with the substrate, the current density can be reduced. As the current density decreases, Joule heat generated at the interface between the plug (embedded wiring 28) and the embedded wiring 23 can be reduced. Therefore,
Electromigration at the interface between the plug (buried wiring 28) and the buried wiring 23 caused by Joule heat can be prevented.

Further, since the contact area between the plug (embedded wiring 28) and the embedded wiring 23 becomes larger than that of the first embodiment, it is formed in the embedded wiring 23 and a later step. Plug (Embedded wiring 2
At the interface with 8), it is possible to suppress an increase in the frequency of collision between electrons and copper due to electric field concentration. By suppressing the increase in the frequency of collision between electrons and copper, it is possible to prevent the movement of copper constituting the embedded wiring, so that the electromigration resistance at the interface between the embedded wiring 23 and the plug (embedded wiring 28) is improved. can do.

In FIGS. 13 to 16 of the third embodiment, the shape of the connection between the embedded wiring 23 and the plug (embedded wiring 28) is described with reference to FIG. 12 in the second embodiment. The case where the present invention is applied to the case having the shape described above has been described as an example. However, in the case described with reference to FIGS. 7 to 8 in the first embodiment and FIGS. 9 to 11 in the second embodiment, It is also possible to apply.

Although the invention made by the inventor has been specifically described based on the embodiments of the present invention, the present invention is not limited to the above embodiments, and various modifications may be made without departing from the gist of the invention. Needless to say, it can be changed.

Further, for example, in the first embodiment, the case where the margin for unplugging the plug from the upper layer is expanded by expanding the buried wiring as the lower wiring in the wiring length direction has been described. By expanding the buried wiring serving as the lower-layer wiring in the width direction of the wiring, the margin for unplugging the plug from the upper layer may be expanded.

For example, in the first embodiment, a case where a tantalum nitride film is deposited by a sputtering method as a barrier conductor film of a buried wiring is illustrated, but tungsten nitride (WN) is deposited by a sputtering method.
A film may be deposited.

Further, the method of manufacturing a semiconductor integrated circuit device according to the present invention is a method of manufacturing a semiconductor integrated circuit device by a wiring forming process using a damascene method.
Application to SI and the like is possible.

[0084]

The effects obtained by typical ones of the inventions disclosed by the present application will be briefly described as follows. (1) According to the present invention, the buried wiring is expanded in the wiring length direction or the wiring width direction in the vicinity of the connection portion between the plug and the buried wiring. Can be prevented. (2) According to the present invention, since the uncovered margin of the buried wiring, which is the lower wiring for dropping the connection hole, is enlarged, electromigration of copper constituting the buried wiring and the plug can be prevented. (3) According to the present invention, since the contact area between the plug and the embedded wiring can be increased, it is possible to prevent the generation of Joule heat at the connection between the plug and the embedded wiring. (4) According to the present invention, Joule heat can be prevented from being generated at the connection between the plug and the embedded wiring.
Electromigration of copper at the interface between the plug and the buried wiring due to Joule heat can be prevented.

[Brief description of the drawings]

FIG. 1 is a fragmentary cross-sectional view showing an example of a method for manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention.

FIG. 2 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 1;

3 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 2;

FIG. 4 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 3;

5 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 4;

FIGS. 6A and 6B are a cross-sectional view and a plan view of a main part of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 5;

7A and 7B are a cross-sectional view and a plan view of a main part of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 6;

FIGS. 8A and 8B are a main part cross-sectional view and a main part plan view illustrating an example of a method for manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention.

FIG. 9 is a fragmentary cross-sectional view showing one example of the method for manufacturing the semiconductor integrated circuit device according to one embodiment of the present invention;

FIG. 10 is a fragmentary cross-sectional view showing one example of the method for manufacturing the semiconductor integrated circuit device according to one embodiment of the present invention;

FIG. 11 is a fragmentary cross-sectional view showing one example of the method for manufacturing the semiconductor integrated circuit device according to one embodiment of the present invention;

FIG. 12 is a fragmentary cross-sectional view showing one example of the method for manufacturing the semiconductor integrated circuit device according to one embodiment of the present invention;

FIGS. 13A and 13B are a main part cross-sectional view and a main part plan view showing an example of a method for manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention.

14 (a) and (b) are a fragmentary cross-sectional view and a fragmentary plan view illustrating an example of a method for manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention.

FIGS. 15A and 15B are a main part cross-sectional view and a main part plan view illustrating an example of a method for manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention.

16 (a) and (b) are a fragmentary cross-sectional view and a fragmentary plan view illustrating an example of a method for manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention.

[Explanation of symbols]

Reference Signs List 1 semiconductor substrate 4 silicon oxide film 5 silicon oxide film 6 element isolation groove 7 p-type well 9 gate oxide film 10 gate electrode 11a cap insulating film 11b sidewall spacer 12 n ⁻ type semiconductor region 13 n ⁺ type semiconductor region 14 insulating film 15 Connection hole 16 Plug 16a Barrier conductor film 16b Conductive film 17 Etch stopper film (first insulating film) 18 Insulating film (first insulating film) 19 Wiring groove 20 Barrier conductor film (first conductive film) 21 Conductive film ( (First conductive film) 23 embedded wiring (first wiring) 24 insulating film (second insulating film) 24a barrier insulating film 24b insulating film 24c etch stopper film 24d insulating film 25a connection hole (first connection hole) 25b wiring groove 26 Barrier conductor film 27 Conductive film 28 Embedded wiring

 ──────────────────────────────────────────────────の Continuing on the front page (72) Katsuhiro Torii Inventor, Device Development Center, Hitachi, Ltd. 6-16, Shinmachi, Ome-shi, Tokyo (72) Inventor Hideki Yamaguchi 6-16, Shinmachi, Ome-shi, Tokyo F-term in the Hitachi, Ltd. Device Development Center Co., Ltd. F-term (reference) PP28 PP33 QQ09 QQ10 QQ25 QQ37 QQ48 QQ58 QQ59 QQ65 QQ73 QQ75 QQ92 QQ94 RR04 RR06 RR09 RR11 SS04 SS11 SS15 TT02 TT08 XX05 XX15

Claims (5)

[Claims] (A) forming a wiring groove by etching a first insulating film deposited on a main surface of a semiconductor substrate; and (b) forming a wiring groove in the first insulating film including the inside of the wiring groove. Depositing a first conductive film on the top, and (c) chemically and mechanically polishing the first conductive film outside the wiring groove, so that the first conductive film is formed in the wiring groove. Forming a first wiring, leaving (d) depositing a second insulating film on the first insulating film and the first wiring, and (e) etching the second insulating film. Forming a first connection hole reaching the first wiring, wherein the first wiring is formed by enlarging at least one of a length direction and a width direction at an interface with the first connection hole. A method for manufacturing a semiconductor integrated circuit device. (A) forming a wiring groove by etching a first insulating film deposited on a main surface of a semiconductor substrate; and (b) forming a wiring groove in the first insulating film including the inside of the wiring groove. Depositing a first conductive film on the top, and (c) chemically and mechanically polishing the first conductive film outside the wiring groove, so that the first conductive film is formed in the wiring groove. Forming a first wiring, leaving (d) depositing a second insulating film on the first insulating film and the first wiring, and (e) etching the second insulating film. Forming a first connection hole reaching the first wiring, wherein the first connection hole is formed so as to reach the inside of the first wiring by over-etching. Method. 3. A step of forming a wiring groove by etching a first insulating film deposited on a main surface of a semiconductor substrate, and FIG. Depositing a first conductive film on the top, and (c) chemically and mechanically polishing the first conductive film outside the wiring groove, so that the first conductive film is formed in the wiring groove. Forming a first wiring, leaving (d) depositing a second insulating film on the first insulating film and the first wiring, and (e) etching the second insulating film. Forming a first connection hole reaching the first wiring, wherein the first wiring is formed by enlarging at least one of a length direction and a width direction at an interface with the first connection hole; The first connection hole is formed as a circular or elliptical opening. If the hole is circular, adjust the diameter to the first
A method for manufacturing a semiconductor integrated circuit device, wherein the width is larger than the width of a wiring, and when the opening shape is an elliptical shape, at least the major axis is larger than the width of the first wiring. 4. A step of forming a wiring groove by etching a first insulating film deposited on a main surface of a semiconductor substrate, and b. Depositing a first conductive film on the top, and (c) chemically and mechanically polishing the first conductive film outside the wiring groove, so that the first conductive film is formed in the wiring groove. Forming a first wiring, leaving (d) depositing a second insulating film on the first insulating film and the first wiring, and (e) etching the second insulating film. Forming a first connection hole reaching the first wiring, wherein the first connection hole is formed so as to reach the inside of the first wiring by overetching with an opening shape of a circle or an ellipse, If the opening shape is circular, the diameter is larger than the width of the first wiring. A method of manufacturing a semiconductor integrated circuit device, wherein, when the opening is elliptical, at least the major axis is larger than the width of the first wiring. 5. A first insulating film formed by depositing a first insulating film on a main surface of a semiconductor substrate and embedding a first conductive film in a wiring groove formed in a part of the first insulating film. A semiconductor integrated circuit device comprising: a wiring; a first connection hole formed in a part of the first insulation film and a second insulation film deposited on the first wiring; Reaches the first wiring, and at least one of a length direction and a width direction of the first wiring is enlarged at an interface with the first connection hole.