JP2002269896A - Signal generation circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a signal generation circuit capable of exactly deriving a specified signal according to signal inversion due to zero-cross of an analog signal. SOLUTION: The signal generation circuit is provided with D flip-flops 2, 3 for receiving an input signal to a terminals T according to signal inversion due to the zero-cross of the analog signal and deriving an output signal to a terminal Q, a comparator 6 having a hysteresis characteristic for receiving the output signals of the D flip-flops 2, 3 to a non-inversion input terminal as input signals, and a generated signal output terminal 5 connected with the non-inverted input terminal of the comparator 6, and derives the generated signal to the generated signal output terminal 5 corresponding to application of the input signal to the comarator 6 having the hysteresis characteristic due to the D flip-flops 2, 3, and also performs operation of resetting the D flip-flops 2, 3 by the output signal of the comparator 6 having the hysteresis characteristic.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a signal generation circuit,
In particular, storage devices (HDD, CD, D
RZ (Return Zero), which converts an analog read signal from a VD or the like disk into a digital signal
o) It relates to a signal generation circuit.

[0002]

2. Description of the Related Art In FIG. 7, a read signal from a disk is an analog signal, and a portion where the signal crosses zero is a data "0" to "1" or a data "1" to "0".
The RZ signal generation circuit generates a signal having a certain pulse width as a signal representing the inverted portion.

As shown in FIGS. 5 and 6, in a conventional circuit, a comparator 1 for binarizing an analog signal, a delay circuit 9 for delaying an output signal of the comparator 1, and an output signal of the comparator 1 are inputted. A pulse signal c, that is, an RZ signal is obtained at the output terminal 5 with the starting point when the output of the comparator 1 is inverted and the ending point after the delay time td of the delay circuit 9. The delay time t of the delay circuit 9 corresponding to this pulse width time
d takes into account the fluctuation of the delay time td, the delay of the edge due to the load capacitance of the RZ signal output terminal 5, and the like.
In order to operate a circuit connected to a subsequent stage of the signal generation circuit, the input signal of the RZ signal generation circuit is set to about １ ／ of the minimum width of the zero-cross interval.

As the data transfer speed has increased, it has become necessary to reduce the pulse width td. However, when the pulse width td is reduced, there is a problem that the H level voltage of the pulse signal cannot be compensated due to the fluctuation of the delay time td or the delay of the rise due to the load capacitance of the RZ signal output terminal.

[0005]

SUMMARY OF THE INVENTION An object of the present invention is to provide a signal generating circuit capable of accurately deriving a predetermined signal according to signal inversion due to zero crossing of an analog signal.

[0006]

In a signal generation circuit according to a first aspect of the present invention, a comparator having a hysteresis characteristic of receiving a predetermined input signal at a non-inverting input terminal according to a signal inversion due to a zero cross of an analog signal, and the comparator And a derived signal output terminal connected to a non-inverting input terminal of the non-inverting input terminal, and derives a produced signal to the produced signal output terminal in response to application of the input signal to a comparator having the hysteresis characteristic, and The reset operation is performed on the input signal by the output signal of the comparator.

In a signal generation circuit according to a second aspect of the present invention, a comparator having a hysteresis characteristic of receiving an input signal rising due to signal inversion due to zero crossing of an analog signal at a non-inverting input terminal and a non-inverting input terminal of the comparator. A generation signal output terminal, wherein a generation signal is derived from the generation signal output terminal in response to application of the input signal to the comparator having the hysteresis characteristic, and the input signal is output by the output signal of the comparator having the hysteresis characteristic. Is to perform a reset operation.

In the signal generation circuit according to the third invention, a D flip-flop for receiving an input signal at a T terminal and deriving an output signal at a Q terminal in response to a signal inversion due to a zero cross of an analog signal, and an output of the D flip-flop A comparator having a hysteresis characteristic that receives a signal as an input signal at a non-inverting input terminal; and a generated signal output terminal connected to the non-inverting input terminal of the comparator. A generation signal is derived to the generation signal output terminal in response to the application of the input signal, and a reset operation of the D flip-flop is performed by an output signal of the comparator having the hysteresis characteristic.

According to a fourth aspect of the present invention, there is provided a signal generation circuit which receives an analog signal as an input, receives the output of the comparator as an input signal at a T terminal, and derives an output signal at a Q terminal. A D flip-flop, a comparator having a hysteresis characteristic of receiving the output signals of the first and second D flip-flops as an input signal at a non-inverting input terminal via an OR circuit, and a non-inverting input terminal of the comparator. A generated signal output terminal connected thereto, and derives a generated signal to the generated signal output terminal in response to application of the input signal to the comparator having the hysteresis characteristic by the D flip-flop, and has the hysteresis characteristic. The first and second D flip-flops are reset by the output signal of the comparator. It is obtained to perform the Tsu door operation.

In a signal generation circuit according to a fifth aspect of the present invention, a logic circuit for deriving a predetermined output signal in response to a signal inversion due to a zero cross of an analog signal, and an output signal of the logic circuit being input to a non-inversion input terminal as an input signal A comparator having a received hysteresis characteristic, and a generation signal output terminal connected to a non-inverting input terminal of the comparator, wherein a generation signal is generated at the generation signal output terminal in response to application of the input signal to the comparator having the hysteresis characteristic. A signal is derived, and a reset operation is performed on the input signal based on an output signal of the comparator having the hysteresis characteristic.

In the signal generating circuit according to a sixth aspect of the present invention, a logic circuit for deriving an output signal which rises by signal inversion due to zero crossing of an analog signal, and a hysteresis characteristic of receiving the output signal of the logic circuit as an input signal at a non-inverting input terminal. And a generation signal output terminal connected to a non-inverting input terminal of the comparator, and derives a generation signal to the generation signal output terminal in response to application of the input signal to the comparator having the hysteresis characteristic. In addition, a reset operation is performed on the input signal based on an output signal of the comparator having the hysteresis characteristic.

[0012] In the signal generation circuit according to the seventh invention, the fifth circuit
Alternatively, in the sixth invention, the logic circuit includes a NAND circuit and an AND circuit.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1 Embodiment 1 of the present invention will be described with reference to FIGS. FIG. 1 is a connection diagram showing a configuration of the signal generation circuit according to the first embodiment. FIG. 2 is a waveform chart showing operation timing in the first embodiment. In the figure, 1 is an input comparator, 2 and 3 are D flip-flops (hereinafter, referred to as DFF), 4 is an OR circuit, and 5 is RZ (Return Zero).
o) A generated signal output terminal for deriving a signal, and 6 is a comparator having a hysteresis characteristic (hereinafter, referred to as a comparator with hysteresis).

In the circuit according to the present invention, the non-inverted output and the inverted output of the comparator 1 which receives a read signal from a disk are connected to the T input terminals of two DFFs 2 and 3 whose D input terminals are fixed at "H", respectively. And these two DFs
The OR logic circuit 4 of the Q terminal output of F2 and F3 is used as the output signal terminal 5 of the RZ signal generation circuit, and the output signal 5 of the OR logic circuit 4 is used as the non-inverting input signal of the comparator 6 with hysteresis of the threshold voltages VthH and VthL. The output of the comparator 6 is composed of a circuit connected to the R terminals of the two DFFs 2 and 3.

When the rising signal at the T input terminal of the DFF
The output changes from “L” to “H”, and the output 5 of the OR logic circuit 4 also changes from “L” to “H”. When the voltage level of the output 5 exceeds the threshold voltage VthH on the H side of the comparator 6, the output of the comparator 6 changes from "L" to "H", and the DFF using this signal as a reset signal
A few Q outputs go to "L". Thus, the response time t4 of the OR logic circuit 4 and the response time t
6, the total time t5 of the reset time t2 (t3) of the DFF2 (3) and the time t5 from when the output terminal 5 exceeds “L” to the threshold voltage VthH on the H side of the comparator 6
An output signal of the RZ signal generation circuit having a pulse width of d [t4 + t6 + t2 (t3) + t5] is obtained.

Therefore, the voltage of the output terminal 5 returns to "L" only when the output terminal 5 exceeds the threshold voltage VthH. That is, even if the rise of this output is delayed due to the load capacitance or the like, a pulse signal of "H" voltage or more exceeding the threshold voltage VthH is always output to the output terminal 5. Further, since the pulse width of a fixed time is not set as in the related art, it is possible to reduce the pulse width to the minimum necessary pulse width, and to further increase the speed.

According to the first embodiment of the present invention, the comparator 6 having a hysteresis characteristic of receiving the input signal b rising by the signal inversion due to the zero crossing of the analog signal at the non-inverting input terminal and the non-inverting input terminal of the comparator 6 A generated signal output terminal 5 connected thereto;
RZ is applied to the generated signal output terminal 5 in response to the application of the input signal b to the comparator 6 having the hysteresis characteristic.
Since the output signal d of the comparator 6 having the hysteresis characteristic is used to perform the reset operation on the input signal b, the input signal b rising due to the signal inversion due to the zero cross of the analog signal is derived. With the comparator 6 having the hysteresis characteristic received at the non-inverting input terminal, it is possible to obtain a signal generating circuit that can accurately derive a predetermined signal corresponding to signal inversion due to zero crossing of an analog signal.

Further, according to the first embodiment of the present invention, the input comparator 1 which receives an analog signal as an input.
And first and second D flip-flops 2 and 3 which receive the output of the comparator 1 as an input signal at a T terminal and derive an output signal at a Q terminal, respectively, and the first and second D flip-flops 2 and 3 A comparator 6 having a hysteresis characteristic of receiving the output signal b of the third circuit 3 as an input signal at a non-inverting input terminal via an OR circuit 4, and a generated signal output terminal 5 connected to the non-inverting input terminal of the comparator 6
And generating a generated signal c, which is an RZ signal, to the generated signal output terminal 5 in accordance with the application of the input signal b to the comparator 6 having the hysteresis characteristic by the D flip-flops 2 and 3. According to the output signal d of the comparator 6 having the hysteresis characteristic,
And the reset operation of the second D flip-flops 2 and 3 is performed, so that the output a of the input comparator 1 to which an analog signal is input is set to T and
A comparator 6 having a hysteresis characteristic of receiving the output signal b of the first and second D flip-flops 2 and 3 for receiving the output signal b at the Q terminal and receiving the output signal b as the input signal at the non-inverting input terminal via the OR circuit 4 Accordingly, it is possible to obtain a signal generation circuit that can accurately derive a predetermined signal according to signal inversion due to zero crossing of an analog signal.

Embodiment 2 Second Embodiment A second embodiment according to the present invention will be described with reference to FIGS. FIG. 3 is a connection diagram illustrating a configuration of a signal generation circuit according to the second embodiment.
FIG. 4 is a waveform chart showing operation timing in the second embodiment. In the second embodiment, the configuration other than the specific configuration described here has the same configuration as the first embodiment described above, and has the same operation.

In the figure, 1 is an input comparator,
2, 3 are DFFs, 4 is an OR circuit, 5 is a generated signal output terminal for deriving an RZ signal, 6 is a comparator with hysteresis, and 8 is a logic circuit including a NAND circuit and an AND circuit.

In the second embodiment, the DFFs 2 and 3 in the first embodiment are replaced with a logic circuit 8 to simplify the circuit. As in the first embodiment, the logic circuit 8 returns the output terminal 5 from "H" to "L" by the "H" signal of the comparator 6 as in the first embodiment.

According to the second embodiment of the present invention, a logic circuit 8 including a NAND circuit and an AND circuit for deriving an output signal b which rises by signal inversion due to zero crossing of an analog signal, and an output signal b of the logic circuit 8 A comparator having a hysteresis characteristic received at the non-inverting input terminal as an input signal; and a generated signal output terminal connected to the non-inverting input terminal of the comparator.
RZ is applied to the generated signal output terminal 5 in response to the application of the input signal b to the comparator 6 having the hysteresis characteristic.
In addition to deriving a generated signal, the output signal d of the comparator 6 having the hysteresis characteristic performs a reset operation on the input signal b, so that an output signal b that rises due to signal inversion due to zero crossing of an analog signal is derived. NAND circuit and AN
A signal that can accurately derive a predetermined signal corresponding to signal inversion due to zero crossing of an analog signal by a comparator 6 having a hysteresis characteristic that receives an output signal b of a logic circuit 8 composed of a D circuit as an input signal at a non-inverting input terminal. A generation circuit can be obtained.

As described above, according to the first and second embodiments of the present invention, by using the comparator 6 with hysteresis, the generated signal output terminal 5 has a voltage of VthH or more set by the comparator 6 with hysteresis. The "H" voltage is always output.

[0024]

According to the first aspect of the present invention, a comparator having a hysteresis characteristic of receiving a predetermined input signal at a non-inverting input terminal in response to a signal inversion due to zero crossing of an analog signal, and connecting to a non-inverting input terminal of the comparator. And a derived signal output terminal, and derives a generated signal to the generated signal output terminal in response to application of the input signal to the comparator having the hysteresis characteristic, and the output signal of the comparator having the hysteresis characteristic. Since the reset operation is performed on the input signal, it is possible to obtain a signal generation circuit that can accurately derive a predetermined signal corresponding to the signal inversion due to the zero crossing of the analog signal by the comparator having the hysteresis characteristic.

According to the second aspect of the invention, the comparator having the hysteresis characteristic of receiving the input signal rising by the signal inversion due to the zero crossing of the analog signal at the non-inverting input terminal, and the output of the generated signal connected to the non-inverting input terminal of the comparator And generating a generation signal to the generation signal output terminal in response to application of the input signal to the comparator having the hysteresis characteristic, and performing a reset operation on the input signal by an output signal of the comparator having the hysteresis characteristic. A comparator having a hysteresis characteristic that receives an input signal that rises by signal inversion due to zero crossing of an analog signal at a non-inverting input terminal can accurately derive a predetermined signal according to signal inversion due to zero crossing of an analog signal. Signal generation circuit It is possible to obtain.

According to the third aspect, a D flip-flop for receiving an input signal at a T terminal and deriving an output signal at a Q terminal in response to a signal inversion due to a zero crossing of an analog signal, and outputting the output signal of the D flip-flop to a non- A comparator having a hysteresis characteristic received as an input signal at an inverting input terminal; and a generated signal output terminal connected to a non-inverting input terminal of the comparator, wherein the input signal to the comparator having the hysteresis characteristic by the D flip-flop is provided. In addition to deriving a generation signal to the generation signal output terminal in response to the application of the signal, the reset operation of the D flip-flop is performed by the output signal of the comparator having the hysteresis characteristic. Corresponding to the input signal at the T terminal and the output signal at the Q terminal To obtain a signal generation circuit that can accurately derive a predetermined signal corresponding to signal inversion due to zero crossing of an analog signal by a comparator having a hysteresis characteristic that receives an output signal of a D flip-flop as an input signal at a non-inverting input terminal. Can be.

According to the fourth aspect of the invention, the input comparator which receives an analog signal as input, and the first and second D which receive the output of the comparator as an input signal at the T terminal and derive the output signal at the Q terminal, respectively. Flip-flops,
A comparator having a hysteresis characteristic for receiving output signals of the first and second D flip-flops as input signals to a non-inverting input terminal via an OR circuit; and a generated signal output terminal connected to the non-inverting input terminal of the comparator Wherein the D flip-flop derives a generation signal to the generation signal output terminal in response to application of the input signal to the comparator having the hysteresis characteristic, and outputs the generated signal from the comparator having the hysteresis characteristic by the output signal of the comparator having the hysteresis characteristic. Since the reset operation of the first and second D flip-flops is performed, the first and second terminals which receive the output of the input comparator which receives the analog signal as an input signal at the T terminal and derive the output signal at the Q terminal, respectively. Non-inverted input of the output signal of D flip-flop No. 2 via OR circuit The comparator with hysteresis that receives as an input signal to the child, it is possible to obtain a signal generating circuit which can accurately derive the predetermined signal corresponding to the signal inversion by zero crossing of the analog signal.

According to the fifth aspect, a logic circuit for deriving a predetermined output signal in accordance with signal inversion due to zero crossing of an analog signal, and a hysteresis characteristic of receiving the output signal of the logic circuit as an input signal at a non-inverting input terminal And a generation signal output terminal connected to a non-inverting input terminal of the comparator, and derives a generation signal to the generation signal output terminal in response to application of the input signal to the comparator having the hysteresis characteristic. Along with
Since the reset operation is performed on the input signal based on the output signal of the comparator having the hysteresis characteristic, the output signal of the logic circuit that derives a predetermined output signal according to the signal inversion due to the zero cross of the analog signal is supplied to the non-inverting input terminal. By using a comparator having a hysteresis characteristic received as an input signal, it is possible to obtain a signal generation circuit that can accurately derive a predetermined signal corresponding to signal inversion due to zero crossing of an analog signal.

According to the sixth aspect, a logic circuit for deriving an output signal which rises by signal inversion due to zero crossing of an analog signal, and a comparator having a hysteresis characteristic of receiving an output signal of the logic circuit as an input signal at a non-inverting input terminal And a generated signal output terminal connected to a non-inverting input terminal of the comparator, and, based on application of the input signal to the comparator having the hysteresis characteristic, deriving a generated signal to the generated signal output terminal, Since the reset operation is performed on the input signal based on the output signal of the comparator having the hysteresis characteristic, the output signal of the logic circuit that derives an output signal that rises due to signal inversion due to zero crossing of the analog signal is input to the non-inverting input terminal. With hysteresis characteristics The chromatography data, it is possible to obtain a signal generating circuit which can accurately derive the predetermined signal corresponding to the signal inversion by zero crossing of the analog signal.

According to a seventh aspect, in the fifth or sixth aspect, the logic circuit is a NAND circuit and an AND circuit.
The circuit has a hysteresis characteristic in which an output signal of a logic circuit composed of a NAND circuit and an AND circuit that derives a predetermined output signal in accordance with signal inversion due to zero crossing of an analog signal is input to a non-inverting input terminal as an input signal. With such a comparator, it is possible to obtain a signal generation circuit that can accurately derive a predetermined signal corresponding to signal inversion due to zero crossing of an analog signal.

[Brief description of the drawings]

FIG. 1 is a connection diagram showing a configuration of an RZ signal generation circuit according to a first embodiment of the present invention.

FIG. 2 is a waveform chart showing operation timing according to the first embodiment of the present invention.

FIG. 3 is a connection diagram showing a configuration of an RZ signal generation circuit according to a second embodiment of the present invention.

FIG. 4 is a waveform chart showing operation timing according to the second embodiment of the present invention.

FIG. 5 is a connection diagram illustrating a configuration of an RZ signal generation circuit in a conventional example.

FIG. 6 is a waveform chart showing operation timing in a conventional example.

FIG. 7 is an operation timing chart illustrating a basic operation in the RZ signal generation circuit.

[Explanation of symbols]

1 input comparator, 2, 3 DFF, 4 OR circuit, 5 generation signal output terminal, 6 comparator with hysteresis, 8 logic circuit.

Claims (7)

[Claims] 1. A comparator having a hysteresis characteristic for receiving a predetermined input signal at a non-inverting input terminal in response to a signal inversion due to a zero crossing of an analog signal, and a generated signal output terminal connected to the non-inverting input terminal of the comparator. A generation signal is derived to the generation signal output terminal in response to the application of the input signal to the comparator having the hysteresis characteristic, and a reset operation is performed on the input signal based on an output signal of the comparator having the hysteresis characteristic. A signal generation circuit, characterized in that: 2. A comparator having a hysteresis characteristic for receiving an input signal rising by a signal inversion due to a zero cross of an analog signal at a non-inverting input terminal, and a generated signal output terminal connected to the non-inverting input terminal of the comparator. A generation signal is derived from the generation signal output terminal in response to application of the input signal to a comparator having hysteresis characteristics, and a reset operation is performed on the input signal based on an output signal of the comparator having hysteresis characteristics. A signal generation circuit characterized by the above-mentioned. 3. A D flip-flop which receives an input signal at a T terminal and derives an output signal at a Q terminal in accordance with a signal inversion due to a zero crossing of an analog signal, and outputs an output signal of the D flip-flop to a non-inverting input terminal. A comparator having a hysteresis characteristic received as a signal, and a generation signal output terminal connected to a non-inverting input terminal of the comparator, and the D flip-flop applies the input signal to the comparator having the hysteresis characteristic according to the application of the input signal. A signal generation circuit, wherein a generation signal is derived to a generation signal output terminal, and a reset operation of the D flip-flop is performed by an output signal of the comparator having the hysteresis characteristic. 4. An input comparator to which an analog signal is input, first and second D flip-flops each receiving an output of the comparator as an input signal at a T terminal and outputting an output signal to a Q terminal, 1st and 2nd
A comparator having a hysteresis characteristic of receiving an output signal of the D flip-flop as an input signal to a non-inverting input terminal via an OR circuit, and a generated signal output terminal connected to the non-inverting input terminal of the comparator. A generation signal is derived from the generation signal output terminal in response to application of the input signal to the comparator having the hysteresis characteristic by a flip-flop, and the first signal is output by the comparator having the hysteresis characteristic.
And a reset operation of the second D flip-flop. 5. A logic circuit for deriving a predetermined output signal in accordance with signal inversion of an analog signal due to zero crossing, a comparator having a hysteresis characteristic receiving an output signal of the logic circuit as an input signal at a non-inverting input terminal, A generation signal output terminal connected to a non-inverting input terminal of a comparator, wherein a generation signal is derived to the generation signal output terminal in response to application of the input signal to a comparator having the hysteresis characteristic, and the hysteresis characteristic A reset operation for the input signal in response to an output signal of the comparator having the signal generation circuit. 6. A logic circuit for deriving an output signal which rises by signal inversion due to a zero crossing of an analog signal, a comparator having a hysteresis characteristic receiving an output signal of the logic circuit as an input signal at a non-inverting input terminal, and a non-inverting circuit of the comparator. A generation signal output terminal connected to an inverting input terminal, wherein the generation signal is derived to the generation signal output terminal in response to application of the input signal to the comparator having the hysteresis characteristic, and the comparator has the hysteresis characteristic A reset operation for the input signal in response to the output signal. 7. A logic circuit comprising: a NAND circuit and an AN
7. The signal generation circuit according to claim 5, wherein the signal generation circuit comprises a D circuit.