JP2002269523A - Ic card - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the read or alteration of important data stored in a semiconductor nonvolatile memory in an IC card, by preventing the unauthorized working of a test mode control signal and making it impossible to control an internal circuit by a test external terminal group, after shipment to the market. SOLUTION: This IC card comprises an unauthorized access detecting circuit 15 for detecting the input of an unauthorized signal, when a test mode control signal 17 outputted from a test mode switching circuit 11 shows a general operation mode, and a signal of a prescribed level is applied to the test external terminal group 11, and an deletion/write circuit 113 for erasing the memory contents of the nonvolatile memory 115 provided in the internal circuit 116 in the detection of the unauthorized input signal by the unauthorized access detecting circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention does not prevent unauthorized analysis of an internal circuit from a test external terminal by a third party, or reading or falsification of data in a nonvolatile semiconductor memory device that can be electrically erased and written. The present invention relates to an IC card having a built-in semiconductor integrated circuit.

[0002]

2. Description of the Related Art In recent years, it has been expected that important data such as personal information and money information will be stored in an IC card, and information security technology has become very important.

Hereinafter, a conventional IC card will be described with reference to the drawings.

FIG. 6 is a configuration diagram of a semiconductor integrated circuit built in a conventional IC card. 6, 61 denotes a test external terminal group, 61a, 61b,..., 61n denotes test external terminals, 62a, 62b,..., 62n denote corresponding test external terminals 61a, 61b,.
1n, an internal pull-down resistor connected to 1n, 67 a test mode control signal, 68 a transfer gate group, 69 an operation suppression circuit, 610 a power-on reset circuit, 611
Is a test mode switching circuit, 612 is test mode control memory read data, 613 is an erase / write circuit,
614 is a test mode control memory area, 615 is a semiconductor nonvolatile memory, 616 is an internal circuit, and 617 is a semiconductor integrated circuit.

Next, the operation of the semiconductor integrated circuit 617 thus configured will be described.

[0006] In the case of a non-contact IC card, the only external terminals actually used in the market as a product are a power supply terminal, a ground terminal, and an antenna. However, at the stage of shipping inspection of the semiconductor integrated circuit 617 incorporated in the non-contact IC card, it is necessary to use the test external terminal group 61 in order to shorten the inspection time and improve the failure detection rate. On the other hand, since the important data stored in the semiconductor nonvolatile memory 615 can be read and falsified from the test external terminal group 61,
After being shipped to the market as a product, it is necessary to disable the test external terminal group 61 used at the time of inspection.

In a shipping inspection process, test mode setting data is written to a test mode control memory area 614 in the semiconductor nonvolatile memory 615. The test mode setting data is stored in the semiconductor integrated circuit 617.
When the reset signal from the power-on reset circuit 610 is input to the test mode switching circuit 611 at the time of power-on, the test mode control memory read data 6
12 and stored in the test mode switching circuit 611. Based on the stored data, the test mode switching circuit 611 outputs a “High” level as the test mode control signal 67. This "High"
By inputting the level test mode control signal 67 to the control terminal of the transfer gate group 68, the test external terminal group 61 and the internal circuit 616 are electrically connected.

Thus, in the shipping inspection process, the internal circuit 616 is controlled using the test external terminal group 61, and the inspection can be performed easily and at high speed.

Next, at the end of the shipping inspection process, data for setting the normal operation mode for shipping to the market is written into the test mode control memory area 614 in the semiconductor nonvolatile memory 615. The information that the normal operation mode is set is stored in the test mode switching circuit 611 in the same manner as when the test mode is set. Based on the stored data, the test mode switching circuit 611 outputs a “Low” level as the test mode control signal 67. The "Low" level test mode control signal 67
Is input to the transfer gate group 68, whereby the connection between the test external terminal group 61 and the internal circuit 616 is electrically disconnected.

As described above, after shipment to the market, access to the internal circuit 616 by the test external terminal group 61 is disabled. Further, in the shipping inspection process, the functions of the internal circuit 616 mounted in the semiconductor integrated circuit 617 incorporated in the IC card can be inspected by making the test external terminal group 61 usable. Becomes

[0011]

However, in the above-mentioned conventional IC card, one test mode control signal 67 is fixed to a "High" level which is a setting for the test mode by a FIB (Focused Ion Beam) device or the like. Alone, the control and analysis of the semiconductor integrated circuit 617 can always be performed from the test external terminal group 61, and important data stored in the semiconductor nonvolatile memory 615 can be easily read or falsified. Was a problem.

SUMMARY OF THE INVENTION The present invention solves the above-mentioned problems. The purpose of the present invention is not only that the test mode control signal of the IC card cannot be easily processed by the FIB device, but also that after the test card is shipped to the market, an external test device is used. An object of the present invention is to provide an IC card having a built-in semiconductor integrated circuit that makes it impossible to control an internal circuit by a terminal group at all, and makes it impossible to read or falsify important data stored in a semiconductor nonvolatile memory.

[0013]

In order to achieve the above-mentioned object, an IC card according to the present invention is an IC card having a built-in semiconductor integrated circuit. A test external terminal group for testing the operation of the integrated circuit, a transfer gate group for electrically connecting and disconnecting the test external terminal group and the internal circuit, and a test for controlling switching between a normal operation mode and a test mode A mode switching circuit and a test mode control signal output from the test mode switching circuit indicate a normal operation mode, and an incorrect signal is input when a signal of a predetermined level is applied to a test external terminal group. Access detection circuit for detecting that an unauthorized access signal has been detected, and a semiconductor nonvolatile memory device provided in an internal circuit when the unauthorized access detection circuit detects an unauthorized input signal Characterized by comprising an erasing / writing circuit for erasing the storage contents.

According to this configuration, after shipment to the market,
By electrically disconnecting the transfer gate group, it is impossible to access the internal circuit by the test external terminal group, and furthermore, the unauthorized access detection circuit prevents unauthorized access to at least one of the test external terminal groups. When the application of the signal is detected, all data in the semiconductor nonvolatile memory device except the test mode control memory area is erased. This makes it impossible to illegally analyze the semiconductor integrated circuit or read or tamper with important data written in the semiconductor nonvolatile memory device.

Also, in the shipping inspection process, by making the external terminal group for testing available, each function of the internal circuit can be efficiently inspected, and a high failure detection rate can be realized in a short time. It becomes possible.

In the semiconductor integrated circuit incorporated in the IC card according to the present invention, when the unauthorized access detection circuit detects an unauthorized input signal from the test external terminal group, the power supply is turned off.
It is preferable that a power supply short circuit for short-circuiting between ground potentials with a MOS transistor is provided.

According to this configuration, when an incorrect signal is input, the power supply and the ground potential are connected (short-circuited) via the N-channel MOS transistor, and the power supply voltage is reduced to the lower limit of operation or lower of the semiconductor integrated circuit. And cannot operate normally. This makes it impossible to access the internal circuit using the test external terminal group, read out data written in the IC card, perform any operation such as erasing / writing, and perform electrical analysis.

Preferably, the power supply short circuit is arranged between an external terminal and an internal circuit corresponding to the power supply wiring and the ground wiring, respectively.

According to this configuration, when illegal processing is attempted, the power supply from the power supply terminal and the ground terminal to the internal circuit becomes unstable, the internal circuit does not operate normally, and is weak against noise. . This makes it possible to further improve security against making it impossible to access or operate the internal circuit due to unauthorized access via the test external terminal group.

Further, it is preferable that the power supply short circuit has a power supply line and a ground line common to the internal circuit and a diffusion layer forming a transistor.

According to this configuration, when an illegal processing is attempted, the operation of the transistor which is indispensable for the operation of the internal circuit becomes impossible. This makes it possible to further improve security against making it impossible to access or operate the internal circuit due to unauthorized access via the test external terminal group.

Further, the semiconductor integrated circuit built in the IC card according to the present invention detects a power-on reset circuit for generating a reset signal when power is turned on, and detects an input signal from a test external terminal group and detects the detection. An external input detection circuit that outputs a result to an unauthorized access detection circuit, wherein the semiconductor nonvolatile storage device has a test mode control memory area in which control data for the test mode switching circuit is stored, and a power-on reset circuit. And an external input detection circuit, a test mode control memory area, a test mode switching circuit, a power supply short circuit, an unauthorized access detection circuit, a transfer gate group, and a signal layout between these circuits and a power supply. Is composed of a lower wiring layer, which is a wiring layer for signals and power supplies that are indispensable for the operation of internal circuits. It is preferred that the obscured by out.

According to this configuration, in order to avoid a short circuit between the power supply and the ground potential at the time of unauthorized access, an attempt is made to disconnect the power supply short circuit from the power supply to the ground potential, or a test mode control signal or an unauthorized access. Even if an attempt is made to illegally control a detection signal or the like, a signal, a power supply, and the like necessary for the operation of the internal circuit are cut off first, making the operation of the semiconductor integrated circuit impossible. This makes it possible to significantly improve security against making it impossible to access or operate the internal circuit due to unauthorized access via the test external terminal group.

[0024]

Embodiments of the present invention will be described below with reference to the drawings.

(First Embodiment) First, a first embodiment of the present invention will be described with reference to FIG.

FIG. 1 is a block diagram showing a first embodiment of the present invention.
FIG. 3 is a configuration diagram of a semiconductor integrated circuit built in a C card.
In FIG. 1, reference numeral 11 denotes a test external terminal group, 11a, 1
, 11n are external test terminals, 12a, 12
, 12n are internal pull-down resistors connected to the corresponding test external terminals 11a, 11b,..., 11n, 13 is an OR circuit, 14a is an external input detection signal, 14 is an external input detection circuit, 15 Is an unauthorized access detection circuit, 16 is an unauthorized access detection signal, 17 is a test mode control signal, 18 is a transfer gate group, 19 is an operation inhibition circuit, 110 is a power-on reset circuit, 111 is a test mode switching circuit, and 112 is a test mode. Control memory read data, 113 is an erase / write circuit, 1
Reference numeral 14 denotes a test mode control memory area, 115 denotes a semiconductor nonvolatile memory, 116 denotes an internal circuit, and 117 denotes a semiconductor integrated circuit.

Next, the operation of the semiconductor integrated circuit 117 configured as described above will be described.

In the shipping inspection process, test mode setting data is written to the test mode control memory area 114 in the semiconductor nonvolatile memory 115. The test mode setting data is stored in the semiconductor integrated circuit 117.
When the reset signal from the power-on reset circuit 110 is input to the test mode switching circuit 111 when the power supply of the test mode is turned on, the test mode control memory read data 1
12 and stored in the test mode switching circuit 111.

Based on the stored data, the test mode switching circuit 111 outputs a “High” level as the test mode control signal 17. By inputting the “High” level test mode control signal 17 to the control terminal of the transfer gate group 18, the test external terminal group 11 and the internal circuit 116 are electrically connected. With this connection, the inspection of the internal circuit 116 by the test external terminal group 11 can be performed easily and at high speed.

Further, by inputting the "High" level test mode control signal 17 to the unauthorized access detection circuit 15, the unauthorized access detection signal 16, which is the output signal of the unauthorized access detection circuit 15, is fixed at the "Low" level. You. Thus, in the test mode, the unauthorized access detection circuit 15 does not detect any input signal from the test external terminal group 11.

As described above, in the shipping inspection process,
The test external terminal group 11 makes it possible to control and inspect the internal circuit 116 via the transfer gate group 18.

Next, at the end of the shipping inspection process, data for setting a normal operation mode for shipping to the market is written into the test mode control memory area 114 in the semiconductor nonvolatile memory 115. The information that the normal operation mode is set is stored in the test mode switching circuit 111 in the same manner as when the test mode is set. Based on the stored data, the test mode switching circuit 111 outputs a “Low” level as the test mode control signal 17.

By inputting a "Low" level test mode control signal 17 to the control terminals of the transfer gate group 18, the test external terminal group 11 and the internal circuit 116 are controlled.
Is electrically disconnected. This disconnection makes it impossible for the test external terminal group 11 to access the internal circuit 116.

Also, by inputting the "Low" level test mode control signal 17 to the unauthorized access detection circuit 15, an external input detection signal 14a which is an input signal to the unauthorized access detection circuit 15 and an unauthorized signal which is an output signal are output. The access detection signal 16 is connected.

After the normal operation mode is set, all the terminals of the test external terminal group 11 are open or “Low”.
Used with the level fixed. In this case, all terminals of the test external terminal group 11 are provided with an internal pull-down resistor 1.
, 12n, the external input detection signal 14a, which is the output signal of the OR circuit 13, is "L".
ow ”level, and the unauthorized access detection signal 16 is also“ L ”.
ow "level, and the semiconductor integrated circuit 117 operates normally.

However, when a “High” level signal is input to any one or more terminals of the test external terminal group 11, the external input detection signal 1 that is the output signal of the OR circuit 13 is output.
4a goes to the “High” level, and the unauthorized access detection signal 16 also goes to the “High” level. At this time, "Hi
The erase / write circuit 113 is controlled by the unauthorized access detection signal 16 at the “gh” level, and the test mode control memory area 11 of the semiconductor nonvolatile memory 115 is controlled.
All data except 4 is erased electrically and IC
Important personal data written in the card cannot be read.

As described above, according to the present embodiment, after shipment to the market, the access to the internal circuit 116 by the test external terminal group 11 is prevented by electrically disconnecting the transfer gate group 18. Further, when an invalid signal (“High” level signal) is applied from one or more terminals of the test external terminal group 11 and the unauthorized access detection signal 16 becomes “High” level, the semiconductor nonvolatile memory In order to erase all data except for the test mode control memory area 114 of the semiconductor integrated circuit 115, the illegal analysis of the semiconductor integrated circuit 117 or the semiconductor nonvolatile memory 1
It becomes impossible to read or tamper with the important data written in 15.

In the shipping inspection process, the functions of the internal circuit 116 in the semiconductor integrated circuit 117 built in the IC card can be efficiently inspected by making the test external terminal group 11 usable. And a high failure detection rate can be realized in a short time.

In this embodiment, after all the internal pull-down resistors 12a, 12b,..., 12n are replaced with internal pull-up resistors, the OR circuit is replaced with a NAND circuit, and after the test mode is set, the test external When it is assumed that all the terminals of the terminal group 11 are in an open state or a state in which the terminals are fixed at the “High” level in a normal use state, “Lo” is applied to at least one terminal of the external test terminal group 11.
When a signal at the “w” level is input, the external input detection signal, which is the output signal of the NAND circuit, goes to the “High” level, and it goes without saying that the same operation is performed thereafter.

(Second Embodiment) Next, a second embodiment of the present invention will be described with reference to FIG.

FIG. 2 is a circuit diagram of an I / O according to a second embodiment of the present invention.
FIG. 3 is a configuration diagram of a semiconductor integrated circuit built in a C card.
In FIG. 2, reference numeral 21 denotes a test external terminal group, 21a, 2
, 21n are test external terminals, 22a, 22
, 22n are internal pull-down resistors connected to the corresponding test external terminals 21a, 21b,..., 21n, 23 is an OR circuit, 24a is an external input detection signal, 24 is an external input detection circuit, 25 Is an unauthorized access detection circuit, 26 is an unauthorized access detection signal, 27 is a test mode control signal, 28 is a transfer gate group, 29 is an operation suppression circuit, 210 is a power-on reset circuit, 211 is a test mode switching circuit, and 212 is a test mode. The control memory read data 213 is an erase / write circuit,
14 is a test mode control memory area, 215 is a semiconductor nonvolatile memory, 216 is an internal circuit, 217 is a semiconductor integrated circuit, 218 is a power short circuit, 218p is a power short circuit power wiring, and 218g is a power short circuit ground wiring. It is.

Next, the operation of the semiconductor integrated circuit 217 thus configured will be described.

First, in the shipping inspection process, as in the first embodiment, when the test mode is set, the unauthorized access detection signal 26 is fixed at the "Low" level. The “Low” level unauthorized access detection signal 26 is connected between the power supply and the ground potential, and is input to the gate of the power supply short circuit 218 composed of an N-channel MOS transistor. At this time, since the gate input signal of the power supply short circuit 218 is fixed at the “Low” level,
The channel MOS transistor is turned off, and the power supply
It is disconnected between the ground potentials. Therefore, in the shipping inspection process, it is possible to control and inspect the internal circuit 216 through the transfer gate group 28 using the test external terminal group 21.

Next, at the end of the shipping inspection process, the first
Similarly to the embodiment, when the normal operation mode is set,
The semiconductor integrated circuit 217 operates normally by using all the terminals of the test external terminal group 21 in an open state or a state in which the terminals are fixed at a “Low” level.

However, when a "High" level signal is input to any one or more terminals of the test external terminal group 21, the external input detection signal 24a becomes "High" level and the unauthorized access detection signal 26 also becomes "High" level. It becomes High level, and the N-channel MOS transistor of the power supply short circuit 218 turns on.

As a result, the power supply and the ground potential are connected (short-circuited) via the N-channel MOS transistor, and the power supply voltage is reduced to the operation lower limit voltage of the semiconductor integrated circuit 217 or lower, and normal operation cannot be performed. This makes it impossible to access the internal circuit using the test external terminal group 21, read out data written in the IC card, perform any operation such as erasing / writing, and perform electrical analysis. .

As described above, according to the present embodiment, after shipment to the market, the transfer gate group 28 is electrically disconnected to prevent the test external terminal group 21 from accessing the internal circuit 216. Further, when an unauthorized signal (a signal of “High” level) is applied from one or more terminals of the test external terminal group 21 and the unauthorized access detection signal 26 becomes “High” level, the semiconductor integrated circuit 217 is activated. Will not work properly.
In the shipping inspection process, the test external terminal group 2
1 makes it possible to efficiently inspect each function of the internal circuit 216 in the semiconductor integrated circuit 217 incorporated in the IC card, and realize a high failure detection rate in a short time. It becomes possible.

Third Embodiment Next, a third embodiment of the present invention will be described with reference to FIG.

FIG. 3 is a circuit diagram of an I / O according to a third embodiment of the present invention.
FIG. 4 is a detailed layout diagram around a power supply short circuit provided in a semiconductor integrated circuit built in a C card. In FIG. 3, reference numeral 31 denotes a power supply terminal, 32 denotes a ground terminal, 33 denotes a power supply short circuit, 33p denotes a power supply wiring for a power supply short circuit,
g is a ground wiring for a power supply short circuit, 34a, 34b, 3
Reference numerals 4c and 34d denote illegal cutting points when attempting to cut illegally using a device such as a laser cutter or FIB.
5p is a power supply diffusion layer-wiring interlayer contact window, 35g is a ground diffusion layer-wiring interlayer contact window, 36 is a diffusion layer,
Reference numeral 37 denotes a power supply short circuit control gate electrode, and reference numeral 38 denotes an internal circuit.

Next, the layout and operation of the power supply short circuit 33 in the semiconductor integrated circuit thus configured will be described.

First, regarding the layout, as shown in FIG. 3, a power supply terminal 31, a ground terminal 32 and an internal circuit 38 are provided.
The power supply short circuit 33 is arranged between the power supply short circuit 33 and the power supply short circuit 33.

At this time, a person who attempts unauthorized access attempts to avoid a short circuit between the power supply and the ground potential, first of all, the power supply short circuit power supply wiring 33p of the power supply short circuit 33.
The power supply terminal 31 side of the illegal disconnection point 34a to be disconnected from now and the internal circuit 38 side of the illegal disconnection point 34b to be disconnected from the
The connection is made with tungsten using a device such as B.

Thereafter, the illegal cutting point 34a and the illegal cutting point 3
By illegally cutting each of 4b using a device such as a laser cutter or FIB, the power supply short circuit power supply wiring 33p side of the power supply short circuit 33 is functionally disconnected from the power supply short circuit 33.

Similarly, the power supply short circuit 33 on the side of the power supply short circuit ground wiring 33g and the ground terminal 32 on the illegal disconnection point 34c to be disconnected from the power supply short circuit 33g, and the illegal disconnection from the same. When the point 34d is connected to the internal circuit 38 side with tungsten, and then each point is disconnected, the power short circuit 33 side of the power short circuit ground line 33g is also functionally disconnected from the power short circuit 33.

However, the power supply from the power supply terminal 31 and the ground terminal 32 to the internal circuit 38 becomes unstable due to illegal processing, the internal circuit 38 does not operate normally, and
Weakness to noise.

As described above, according to the present embodiment, the security is further improved against making it impossible to access or operate the internal circuit 38 due to unauthorized access by the test external terminal group 21. Can be realized.

(Fourth Embodiment) Next, a fourth embodiment of the present invention will be described with reference to FIG.

FIG. 4 is a block diagram showing a fourth embodiment of the present invention.
FIG. 4 is a detailed layout diagram around a power supply short circuit provided in a semiconductor integrated circuit built in a C card. In FIG. 4, 41 is a power supply terminal, 42 is a ground terminal, 43 is a power supply short circuit, 44a, 44b, 44c, 44d are illegal cutting points when an illegal cutting is attempted using a device such as a laser cutter or FIB, 45p is a power diffusion layer-interlayer contact window, 45g is a ground diffusion layer-interlayer contact window, 46 is a power supply short circuit control gate electrode, 47 is a diffusion layer, 48 is an internal circuit gate electrode, and 49 is an internal circuit gate electrode.
Is an internal circuit, 410 and 411 are transistors indispensable for the operation of the internal circuit 49, 412 is a ground wiring, and 413 is a power supply wiring.

Next, the layout and operation of the power supply short circuit 43 in the semiconductor integrated circuit thus configured will be described.

First, regarding the layout, the power supply terminal 41
A power supply short circuit 43 is arranged between the ground terminal 42 and the internal circuit 49, and the power supply short circuit 43 further includes a transistor 410 indispensable for the operation of the internal circuit 49,
The diffusion layer 47 is shared with a part of the diffusion layer 47.

At this time, in order to avoid a short circuit between the power supply and the ground potential, first, the unauthorized access point tries to avoid the short circuit between the power supply terminal and the ground potential on the power supply terminal side.
Is illegally cut using a device such as a laser cutter or FIB, and then the illegal cutting point 44a and the illegal cutting point 44b are directly connected, the operation of the transistor 410 which is indispensable for the operation of the internal circuit 49 is also reduced. Impossible.

Also, in the case of the ground terminal 42 side, the power supply terminal 4
In the same manner as the first side, the illegal cutting point 44c and the illegal cutting point 44
If both points 44c and 44d are directly connected after cutting each of d, the operation of the transistor 411 which is indispensable for the operation of the internal circuit 49 becomes impossible.

As described above, according to the present embodiment, further security is provided against making it impossible to access or operate the internal circuit 49 due to unauthorized access using the test external terminal group 21. Can be improved.

(Fifth Embodiment) Next, a fifth embodiment of the present invention will be described with reference to FIGS.

FIG. 5 is a circuit diagram of an I-type semiconductor device according to a fifth embodiment of the present invention.
FIG. 4 is a detailed layout diagram of a periphery of a power supply short circuit provided in a semiconductor integrated circuit built in a C card. In FIG. 5, reference numeral 51 denotes a lower wiring layer, 52 denotes an upper wiring layer,
53 is polysilicon.

Next, the layout and operation of the power supply short circuit 218 (FIG. 2) in the semiconductor integrated circuit thus configured will be described.

First, with regard to the layout, in the fifth embodiment, in order to make it more difficult to avoid a short circuit between the power supply and the ground potential in the fourth embodiment, the power-on reset circuit 210 shown in FIG. A switching circuit 211, a test mode control memory area 214,
A power supply short circuit 218, an external input detection circuit 24,
Unauthorized access detection circuit 25 and transfer gate group 2
8 and a wiring layout of signals and power supply between these circuits are constituted by a lower wiring layer 51, and an upper wiring layer 52 provided on the lower wiring layer 51 is essential for the operation of the internal circuit 216. Configure the wiring layout of the signals and power supply. Then, a layout is formed such that the upper wiring layer 52 covers the wiring layout of all the circuits constituted by the lower wiring layer 51 and the signal and power supply between the circuits with the upper wiring layer 52.

With this wiring layout, in order to avoid a short circuit between the power supply and the ground potential at the time of an illegal access,
If an attempt is made to disconnect the power supply-ground potential of the power supply short circuit 218, or if the test mode control signal 27, the unauthorized access detection signal 26, etc.
Signals and power supplies necessary for the operation of the internal circuit 216 are cut off first, making the operation of the semiconductor integrated circuit 217 impossible.

As described above, according to the present embodiment, the fourth
In this embodiment, access to the internal circuit 216 due to improper access via the test external terminal group 21 and the operation of the internal circuit 216 are not allowed.

[0070]

As described above, according to the present invention, when an illegal input signal is input to the internal semiconductor integrated circuit from the outside after the IC card is shipped to the market, the semiconductor nonvolatile circuit Access to an internal circuit including the memory is prohibited, and stored information in the semiconductor nonvolatile memory is erased. Alternatively, when an incorrect input signal is input, a short circuit between the power supply and the ground potential makes any operation of the internal semiconductor integrated circuit impossible. Further, even if an attempt is made to avoid a short circuit between the power supply and the ground potential and to illegally disconnect the power supply and the control signal wiring of the short path between the power supply and the ground potential, the signals and the power supply indispensable to the internal circuit are cut off. Will be.

For this reason, after shipment to the market, the operation of the internal circuit by the test external terminal group cannot be performed at all, and it is not possible to read out or falsify data written in the semiconductor nonvolatile memory. Becomes Also, in the shipping inspection process, by making the test external terminal group available, each function of the semiconductor integrated circuit can be efficiently inspected, and a high failure detection rate can be realized in a short time. I, which has very high security
A C card can be realized.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a semiconductor integrated circuit built in an IC card according to a first embodiment of the present invention;

FIG. 2 is a configuration diagram of a semiconductor integrated circuit built in an IC card according to a second embodiment of the present invention;

FIG. 3 is a detailed layout diagram around a power supply short circuit provided in a semiconductor integrated circuit built in an IC card according to a third embodiment of the present invention;

FIG. 4 is a detailed layout diagram around a power supply short circuit provided in a semiconductor integrated circuit built in an IC card according to a fourth embodiment of the present invention;

FIG. 5 is a detailed layout diagram around a power supply short circuit provided in a semiconductor integrated circuit built in an IC card according to a fifth embodiment of the present invention;

FIG. 6 is a configuration diagram of a semiconductor integrated circuit built in a conventional IC card.

[Explanation of symbols]

11a, 11b, 11n, 21a, 21b, 21n Test external terminals 11, 21, Test external terminal group 12a, 12b, 12n, 22a, 22b, 22n Internal pull-down resistor 13, 23 OR circuit 14, 24 External input detection circuit 14a , 24a External input detection signal 15, 25 Unauthorized access detection circuit 16, 26 Unauthorized access detection signal 17, 27 Test mode control signal 18, 28 Transfer gate group 19, 29 Operation control circuit 110, 210 Power-on reset circuit 111, 211 Test Mode switching circuit 112, 212 Test mode control memory read data 113, 213 Erasing / writing circuit 114, 214 Test mode control memory area 115, 215 Semiconductor nonvolatile memory 116, 216 Internal circuit 117, 217 Semiconductor Integrated circuit 218 Power supply short circuit 218p Power supply short circuit power supply wiring 218g Power supply short circuit ground wiring 31, 41 Power supply terminal 32, 42 Ground terminal 33, 43 Power supply short circuit 33p Power supply short circuit power supply wiring 33g Power supply short circuit ground wiring 34a, 34b, 34c, 34d, 44a, 44b, 4
4c, 44d Illegal cutting point 35p, 45p Power supply diffusion layer-interlayer contact window 35g, 45g Ground diffusion layer-interlayer contact window 36, 47 Diffusion layer 37, 46 Power supply short circuit control gate electrode 38, 49 Internal circuit 48 Gate electrode for internal circuit 410 Transistor indispensable for operation of internal circuit 49 411 Transistor indispensable for operation of internal circuit 49 412 Ground wiring 413 Power supply wiring 51 Lower wiring layer 52 Upper wiring layer 53 Polysilicon

Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat II (reference) G11C 17/00 G01R 31/28 V 5B035 16/02 W 5L106 29/00 673 B G11C 17/00 601P F term (reference) 2G132 AA09 AA18 AK11 AK15 AK22 5B003 AB05 AD03 AD09 AE04 5B017 AA07 BA08 BB03 CA14 5B018 GA10 HA26 MA24 NA06 PA03 QA13 5B025 AD04 AD08 AD09 AD14 AE09 AE10 5B035 AA13 BB09 BC08 CA12 CA38 5L106A

Claims (5)

[Claims] 1. An IC card having a built-in semiconductor integrated circuit, wherein the semiconductor integrated circuit has a test external terminal group for applying an external signal to test the operation of the semiconductor integrated circuit; A transfer gate group for electrically connecting and disconnecting an external terminal group and an internal circuit; a test mode switching circuit for controlling switching between a normal operation mode and a test mode; and a test mode control signal output from the test mode switching circuit Indicates a normal operation mode, and when a signal of a predetermined level is applied to the test external terminal group, an unauthorized access detection circuit that detects that an unauthorized signal has been input; and An erasing / writing circuit for erasing the storage contents of the semiconductor nonvolatile memory device provided in the internal circuit when detecting an incorrect input signal; IC card characterized by comprising. 2. The semiconductor integrated circuit includes a power supply short circuit that short-circuits between a power supply and a ground potential when the unauthorized access detection circuit detects an illegal input signal from the test external terminal group. 2. The method according to claim 1, wherein
The described IC card. 3. The IC card according to claim 2, wherein the power supply short circuit is arranged between an external terminal corresponding to a power supply line and a ground line, respectively, and the internal circuit. 4. The IC card according to claim 3, wherein the power supply short circuit has a power supply line and a ground line common to the internal circuit, and a diffusion layer forming a transistor. 5. A power-on reset circuit for generating a reset signal when a power supply is turned on,
An external input detection circuit that detects an input signal from the test external terminal group and outputs a detection result to the unauthorized access detection circuit, wherein the semiconductor nonvolatile memory device controls the test mode switching circuit. A power-on reset circuit, the external input detection circuit, the test mode control memory area, the test mode switching circuit, and the power supply short circuit. The unauthorized access detection circuit, the transfer gate group, and the wiring layout of signals and power supply between these circuits are constituted by a lower wiring layer, and the lower wiring layer is indispensable for the operation of the internal circuit. 5. The IC card according to claim 4, wherein the IC card is covered by a wiring layout of a signal and a power supply.