JP2002269163A - Device, method and program for supporting design - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a design supporting device capable of speedily and easily dividing the processing function of a system to hardware and software. SOLUTION: At least one parameter for evaluating the processing function division of the system is inputted and on the basis of the input parameter, a division index is calculated. On the basis of the calculated division index, the candidates of a processing function for changing the division from hardware to software or from software to hardware are determined, and the system processing function is divided again by changing the division of the candidates. Concerning the result of re-division, the simulation of performance evaluation is performed and this is repeated until a design limitation is satisfied. As a division index, a ratio between estimated processing time in the case of software and an estimated number of gates in the case of hardware or the product of estimated processing time in the case of software and a CPU waiting time is to be used.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the support of hardware / software co-design of an arithmetic processing system such as a computer, and an apparatus, a method and a program for supporting a design for dividing a processing function of a system into hardware and software. About.

[0002]

2. Description of the Related Art Systems widely used in home electric appliances and office equipment are generally embedded systems composed of hardware and software. The embedded system includes an ASIC, a CPU, a memory, and the like. In the design of an embedded system, it is necessary to divide the specifications describing the processing functions of the entire system into a part that is implemented by hardware using an ASIC or the like and a part that is implemented by software as a program executed by the CPU. This is called hardware / software function division. In the case of such hardware / software function division, ASIC, CP
Estimate the cost such as the number of gates and performance of the entire system such as U and memory, and divide the processing functions of the system into hardware and software so as to satisfy the design constraints such as chip area and time performance given in advance by the designer. There is a need.

Conventionally, the hardware / software function division has been solved by the intuition and experience of a skilled system designer. However, due to the advancement of computer performance, the spread of programmable devices with easy architecture evaluation, and the development of CAD tools, Due to the current situation such as the possibility and necessity of an integrated CAD environment, hardware / software function partitioning as a method of systematically designing a system based on a quantitative method is being researched and developed. For example,
A. "Hardware / Software Partitio" by Kalavade
ning for Multifunction Systems, IEEE TRANSACTI0NS
ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AN
D SYSTEMS, VOL.17, NO.9, SEPTEMBER 1998 ”, the processing function of the system can be calculated statically with the processing time of each function and the area ratio when hardware is installed. The division is determined based on a comparison with the processing time of the entire system. However, when it is difficult to statically calculate the processing time of the entire system, hardware / software function division based on a quantitative method cannot be performed.

As disclosed in Japanese Patent Application Laid-Open No. 2000-57199, there is known an apparatus for performing system design by accurately estimating the performance of the entire system in hardware / software function division by simulation and checking design constraints. is there. However, with this apparatus, a huge number of simulations are required in subdividing the functions of the system, and a division plan that improves the performance of the system cannot be quickly determined.

[0005] In a large-scale and complicated system in which it is difficult to statically calculate the processing time of the entire system, it is not easy to divide the functions of hardware and software.
Furthermore, in a system in which a large number of division plans are considered, there is a problem that a division plan that is expected to improve performance cannot be uniquely determined, the number of simulations increases, and the design period becomes longer.

[0006]

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and provides a design support apparatus and a design support system capable of quickly and easily dividing the processing functions of a system into hardware and software. The purpose is to provide a support method and a design support program.

[0007]

In order to solve the above-mentioned problems and achieve the object, the present invention is configured as follows.

According to a first aspect of the present invention, there is provided a design support apparatus for supporting a design for dividing a processing function of a system into hardware and software, wherein at least one parameter for evaluating the division is input. Means for calculating a division index based on the input parameters; and a processing function for changing the division from hardware to software or from software to hardware according to a priority order based on the calculated division index. Means for determining at least one candidate; and means for changing the division of the candidate and re-dividing the processing functions of the system.

According to the design support apparatus of the first aspect, hardware constraints, software constraints, and the like are input as parameters, and a division index is calculated in consideration of a trade-off between hardware and software. , By outputting a value for judging the quality of the division of each processing function of the system, and obtaining a candidate of the processing function for changing the division from hardware to software or from software to hardware according to the output result according to the priority order. In addition, the subdivision for improving the performance of the system can be uniquely performed, the number of performance simulations for performing the performance evaluation for each division can be reduced, and the system can be quickly designed.

As a more specific configuration, a ratio between a processing time predicted when the processing function is implemented by software and a gate number predicted when the processing function is implemented by hardware is used as the division index. , The processing time expected when the processing function is implemented by software, and the CP
The product of the U waiting time may be used as the division index.

According to a fourth aspect of the present invention, there is provided a design support method comprising:
In a method for supporting a design of dividing a processing function of a system into hardware and software, inputting at least one parameter for evaluating the division, and calculating a division index based on the input parameter. And, according to the priority based on the calculated division index, determining at least one candidate of the processing function to change the division from hardware to software or from software to hardware, and change the division of the candidates Performing a subdivision of the processing functions of the system.

According to a fifth aspect of the present invention, there is provided a design support program for supporting a design in which a processing function of a system is divided into hardware and software, wherein a computer inputs at least one parameter for evaluating the division. Means for calculating a division index based on the input parameters; and at least one of the processing functions for changing the division from hardware to software or from software to hardware according to a priority order based on the calculated division index. Means to determine one candidate,
A program for functioning as means for changing the division of the candidates and re-dividing the processing functions of the system.

[0013]

Embodiments of the present invention will be described below with reference to the drawings.

(First Embodiment) FIG. 1 shows a first embodiment of the present invention.
1 is a block diagram illustrating a schematic configuration of a design support device according to an embodiment. This device divides these processing functions into hardware and software when a designer describes the specifications of each processing function constituting a system to be designed.

A processing function description unit 101 describes a (operation) specification of a system to be designed,
The software function division unit 102 is a processing function description unit 101
For dividing the processing function of the system described in (1) into hardware and software,
Numeral 03 denotes a part for simulating the processing functions divided by the hardware / software function dividing unit 102. The result display unit 104 is a simulation execution unit 103
The performance of the system simulated in (here,
Time performance value and total number of gates).

Here, the "processing function" of the system refers to a processing or function which is a component of the system, and a function which can be described in the processing function description unit 101. Also,
“Dividing” a processing function into hardware and software means determining whether each processing function is realized by hardware or software. When the design is completed, each processing function as an abstract concept described as a specification is assigned to either hardware or software.

The evaluation parameter input unit 105 inputs a parameter used for calculation of a division index. The division index calculation unit 106 calculates the performance result simulated by the simulation execution unit 103 and the evaluation parameter input unit 1.
In step 05, a division index is calculated using parameters input from a designer or the like. The subdivision candidate output unit 107 outputs a processing function candidate for performing subdivision of the processing function of the system based on the result calculated by the division index calculation unit 106.

FIG. 2 shows an example of a system described by the processing function description section 101. This system is composed of seven processing blocks from processing 1 to processing 7.
First, processing 1 for the first data input is started.
When this processing 1 is completed, processing 2 and processing 4 are started. When the process 2 ends, the process 3 starts, and when the process 4 ends, the process 5 starts and the process 1 for the next input starts. When processing 3 and processing 5 are completed, processing 6
Is started, and when the processing 6 is completed, the processing 7 is started. When the process 7 is completed, data is output. The above processing is repeated until outputs for all inputs are obtained.

Hardware / software function division unit 1
In 02, the processing blocks of the system as shown in FIG. 2 are divided into hardware and software. Initially,
Since there is no input from the subdivision candidate output unit 107, for example, all processing blocks are divided into software.

The simulation execution unit 103 performs scheduling of processing blocks of the system divided by the hardware / software function division unit 102, and performs a performance simulation. The scheduling method is
For example, FIFO (First In First Out) or priority order scheduling is used.

The result display unit 104 displays the result of the performance of the system executed by the simulation execution unit 103. For example, for 100 input data, the processing time required to obtain 100 output data, the total number of gates of the system, and the like are displayed.

The evaluation parameter input unit 105 inputs parameters used for calculating a division index. For example,
The processing amount of each processing block shown in FIG. 2 and the number of gates predicted when each processing block is implemented in hardware are shown. Also, power consumption, CPU waiting time when processing blocks are scheduled, time deadline, code size when software is implemented, system chip area, buffer size, or when processing blocks are repeatedly executed May be input as a parameter.

The division index calculation unit 106 calculates the division index based on the parameters input by the evaluation parameter input unit 105 and the performance results obtained by the simulation execution unit 103.
Calculate the division index. For example, when a processing amount parameter when each processing block is implemented by software and a predicted number of gates parameter when each processing block is implemented by hardware are input to the evaluation parameter input unit 105, the simulation execution unit 103 The processing amount and the predicted gate number are referred from the performance result, and the processing amount / predicted gate number is calculated for each processing block, and each is set as a division index value of each processing block.

The re-partition candidate output unit 107 determines whether each processing block should be divided into software or hardware based on the division index value calculated by the division index calculation unit 106. Then, processing block candidates to be re-divided are output with priorities. For example, assume that the processing amount of each processing block, the number of predicted gates, and the processing amount / predicted gate number calculated as the division index calculated by the division index calculation unit 106 are as shown in FIG. From the results shown in FIG. 3, priority is given to processing blocks having large values of processing amount / number of gates, and these processing blocks are output as candidates to be divided into hardware.

Returning to the hardware / software function dividing unit 102 again, the subdivision candidate output unit 107 redivides the processing blocks of the system from the subdivision candidates.
The simulation is performed by the simulation execution unit 103. For example, the process 205 having the highest priority is subdivided from software to hardware, and a simulation is performed. This is repeated until a performance simulation result that satisfies the design constraint given in advance is obtained.

As described above, by calculating the division index using the evaluation parameters and outputting the processing block of the re-division candidate, it is possible to easily evaluate one division plan of the system. The next division plan for improving system performance can be uniquely determined, and the number of simulations of hardware / software function division can be reduced.

(Second Embodiment) Next, a second embodiment of the present invention will be described with reference to FIGS. This second
The embodiment shows a division plan obtained by hardware / software function division with respect to the example of the system of FIG. 2 shown in the first embodiment. FIG. 4 shows performance simulation result display items for each division plan and design constraints previously given to each item. FIG.
FIG. 6 is a diagram showing processing blocks divided into software and processing blocks divided into hardware for each division plan. FIG. 6 is a diagram showing simulation results for each division plan. Here, the time performance value used as a design constraint is a value relating to the processing time of the entire system, and in the present embodiment, is a frame rate relating to image display.

First, all processing blocks are divided into software in the hardware / software function dividing unit 102. The result of performing a simulation on the division plan 301 by the simulation execution unit 103 does not satisfy the design constraint as indicated by the division index 401 in FIG. 6 (the time performance value is “9.7” and is a design constraint). Since the total number of gates is “0”, the design constraint “80 or less” is satisfied.
The re-division candidate output unit 107 determines which processing block is to be divided into hardware. FIG. 3 shows reordering candidates with priorities obtained according to the determination result. Here, as shown in FIG.
5 is divided into hardware. Similarly, this division plan 30
As a result of the simulation performed on No. 2 does not satisfy the design constraint as indicated by the division index 402, the re-division candidate output unit 107 further determines a processing block to be divided into hardware. According to FIG. 3, the process 204 having the next highest priority after the process 205 is divided into hardware. Similarly, a result of performing a simulation on the division plan 303 is indicated by a division index 403. Further, the subdivision candidate output unit 107 determines a processing block to be divided into hardware, and the priority is set to processing 2
The process 206, which is the next highest in 04, is divided into hardware.
The simulation result for the division plan 304 shows that the time performance value satisfies the design constraint as indicated by the division index 404, but the total number of gates is 80 or more, which does not satisfy the constraint. Therefore, the processing 20 in the subdivision candidate output unit 107
6 is divided into software, and the process 202 having the next largest division index value after the process 206 is divided into hardware. The simulation result for the division plan 305 satisfies the design constraint as indicated by the division index 405 (the time performance value is “32.8” and the design constraint is “30 or more”).
Meet. Further, the total number of gates is “65”, which satisfies the design constraint of “80 or less”. That is, the division plan 305 for the example of the system in FIG. 2 is obtained as a solution.

As the division plan for the example of FIG. 2, there are 2 7 ways, that is, 128 ways. However, it is possible to calculate the division index value as in the present invention and perform the subdivision based on the calculated index value. It is possible to obtain a division plan that satisfies the design constraints with a relatively small number of simulations (here, five times), thereby shortening the design period.

Third Embodiment Next, a third embodiment of the present invention will be described with reference to FIGS. In the third embodiment, a division plan obtained by dividing hardware / software functions of a system using a division index different from the division index shown in the second embodiment.
FIG. 7 is a diagram illustrating a configuration of a simulation model for simulating a processing block divided into software. Software processing block group 501
Is a processing block group divided by software. The software simulation model 502 is a simulation model for simulating each processing block of the software processing block group 501. The queue model 503 includes the software processing block group 50
This is a model in which each processing block is queued.
The CPU model 504 is a model that schedules each processing block of the queue model 503 and simulates one of them. Time performance value calculation unit 505
Is a part for calculating the time performance value of each processing block of the software processing block group 501. The simulation result output unit 506 is a unit that outputs a simulation result.

First, the software processing block group 501
Are queued by the queue model 503 when the simulation is executed. At this time, the time at which each processing block is queued is stored in the model. Next, scheduling is performed by the CPU model 504, and one processing block is simulated. The scheduling method is, for example, a FIFO or priority order algorithm. At this time, the start time at which the processing block was simulated is stored in the model.
Next, the time performance value calculation unit 505 calculates a time at which the processing block is queued and a simulation start time by the CPU model 504. For example, by subtracting the queued time from the simulation start time, the time during which the processing block waited for the CPU can be obtained. This calculation result is output to the simulation result output unit 506.
Output as a simulation result.

By using such a simulation result, the processing amount parameter of each processing block and the CPU waiting time parameter of each processing block are set in the evaluation parameter input unit 105 of FIG. It is possible to calculate the product of the processing amount and the CPU waiting time at 106 as a division index, and to obtain a candidate for a processing block to be re-divided at the subdivision candidate output unit 107 using this division index. It should be noted that the priority of the processing block candidate to be re-divided into the hardware is 1 with a large division index value.
Top priority is high. The fact that the product of the CPU waiting time and the processing amount is large implies that the load on the CPU is large when implemented as software, which may affect other processes. Performance improvement is expected. As described above, by performing evaluation using the simulation result of the software model as the division index, it is possible to output a candidate for subdivision of the processing function, and it is possible to easily perform subdivision of the system.

FIG. 8 summarizes the operation of the design support apparatus of the first to third embodiments as described above.

First, in step S1, the processing functions of the system are described.

Next, in step S2, an evaluation parameter and a design constraint are input. The evaluation parameters include, for example, the processing amount of each processing block, the number of gates predicted when implemented in hardware, and the CPU of the processing block.
The waiting time and the like, and the design constraints are the time performance value of the system and the total number of gates.

Next, in step S3, all processing blocks are divided into software as initial division.

Next, in step S4, a simulation for the division plan is executed.

Next, in step S5, it is determined whether or not the design constraint is satisfied, and if so, the process ends. If the design constraint is not satisfied, a division index value is calculated in step S6. The division index value uses the evaluation parameter input in step S2 and the simulation execution result in step S4, for example, the processing amount of processing block / the number of gates (first and second embodiments) and the processing amount of processing block. This is a calculated value such as a product of the CPU waiting time (third embodiment).

Next, in step S7, a priority-set candidate of a processing block to be divided into hardware is output.

Next, in step S8, step S7
A processing block to be re-divided into hardware is determined from among the candidates output in step, and the system is re-divided. The processing block is determined, for example, by selecting the processing block having the highest priority. The simulation is again performed on this new division plan in step S4, and this is repeated until a division plan satisfying the design constraint is obtained.

The embodiment described above can be realized as software, and is for causing a computer to execute predetermined means (or for causing a computer to function as predetermined means, or for causing a computer to realize predetermined functions). ) May be implemented as a program, or as a computer-readable recording medium on which the program is recorded.

It should be noted that the configuration exemplified in the embodiment of the present invention is an example, and is not intended to exclude other configurations, and a part of the illustrated configuration is replaced with another one or illustrated. Another configuration obtained by omitting a part of the configuration, adding another function or element to the illustrated configuration, or combining them is also possible. Also, another configuration that is logically equivalent to the illustrated configuration,
Another configuration including a portion logically equivalent to the illustrated configuration, another configuration logically equivalent to a main part of the illustrated configuration, and the like are also possible. Further, another configuration that achieves the same or similar purpose as the illustrated configuration, another configuration that achieves the same or similar effect as the illustrated configuration, and the like are also possible. Various variations of the various components exemplified in the embodiments of the present invention can be implemented in appropriate combinations. Further, the embodiments of the present invention relate to an invention as an individual device, an invention about two or more related devices, an invention as a whole system, an invention about components inside an individual device, or a method corresponding thereto. It encompasses and includes inventions related to various aspects, stages, concepts or categories, such as inventions. Therefore, the present invention can be extracted from the contents disclosed in the embodiments of the present invention without being limited to the illustrated configuration.

[0043]

As described above, according to the present invention,
It is possible to uniquely determine the subdivision of the system,
Furthermore, the number of simulations for the system division plan can be reduced, and the processing functions of the system can be quickly and easily divided into hardware and software.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a schematic configuration of a design support apparatus according to an embodiment of the present invention.

FIG. 2 is a diagram showing an example of a system to be designed described in a processing function description unit according to the embodiment.

FIG. 3 is a diagram showing calculation results and priorities of division indices according to the embodiment.

FIG. 4 is a diagram showing a processing amount and a predicted gate number of each processing block according to the embodiment.

FIG. 5 is a diagram showing a hardware / software division plan according to the embodiment;

FIG. 6 is a diagram showing a simulation result for a division plan according to the embodiment.

FIG. 7 is a block diagram showing a schematic configuration of a simulation model of a processing block divided by software according to the embodiment;

FIG. 8 is a flowchart showing a hardware / software function division procedure according to the embodiment.

[Explanation of symbols]

 101 processing function description unit 102 hardware / software function division unit 103 simulation execution unit 104 result display unit 105 evaluation parameter input unit 106 division index calculation unit 107 re-division candidate output unit

Claims (5)

[Claims] 1. An apparatus for supporting a design for dividing a processing function of a system into hardware and software, comprising: means for inputting at least one parameter for evaluating the division; and based on the input parameter. Means for calculating a division index; means for determining at least one candidate of the processing function for changing the division from hardware to software or from software to hardware according to a priority order based on the calculated division index; Means for changing the division of the system and re-dividing the processing functions of the system. 2. The division index is a ratio between a processing time estimated when the processing function is implemented by software and a gate number estimated when the processing function is implemented by hardware. 2. The design support device according to 1. 3. The design support apparatus according to claim 1, wherein a product of a processing time estimated when the processing function is implemented by software and a CPU waiting time is used as the division index. 4. A method for supporting a design for dividing a processing function of a system into hardware and software, wherein at least one parameter for evaluating the division is input, and the division is performed based on the input parameter. Calculating an index, and determining at least one candidate of the processing function of changing the division from hardware to software or from software to hardware according to the priority order based on the calculated division index; and Changing the division and re-dividing the processing functions of the system. 5. A program for supporting design for dividing a processing function of a system into hardware and software, comprising: a computer for inputting at least one parameter for evaluating the division; Means for calculating a division index based on the above, according to a priority order based on the calculated division index, means for determining at least one candidate of the processing function for changing the division from hardware to software or from software to hardware, A design support program for functioning as means for changing the division of candidates and re-dividing the processing functions of the system.