JP2002262563A - Power-factor improving converter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve a power factor without the use of a multiplier for a reduction in price. SOLUTION: A trigger signal having a constant period is outputted from a control circuit 42 to an OR gate 43, and thus the switching period of a transistor Q1 is fixed. A differential amplified signal is outputted from an operational amplifier OP1, and is inputted to the negative terminal of a comparator COMP1. The drain current ID of the transistor Q1 is detected by a resistor R1. A signal V6 obtained by adding a slope compensation signal (V5) to a drain current detection signal (V4) is inputted to the positive terminal of the comparator COMP1, and the duty of the transistor Q1 is determined with a timing with which a signal V7 outputted from the comparator COMP1 is brought to high.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power factor correction converter, and more particularly, to a power factor correction converter capable of achieving miniaturization and high efficiency.

[0002]

2. Description of the Related Art A power factor is represented by power / (current × voltage), and is also called a phase difference between a current and a voltage of an AC circuit. In a converter, particularly a capacitor input type converter, although this phase difference is negligible, a harmonic component may be included in the input current in some cases.

FIG. 9 is an explanatory diagram showing input waveforms of a capacitor input type converter. In the capacitor input type converter, since a capacitor is inserted after the rectifying unit for rectifying the AC, as shown in FIG. 9, the pulsating current I rectified by the rectifying unit is originally a voltage V
When the waveform becomes the same as the waveform of (1), the conduction angle of the pulsating flow I becomes narrow, and many harmonic components are included. This harmonic component causes a reduction in the power factor. Since these harmonic components appear as noise disturbances, it is important to remove the harmonic components and improve the power factor in the converter.

[0004] In order to improve the power factor, conventionally, as a voltage control type, the speed of the feedback response under the voltage control is sufficiently lower than the input commercial frequency, and the inductor is operated in the critical mode. There is a power factor correction converter that controls a switching current output from a power supply. Further, as a current control type converter, there is a power factor improving converter that uses a multiplier for controlling a switching current and controls the switching current so that the switching current is in a critical mode.

FIG. 10 is a circuit diagram showing a configuration of a conventional current control type power factor correction converter. In this power factor correction converter, the AC output from the AC power supply 51 via the filter 52 is rectified by the bridge rectifier circuit 53 and input to the inductor L51 via the filter 54. When the transistor Q51 is turned on, energy is accumulated in the inductor L51, and when the transistor Q51 is turned off, energy is released from the inductor L51. Due to this energy release, a current flows to the capacitor C51 via the diode D51, and the capacitor C51 is charged. The current is smoothed and DC is output. A pulse for turning on / off the transistor Q51 is supplied to the operational amplifier OP51 (comparator operation) and the comparator CO
It is generated by the MP 51 and the flip-flop 55.

The voltage of the inductor L51 and its direction are
It is detected by the detection coil L52. The detected voltage is input to the operational amplifier OP51 via the resistor R54, and is compared with the reference voltage Vref51. As a result of the comparison, a differential amplified signal is output from the operational amplifier OP51, the differential amplified signal is delayed by the delay circuit 56, and the flip-flop 55 is set by the delayed signal output from the delay circuit 56.

The output voltage is compared with a reference voltage Vref 52 by an operational amplifier OP 52. As a result of the comparison, a differential amplified signal is output, and the differential amplified signal is input to a multiplier 57.

The input voltage of the inductor L51 is equal to the resistance of the resistor R5.
5, divided by R56 and input to the multiplier 57. The input signal is multiplied by the differential amplified signal output from the operational amplifier OP52. Thereby, the error between the input voltage and the output voltage is multiplied. In addition, the operational amplifier OP
Since the gain of 52 is set relatively small, a signal proportional to the input voltage is output from multiplier 57 in response to the fluctuation of the output voltage, and the value of this output signal is determined by the output of operational amplifier 52. Is done.

On the other hand, the drain current _ID is detected by a resistor R51 and converted into a voltage. The detected signal is
The comparator COMP51 compares the signal with the signal output from the multiplier 57.

The transistor Q51 is connected to an operational amplifier OP5
It is turned on by the signal output from 1 and the comparator C
The signal is turned off by a signal output from the OMP 51.

In such a power factor improving converter, when the detected output voltage is equal to or lower than a predetermined value defined by the reference voltage Vref52, the multiplier 57 outputs a signal proportional to the input voltage in accordance with the output voltage. Is output.

Therefore, when the output voltage is higher than a predetermined value,
A smaller signal is input to the negative-phase input of the comparator COMP51, and a reset signal is output from the comparator COMP51 to the flip-flop 55 so that the input current becomes smaller. When the output voltage is equal to or lower than the predetermined value, a reset signal is output from the comparator COMP51 to the flip-flop 55 so as to have a large input current.

When the release of the energy of the inductor L51 is completed, that is, when the voltage of the inductor L51 is inverted, a set signal is output from the comparator OP51, and the transistor Q51 is turned on. With such an operation, the input current waveform is made closer to the input voltage waveform to improve the power factor.

[0014]

By the way, in the conventional power factor improving converter, the switching current operates in the critical mode, so that the peak value of the switching current increases and the switching loss increases. For this reason, this switching loss causes a decrease in efficiency, and the inductor L51
It is also the cause of the increase. Also, this type of multiplier 57 is generally expensive, which also causes the converter price to increase.

SUMMARY OF THE INVENTION The present invention has been made in view of such a conventional problem, and it is an object of the present invention to provide a current control type converter having a power factor improving converter capable of achieving downsizing and high efficiency. Aim. Also, the present invention
An object is to provide an inexpensive power factor correction converter.

[0016]

To achieve this object, a power factor improving converter according to a first aspect of the present invention comprises:
A rectifying unit that rectifies an alternating current to generate a pulsating current, an inductor that inputs the pulsating current rectified by the rectifying unit, and turns on and off based on a predetermined pulse signal to change a current flowing through the inductor. A switching element to be
A pulse signal generation unit that generates a pulse signal for turning on and off the switching element, and smoothes a current output from the inductor based on energy stored in the inductor, and converts the smoothed current and voltage to DC. A DC output unit, a device current detection unit that detects an element current flowing through the switching element and outputs an element current detection signal, a slope signal generation unit that generates a slope signal having a predetermined slope, and the element A slope addition unit that adds a slope signal generated by the slope signal generation unit to the element current detection signal output from the current detection unit, and outputs a slope addition signal; and a slope addition signal output from the slope addition unit. Is compared with a predetermined reference level, and a comparison unit that outputs a comparison result, and a comparison result output from the comparison unit Zui it is obtained by the so comprises a duty setting portion, a for setting the duty of the pulse signal generated by the pulse signal generating unit.

According to this configuration, the element current flowing through the switching element has a gradient due to the inductor. This slope changes according to the rectified voltage rectified by the rectifier. When the rectified voltage is high, the slope of the element current becomes steep, and when the rectified voltage is low, the slope of the element current becomes gentle. Further, the element current can be compared with a predetermined reference level by adding the slope signal to the element current detection signal. Therefore, when the rectified voltage is high, the slope of the element current is steep, so that the pulse signal is narrow. When the rectified voltage is low, the slope of the element current is gentle and the pulse signal is wide. By setting the duty of the pulse signal based on the comparison result, the current waveform of the inductor becomes a waveform corresponding to the waveform of the rectified voltage, and the power factor is improved.

The slope adder may be constituted by a circuit in which a resistor and a capacitor are connected in series, or may be constituted by a buffer. A differential amplifier may be provided that outputs a differentially amplified signal whose level has been adjusted by differentially amplifying a predetermined signal as a predetermined target value to the comparison unit.

Also, an output voltage detection unit for detecting an output voltage of the DC output unit and outputting an output voltage detection signal, and a feedback for feeding back the output voltage detection signal output from the output voltage detection unit to the comparison unit And the feedback section may be configured by a detection voltage superimposing circuit that superimposes an output voltage detection signal on an element current detection signal.

Further, the output voltage detecting section is constituted by a light emitting element which emits light in an amount of light emission according to the detected output voltage and outputs the optical signal as an output voltage detection signal;
The detection voltage superimposing circuit may be configured by a light receiving element that receives light from the light emitting element as an optical signal and superimposes a signal flowing based on the amount of received light on an element current detection signal.

The element current detecting section may be constituted by a resistor for converting the element current of the switching element into a voltage. The inductor is formed of a primary coil, a primary coil and a secondary coil are insulated and wound at a predetermined winding ratio to form a transformer, and the DC output unit is connected to the secondary coil. Good.

[0022]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A power factor improving converter according to an embodiment of the present invention will be described below with reference to the drawings. First,
The power factor improving converter according to the first embodiment will be described. The power factor correction converter according to the first embodiment sets the duty of the switching transistor by comparing a value obtained by adding a slope compensation signal to a detection signal obtained by detecting a current flowing through the transistor using the output voltage as a reference voltage. , To improve the power factor.

FIG. 1 is a circuit diagram showing a configuration of the power factor correction converter according to the first embodiment. The power factor correction converter according to the first embodiment includes a main circuit 1, a current detection unit 2, an output voltage detection unit 3, and a control unit 4.

The main circuit 1 includes an AC power supply 11, a filter 12, a bridge rectifier circuit 13, a filter 14,
Inductor L, transistor Q1, and diode D5
And a capacitor C1. The current detection unit 2 is configured by a resistor R1. The output voltage detection unit 3 includes resistors R2 and R3. The control unit 4 includes a flip-flop 41 and a control circuit 4
2, an OR gate 43, an operational amplifier OP1, a comparator COMP1, diodes D6 and D7, a Zener diode D8, capacitors C2 and C3, and a resistor R
4 to R9. In the main circuit 1, the filter 12 is for removing power supply noise of an alternating current (AC) power supply 11 and is connected to the AC power supply 11.

FIG. 2 is a circuit diagram showing an example of the configuration of the filter 12. As shown in FIG.
Reference numeral 2 denotes a normal mode filter as shown in FIG. 2A or 2B or a common mode filter as shown in FIG. 2C.

The bridge rectifier circuit 13 is for rectifying alternating current and is composed of four diodes D1 to D4. The filter 14 is a filter for removing power supply noise, has the same configuration as the filter 12, and is connected to the bridge rectifier circuit 13. The inductor L inputs a pulsating current rectified by the bridge rectifying circuit 13 through the filter 14 and has a predetermined inductance, thereby accumulating energy according to a change in current and generating an electromotive force. Things. This inductor L is formed by a choke coil, and is connected to the positive electrode of the filter 14.

The transistor Q1 is constituted by an N-channel field effect transistor (FET).
By turning off, the current flowing through the inductor L is changed to excite electromotive force in the inductor L,
The drain is connected to the output terminal of the inductor L, and the source is connected to the negative electrode side of the filter 14 via the resistor R1.

The diode D5 is a diode for preventing the current stored in the capacitor C1 from flowing backward when the transistor Q1 is turned on, and has an anode connected to the inductor L.

The capacitor C1 smoothes the current input from the inductor L via the diode D5, and is connected between the output terminals Pout1 and Pout2.
The output terminal Pout2, the negative electrode of the filter 14, and the negative terminal of the capacitor are grounded.

In the current detector 2, the resistor R1 is a resistor for converting the drain (switching) current flowing through the transistor Q1 into a voltage to detect the drain current, and is connected between the source of the transistor Q1 and the ground. . In the output voltage detector 3, the resistors R2 and R3 are voltage-dividing resistors for detecting the output voltage, and are connected in series between the positive terminal of the capacitor (hereinafter referred to as "+ terminal") and the ground. .

In the control unit 4, the operational amplifier OP1 includes:
An amplifier that compares the output voltage divided by the voltage dividing resistors R2 and R3 with a reference voltage Vref1 and outputs a differential amplified signal, and has an inverting input terminal (hereinafter referred to as a “− terminal”). The reference voltage V is connected to a connection point between the resistors R2 and R3, and is applied to a non-inverting input terminal (hereinafter, referred to as a “+ terminal”).
ref1 is input.

The diodes D6 and D7 are voltage drop diodes connected in series in the same direction, and the anode of the diode D6 is connected to the output terminal of the operational amplifier OP1.

The comparator COMP1 has an operational amplifier O
Differential amplified signal output from P1 and transistor Q1
Flip-flop 41 based on the drain current flowing through
Is connected to the cathode of a diode D7 via a resistor R4 and grounded via a resistor 5.

The resistors R4 and R5 are connected to diodes D6 and D7.
This is a resistor for dividing the differential amplified signal whose voltage has dropped due to the above. The Zener diode D8 is a diode for overcurrent protection, and its cathode is connected to the comparator CO2.
It is connected to the-terminal of MP1 and its anode is grounded. The resistor R6 is a resistor for level adjustment, and is connected in series between the source of the transistor Q1 and the + terminal of the comparator COMP1.

The control circuit 42 generates a trigger signal for setting a switching cycle, outputs the trigger signal from a terminal P1, generates a slope compensation signal, and outputs the slope compensation signal from a terminal P2. It is. This slope compensation signal is a signal for adding a predetermined slope to the drain current of the transistor, and is a signal having a sawtooth waveform.

The flip-flop 41 includes a transistor Q
1 is an RS flip-flop for generating a pulse signal for turning on and off the control circuit 42, and its set (S) terminal is connected to the terminal P1 of the control circuit 42;
Is input as a set signal. The reset (R) terminal of the flip-flop 41 is connected to the output terminal of the comparator COMP1, and the flip-flop 41 resets the pulse signal based on the signal output from the comparator COMP1, and turns on and off the generated pulse signal. The off ratio, that is, the duty is set.

The OR gate 43 is connected to the terminal P of the control circuit 42.
OR operation of the trigger signal output from 1 and the pulse signal output from the Q terminal of the flip-flop 41 is performed,
The OR-operated pulse signal is output to the gate of the transistor Q1 and is connected to the terminal P1 of the control circuit 42 and the Q terminal of the flip-flop 41.

The terminal P2 of the control circuit 42 is connected to a connection point between the resistor R8 and the capacitor C2, the capacitor C2 is grounded, and a DC power supply having a reference voltage Vref2 is connected to the resistor R8.

The terminal P2 of the control circuit 42 is connected to a connection point between the resistors R6 and R7 via a resistor R9 and a capacitor C3 connected in series. This resistor R9
The capacitor C3 is a circuit for superimposing the slope compensation signal on the detection signal of the drain current of the transistor Q1.

Next, the operation of the power factor improving converter according to the first embodiment will be described. The AC generated by the AC power supply 11 is rectified by the bridge rectifier circuit 13 via the filter 12.

FIG. 3 is a waveform diagram of the rectified voltage rectified by the bridge rectifier circuit 13. The cycle of the rectified voltage is １ ／ of the cycle of the voltage of the AC power supply 11. This rectified voltage is input to the inductor L via the filter 14.

When the transistor Q1 turns on, energy is stored in the inductor L, and when the transistor Q1 turns off, energy is released. Turn on transistor Q1,
The pulse signal for turning off is generated by the control circuit 42, the flip-flop 41, and the OR gate 43.

FIG. 4 is a signal waveform diagram showing the operation of control unit 4. FIG. 4A shows a part of the rectified voltage output from the bridge rectifier circuit 13 (when the voltage rises). A trigger signal V1 is output from the terminal P1 of the control circuit 42, as shown in FIG. This trigger signal V1 is OR
Input to the gate 43. The switching cycle of the transistor Q1 is set by the cycle of the trigger signal V1.

On the other hand, the output voltage Vout is equal to the resistances R2 and R3.
Is divided by The divided signal V2 is an output voltage detection signal, and the signal V2 is input to the negative terminal of the operational amplifier OP1. Then, as shown in FIG. 4C, the signal level of the signal V2 is compared with the reference voltage Vref1 by the operational amplifier OP1, and as a result of the comparison, a differential amplified signal is output. The amplification degree of the operational amplifier OP1 is set such that the ripple of the differential amplified signal is much smaller than the ripple with respect to the output voltage Vout.
The differential amplified signal is almost at the DC level.

This differential amplified signal is supplied to diodes D6 and D6.
7, the voltage V3 is divided by the resistors R4 and R5, and the divided signal V3 as shown in FIG. 4D is input to the minus terminal of the comparator COMP1. This signal V
3 becomes the reference level of the signal V6 shown in FIG.

The drain current I of the transistor Q1 is
_D is voltage-converted by the resistor R1 to generate a signal V4 as shown in FIG. This signal V4 becomes a drain current detection signal, and has the same waveform as the drain current _ID .

On the other hand, from the terminal P2 of the control circuit 42, a signal V5 which is a slope compensation signal as shown in FIG.
Is output. This signal V5 is added to the signal V4 via the resistor R9 and the capacitor C3 to generate a signal V6 as shown in FIG.

Here, when the rectified voltage is low (from time t1 to time t1).
t2) and a high case (time t3 to t4),
When the rectified voltage is low, the slope of the drain current detection signal (V4) becomes gentle as shown in FIG. In this case, the time until the transistor Q1 is turned off increases, and the level of the slope compensation signal (V5) added to the drain current detection signal increases.

On the other hand, when the rectified voltage is high, the slope of the drain current detection signal (V4) becomes steep, and the time until the transistor Q1 turns off becomes short. In this case, the level of the slope compensation signal added to the drain current detection signal decreases. As described above, the level of the signal V6 is adjusted by adding the slope compensation signal to the drain current detection signal.

The generated signal V6 is supplied to the comparator CO
The signal V input to the + terminal of MP1 and input to the-terminal
Compared to 3. When the signal V6 reaches the signal level of the signal V3, the signal V7 output from the comparator COMP1 becomes a high level as shown in FIG.
The flip-flop 41 is reset. Therefore, the signal V shown in FIG.
8 is output.

Then, an OR operation is performed by the OR gate 43, and as a result of the operation, a pulse signal similar to the signal V8 is input to the gate of the transistor Q1.
This pulse signal becomes a gate signal of the transistor Q1, and when the gate signal is at a high level, the transistor Q1
Turns on, and when the gate signal is at a low level, the transistor turns off.

In the example shown in FIG. 4 (j), times t1 to t2
Then, the period from time t1 to time t11 is the on-period ton of the transistor Q1 in this period, the period from time t11 to time t2 is the off-period toff of the transistor Q1 in this period, and this ratio is the duty. .

During the on-period ton, the drain current _ID flows through the transistor Q1, and during the off-period toff, the current Ic flows through the diode C5 to the capacitor C1.

When the voltage at the output terminal of the inductor L is higher than the terminal voltage of the capacitor C1, the diode D
5 conducts, the capacitor C1 is charged, and when the output terminal voltage becomes lower than the terminal voltage of the capacitor C1, the reverse current of the current is prevented by the diode D5. Thus, the current Ic and the output voltage Vout output from the inductor L are smoothed, and the DC output voltage Vout is output from the terminals Pout1 and Pout2.

At time t1, the transistor Q
1 turns on, the drain current I _DGradually increases and time
At time t11, when the transistor Q1 is turned off,
Drain current I_DIs cut off and the current Ic is
It starts to flow to the condenser C1 at the flow rate.

Since the energy stored in the inductor L decreases with the passage of time, the current Ic gradually decreases. At time t2, the transistor Q1 turns on again before the current Ic becomes 0, so that the drain current _ID to which the current Ic is added flows through the transistor Q1. Current I
_{When L} continues to flow without becoming zero as described above, a so-called non-critical mode (or continuous mode) is obtained.

The cycle of the rectified voltage is about 50 to 60 Hz, and the switching cycle of the transistor Q1 is
0 kHz. Thus rectified voltage on the transistor Q1 in a shorter period than the period of, off, further, by adding the slope compensation signal to the drain current detection signal, the waveform of the current I _L a waveform corresponding to the rectified voltage,
Power factor is improved.

As described above, according to the present embodiment, the slope compensation signal is added to the drain current detection signal, the added signal is compared with the DC level signal based on the output voltage detection signal, and the duty is reduced. Because it is set, the power factor can be improved well. Further, since no multiplier is used, the power factor improving converter can be made inexpensive.

Since the resistor R9 and the capacitor C3 are used as an adding circuit for adding the slope compensation signal to the drain current detection signal, the slope compensation signal can be added to the drain current detection signal with a simple configuration. .

In the above embodiment, the AC is rectified using the bridge rectifier circuit 13. However, the rectifier is not limited to the bridge rectifier circuit, but may be a single-phase half-wave rectifier circuit. Alternatively, a single-phase center tap rectifier circuit, a single-phase voltage doubler rectifier circuit or the like may be used.

Although an N-channel FET is used as a switching element, it is not limited to this.
A P-channel FET, an NPN-type bipolar transistor, a PNP-type transistor, a thyristor, or the like can be used.

For generating a pulse signal, an oscillator for outputting a triangular wave, for example, by comparing the output triangular wave with a predetermined reference level without using the flip-flop 41, the control circuit 42 and the OR gate 43. , A circuit for generating a pulse signal. Also, for slope compensation, an oscillator that generates a sawtooth wave can be used without using the control circuit 42.

Next, a power factor improving converter according to a second embodiment will be described. The power factor improving converter according to the second embodiment uses a photocoupler for output voltage feedback, superimposes an output voltage detection signal on a drain current detection signal, compares the output voltage detection signal with a fixed reference level, and sets a duty. Thus, the output voltage is controlled together with the current.

FIG. 5 is a circuit diagram showing a configuration of a power factor correction converter according to the second embodiment. In FIG.
The output voltage detector 3 includes a photodiode 31a as a light emitting unit of the photocoupler 31, a transistor Q2, resistors R2, R3, R11, and a Zener diode D11.
And the control unit 4 includes the photocoupler 3
A phototransistor 31b is provided as one light receiving unit.

The photocoupler 31 is for detecting the output voltage Vout and superimposing the detected output voltage Vout on the drain current detection signal. Photodiode 31
“a” conducts and emits light at a light emission amount corresponding to the amount of current flowing, and the anode thereof is connected to the output terminal Pout1.

The transistor Q2 is an NPN-type bipolar transistor for conducting the photodiode 31a with a current amount corresponding to the output voltage Vout. The collector of the transistor Q2 is connected to the cathode of the photodiode 31a via a resistor R11. , Resistors R2 and R3. Note that the resistance values of the resistors R2 and R3 are set so that the transistor Q2 is turned on within a range for controlling the output voltage Vout.

The Zener diode D11 is connected to a transistor
Base-emitter voltage V _BECombined with
For setting the reference voltage for comparison.
The cathode is connected to the emitter of the transistor Q2,
The anode is grounded.

The collector of the phototransistor 31b is
The emitter is connected to the DC power supply of the reference voltage Vref2, and the emitter is connected to the connection point between the capacitor C3 and the resistors R6 and R7, whereby the output voltage detection signal is superimposed on the drain current detection signal.

In the second embodiment, the operational amplifier OP1
-Terminal is grounded, and the output differential amplified voltage has a constant value. In the comparator COMP1, the signal level of the signal input to the + terminal is compared with the differential amplified voltage. The same elements as those in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted.

Next, the operation of the power factor correction converter according to the second embodiment will be described. When the output voltage Vout exceeds a predetermined upper limit, the transistor Q2 is turned on by application of the base voltage.

When the transistor Q2 is turned on, a current flows through the photodiode 31a, and the photodiode 31a emits light according to the amount of current. The amount of current is an amount corresponding to the output voltage Vout.

The light when the photodiode 31a emits light is received by the phototransistor 31b, and the amount of current flowing through the phototransistor 31a is controlled by the amount of light received. Since the emitter of the phototransistor 31b is connected to the connection point between the resistors R6 and R7, the output voltage detection signal is superimposed on the drain current detection signal.

On the other hand, the negative terminal of the operational amplifier OP1 is grounded, and the differential amplified voltage input to the negative terminal of the comparator COMP1 is constant. This voltage becomes the reference level,
The signal level of the drain current detection signal on which the output voltage detection signal is superimposed is compared with this reference level.

As described above, according to the present embodiment, the detection signal of the output voltage Vout can be superimposed on the drain current detection signal using the photocoupler 31, and the input side and the output side can be insulated.

Next, a power factor improving converter according to a third embodiment will be described. The power factor improving converter according to the third embodiment is configured such that a buffer is connected to an output terminal of the control circuit that outputs a slope compensation signal.

FIG. 6 is a circuit diagram showing a configuration of a power factor correction converter according to the third embodiment. As shown in FIG. 6, the NPN-type bipolar transistor Q3 has a function as a buffer, its base is connected to the terminal P2 of the control circuit 42, and its collector is connected to the DC power supply of the reference voltage Vref2. , The emitter is a resistor R12
Is connected to a connection point between the resistor R6 and the resistor R7. The same elements as those in FIGS. 1 and 5 are denoted by the same reference numerals, and description thereof will be omitted.

Next, the operation of the power factor correction converter according to the third embodiment will be described. The slope compensation signal output from the terminal P2 of the control circuit 42 is output to the base of the transistor Q3, and the transistor Q3 turns on according to the signal level of the slope compensation signal.

As described above, according to the present embodiment, the control circuit 4
Since the buffer constituted by the transistor Q3 is connected to the terminal P2 for outputting the second slope compensation signal, the output impedance of the control circuit 42 can be reduced. In the present embodiment, N is stored in the buffer.
Although a PN-type bipolar transistor was used, the present invention is not limited to this. For example, a PNP-type bipolar transistor, an operational amplifier, or the like can be used.

Next, a power factor improving converter according to a fourth embodiment will be described. In the power factor correction converter according to the fourth embodiment, a transformer is configured with an inductor as a primary side coil.

FIG. 7 is a circuit diagram showing a configuration of a power factor correction converter according to the fourth embodiment. As shown in FIG. 7, the inductor L of the first embodiment is a primary coil of a transformer T, and the transformer T is wound at a predetermined turn ratio while the primary coil and the secondary coil are insulated. It is constituted by. One end of the secondary coil of the transformer T is connected to the anode of the diode D5,
The other end is connected to the negative electrode side of the capacitor C1. The same elements as those in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted.

Next, the operation of the power factor correction converter according to the fourth embodiment will be described. The pulsating flow rectified by the bridge rectifier circuit 13 is input to the primary coil of the transformer T via the filter 14. When the transistor Q1 is turned on, energy is accumulated in the primary coil of the transformer T. When the transistor Q1 is turned off, energy is released.
Due to this energy release, the current Ic flows to the capacitor C1 via the diode D5, and the capacitor C1 is charged.

As in the first embodiment, the output voltage Vout is divided by the resistors R2 and R3, and the signal obtained by adding the slope compensation signal to the drain current detection signal is the differential signal output from the operational amplifier OP1. It is compared with a DC level signal based on the amplified signal.

As described above, according to the present embodiment, the transformer T
, The primary side and the secondary side can be insulated from each other.

Next, a power factor improving converter according to a fifth embodiment will be described. The power factor improving converter according to the fifth embodiment uses a transformer and a photocoupler to completely insulate the primary side from the secondary side.

FIG. 8 is a circuit diagram showing a configuration of a power factor correction converter according to the fifth embodiment. The power factor improving converter according to the fifth embodiment uses a transformer T as in the fourth embodiment, and the photodiode 31a of the photocoupler 31 as in the second embodiment.
The output voltage Vout is detected based on the detected output voltage Vo.
ut is fed back to the primary side by the phototransistor 31b.

In the power factor improving converter according to the fifth embodiment, the reference voltage Vref1 is input to the minus terminal of the comparator COMP1 without using the operational amplifier OP1, and the detection signal of the drain current _ID of the transistor Q1 is output. The comparator COMP1 is configured to output a reset signal as compared with the reference voltage Vref1. The same elements as those in FIGS. 1, 5, and 7 are denoted by the same reference numerals, and description thereof is omitted.

Next, the operation of the power factor improving converter according to the fifth embodiment will be described. As in the fourth embodiment, when the transistor Q1 is turned on, energy is accumulated in the primary coil of the transformer T, and when the transistor Q1 is turned off, energy is released. Due to this energy release, current flows through the diode D5. The current flows to the capacitor C1, and the capacitor C1 is charged.

The output voltage detection signal and the slope compensation signal are superimposed on the drain current detection signal. Then, these signals are input to the + terminal of the comparator COMP1 via the resistor R7. Comparator COM
At P1, the signal input to the + terminal of the comparator COMP1 is compared with the reference voltage Vref1, and the duty of the pulse signal is determined.

As described above, according to the present embodiment, the transformer T
In addition, by using the photocoupler 31, the primary side and the secondary side can be completely insulated.

[0090]

As described above, according to the power factor improving converter according to the present invention, the power factor can be improved.
Moreover, the cost can be reduced.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of a power factor correction converter according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing an example of a configuration of the filter of FIG.

FIG. 3 is a waveform diagram of a pulsating flow rectified by the bridge rectifier circuit of FIG. 1;

FIG. 4 is a signal waveform diagram illustrating an operation of a control unit in FIG. 1;

FIG. 5 is a circuit diagram showing a configuration of a power factor correction converter according to a second embodiment of the present invention.

FIG. 6 is a circuit diagram showing a configuration of a power factor correction converter according to a third embodiment of the present invention.

FIG. 7 is a circuit diagram showing a configuration of a power factor correction converter according to a fourth embodiment of the present invention.

FIG. 8 is a circuit diagram showing a configuration of a power factor correction converter according to a fifth embodiment of the present invention.

FIG. 9 is an explanatory diagram showing an input waveform of a capacitor input type converter.

FIG. 10 is a circuit diagram showing a configuration of a conventional power factor correction converter.

[Explanation of symbols]

 Reference Signs List 11 AC power supply 13 Bridge rectifier circuit 41 Flip-flop 42 Control circuit Q1 Transistor (FET) L Inductor D1 to D4 Diode (for bridge rectifier circuit) D5 Diode (for backflow prevention)

Claims (9)

[Claims] 1. A rectifying unit for rectifying an alternating current to generate a pulsating flow, an inductor for inputting a pulsating current rectified by the rectifying unit, A switching element that changes a current flowing through the switching element; a pulse signal generation unit that generates a pulse signal for turning on and off the switching element; and smoothing a current output from the inductor based on energy stored in the inductor. A DC output unit that outputs the smoothed current and voltage as DC, an element current detection unit that detects an element current flowing through the switching element, and outputs an element current detection signal, and a slope signal having a predetermined slope. A slope signal generation unit to generate, and an element current detection signal output from the element current detection unit, the slope signal generation unit A slope addition unit that adds the slope signals generated by the above, and outputs a slope addition signal; a comparison unit that compares the slope addition signal output from the slope addition unit with a predetermined reference level, and outputs a comparison result; A power factor improving converter comprising: a duty setting unit that sets a duty of a pulse signal generated by a pulse signal generation unit based on a comparison result output from a comparison unit. 2. The power factor improving converter according to claim 1, wherein said slope adding section is constituted by a circuit in which a resistor and a capacitor are connected in series. 3. The power factor improving converter according to claim 1, wherein said slope adding section is constituted by a buffer. 4. A differential amplifier for differentially amplifying a predetermined signal to output a differentially amplified signal whose level has been adjusted as a predetermined target value to a comparing section.
The power factor improving converter according to any one of claims 1 to 3. 5. An output voltage detection unit for detecting an output voltage of the DC output unit and outputting an output voltage detection signal, and a feedback for feeding back an output voltage detection signal output from the output voltage detection unit to the comparison unit. Department and
The power factor improving converter according to any one of claims 1 to 4, further comprising: 6. The power factor improving converter according to claim 5, wherein said feedback section is constituted by a detection voltage superimposing circuit for superimposing an output voltage detection signal on an element current detection signal. 7. The output voltage detecting section is constituted by a light emitting element which emits light with a light emission amount according to the detected output voltage and outputs the light signal as an output voltage detection signal. The power factor improving converter according to claim 6, comprising a light receiving element that receives light from the light emitting element as an optical signal and superimposes a signal flowing based on the amount of received light on an element current detection signal. 8. The power factor improving device according to claim 1, wherein said element current detecting section is constituted by a resistor for converting an element current of said switching element into a voltage. converter. 9. The method according to claim 9, wherein the inductor is formed of a primary coil.
9. The transformer according to claim 1, wherein the primary coil and the secondary coil are insulated and wound at a predetermined winding ratio to form a transformer, and the DC output unit is connected to the secondary coil. 2. The power factor improving converter according to claim 1.