JP2002261714A - Frequency-regulating circuit of stereo multiplexer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress a deviation of an oscillation frequency of a VCO contained in a stereo multiplexer to an allowing range. SOLUTION: A frequency-regulating circuit of the stereo multiplexer comprises an FM tuber circuit 27 and a stereo multiplexing circuit 28 formed in the same chip. Thus, the oscillation frequency of the VCO 42 contained in the multiplexing circuit 28 is corrected, based on a clock signal from a clock signal oscillator 31 contained in a PLL circuit 32 of the tuber circuit 27.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a stereo multiplex frequency adjustment circuit for oscillating a VCO of a PLL incorporated in a stereo multiplex at an accurate frequency.

[0002]

2. Description of the Related Art FM stereo receivers receive FM signals.
A broadcast signal is processed by an FM tuner to extract a stereo-stereo composite signal, and the stereo-stereo composite signal is added to a stereo multiplex to extract a left signal L and a right signal R.

FIG. 4 is a block diagram of a conventional FM stereo receiver. Antenna 1 is connected to FM through antenna circuit 2.
It is connected to a tuner circuit T and a stereo multiplex circuit M.

The FM tuner circuit T is an antenna circuit 2
-Frequency amplifier circuit 4 and clock signal oscillator 5 connected to
A PLL circuit 6 having a VCO that produces a local oscillation signal based on the clock signal oscillated from the LM, a FM broadcast signal received by the antenna circuit 2 and a local oscillation signal from the VCO of the PLL circuit 6 are mixed. The mixer circuit 7 converts the signal into a predetermined intermediate frequency signal.

The tuner circuit T further includes an intermediate frequency amplifying circuit 8 for amplifying the intermediate frequency signal converted by the mixer circuit 7 and an FM demodulating circuit 9 for performing FM demodulation and demodulating a stereo composite signal from the converted intermediate frequency signal.
Having.

The stereo multiplex circuit M connected to the tuner circuit T comprises a PLL circuit 11, a decoder 12, and a stereo switch circuit 13.

FIG. 5 is a block diagram showing details of the PLL circuit 11. The PLL circuit 11 includes a phase comparator 15 to which the 19 KHZ pilot signal is added, a low-pass filter 16 connected to the phase comparison circuit 15, a VCO connected via a buffer circuit 17, and a 76KHZ oscillator oscillated by the VCO 18. And a frequency divider 20 for reducing the oscillation frequency to 1/2. In this example, frequency divider 1
Since the frequency division ratio of 9 is 1/2, the oscillation frequency of the VCO is 3
8 / (1/2) = 76 KHz, but the oscillation frequency of the VCO differs depending on the set value of the frequency division ratio.

[0008] The FM stereo broadcast signal received by the antenna 1 is applied to the high frequency amplifier circuit 4 of the tuner circuit T via the antenna circuit 2 and amplified. The FM stereo broadcast signal amplified by the high frequency amplifier circuit 4 is supplied to a mixer circuit 7.
Is mixed with the local oscillation signal oscillated by the VCO of the PLL circuit 6 and converted into an intermediate frequency signal.

The local oscillation signal is a clock signal oscillator 5
According to the FM stereo broadcast signal to be received using the clock signal from the FM stereo broadcast signal as a reference signal, the frequency difference from the FM stereo broadcast signal is set to a predetermined intermediate frequency. Accordingly, the mixer circuit 7 converts the frequency of the FM stereo broadcast signal into an intermediate frequency signal having a constant frequency.

The frequency-converted intermediate frequency signal is amplified by an intermediate frequency amplifier circuit 8 and demodulated by an FM demodulation circuit 9 to demodulate a stereo composite signal.
The composite signal extracted from the FM demodulation circuit 9 is applied to a stereo multiplex circuit M. The added composite signal is applied to the phase comparator 15 of the PLL circuit 11.

19 KH applied to the phase comparator 11
The Z pilot signal is 76KH oscillated by the VCO 18.
The oscillation signal in the vicinity of Z is compared in phase with the signal divided by the frequency divider 19 and the frequency divider 20, and the output signal adjusts the oscillation frequency of the VCO 18, and the VCO 18 oscillates the 76 KHZ oscillation signal.

The composite signal extracted from the FM demodulation circuit 9 of the tuner circuit T is applied to the decoder 12. In the decoder 12, a 38K signal generated by the PLL circuit 11 and added through the stereo switch circuit 13 is used.
The main signal L + R combined with the function of the HZ reproduced subcarrier signal
And the sub-signals (LR) and-(LR) are extracted, and these signals are added to extract the left signal L and the right signal R.

[0013]

As described above, the composite signal extracted from the FM demodulation circuit of the tuner circuit is applied to the stereo multiplex circuit, and the composite signal is output from the VCO.
Regenerate the 8 KHZ subcarrier signal. On the other hand, in the decoder, the main signal L + R and the sub-signals (LR) and-(L-) are combined with the function of the reproduced sub-carrier signal of 38 KHZ created by the PLL circuit and added through the stereo switch circuit.
R), and these signals are added to obtain a left signal L and a right signal R.

As described above, since the reproduced sub-carrier signal is obtained from the VCO built in the PLL of the stereo multiplex circuit, the VCO needs to be oscillated at a precisely determined frequency. For this reason, the frequencies are matched on the chip, but the oscillation frequency of the VCO deviates from the set value due to the stress at the time of molding the chip, the variation increases, and the yield of the chip decreases.

[0015]

According to the present invention, there is provided a PLL circuit for generating a local oscillation signal based on a clock signal oscillated from a clock signal oscillator, and an F signal received by an antenna.
An FM tuner circuit having a mixer circuit for mixing an M stereo broadcast signal and a local oscillation signal from the PLL circuit and converting the signal into an intermediate frequency signal, and an FM tuner circuit for demodulating a stereo composite signal; and a stereo composite signal added from the FM tuner circuit. P to recover the subcarrier signal from the signal
A stereo multiplex circuit having an LL circuit and a decoder for generating a left signal and a right signal, wherein the FM tuner circuit and the stereo multiplex circuit are formed on the same chip, and a VCO built in the stereo multiplex circuit is provided. The oscillation frequency is set to P of the FM tuner circuit.
Provided is a stereo multiplex frequency adjustment circuit that corrects based on a clock signal from a clock signal oscillator built in an LL circuit.

Further, according to the present invention, a VCO incorporated in the stereo multiplex circuit is provided with a first terminal whose oscillation frequency increases when a first switch is turned on, and a second terminal whose oscillation frequency is decreased when a second switch is turned on, A counter circuit for counting an oscillation frequency from a VCO incorporated in the stereo multiplex circuit with reference to a clock signal oscillated from a clock signal oscillator incorporated in the tuner circuit, wherein the counter circuit has a value determined as an upper limit. When the above is reached, turn on the second switch
Then, the oscillation frequency of the VCO is reduced, and when the counter circuit becomes equal to or less than a value set as the lower limit, the first switch is turned on to increase the oscillation frequency of the VCO, and the counter circuit is set within the range between the upper limit and the lower limit. In this case, a stereo multiplex frequency adjustment circuit is provided in which the switch is held in the previous state and the VCO continues to oscillate with the oscillation signal in that state.

Further, according to the present invention, a VCO incorporated in the stereo multiplex circuit is provided with a first terminal whose oscillation frequency is increased when a first switch is turned on, and a second terminal whose oscillation frequency is decreased when a second switch is turned on, V
A counter circuit that counts a clock signal oscillated from a clock signal oscillator built in the tuner circuit with reference to an oscillation signal oscillated from the CO. Turn on the first switch to increase the oscillation frequency of the VCO,
The second switch is turned on when the counter circuit becomes equal to or less than a value defined as a lower limit, and the oscillation frequency of the VCO is reduced. When the counter circuit is within the range of the upper limit and the lower limit, the oscillation frequency of the VCO is changed to the state. The present invention provides a stereo multiplex frequency adjustment circuit to be held by the multiplexing circuit.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A stereo multiplex frequency adjusting circuit according to the present invention will be described with reference to FIGS.

FIG. 3 is a block diagram of the FM stereo receiver of the present invention. An FM tuner circuit 27 and a stereo multiplex circuit 28 formed on the same chip are connected to the antenna 25 via an antenna circuit 26.

The FM tuner circuit 27 has a high frequency amplifier circuit 30 for amplifying the FM stereo broadcast signal received by the antenna circuit 26 and a PLL having a VCO for oscillating a local oscillation signal based on an oscillation signal oscillated from a clock signal oscillator. A circuit 32 comprises a mixer circuit 33 for mixing the FM stereo broadcast signal amplified by the high frequency amplifier circuit 30 and the local oscillation signal from the VCO and converting the signal into a predetermined intermediate frequency signal.

The tuner circuit 27 further includes an intermediate frequency amplifying circuit 34 for amplifying the intermediate frequency signal converted by the mixer circuit 33 and an FM demodulation circuit 35 for performing FM demodulation and demodulating a stereo composite signal from the converted intermediate frequency signal. Having.

The stereo multiplex circuit 28 connected to the tuner circuit 27 comprises a PLL circuit 36, a decoder 38 and a stereo switch circuit 37.

FIG. 1 is a block diagram of a stereo multiplex frequency adjusting circuit according to the present invention, which is a main part of a PLL circuit 36 of the stereo multiplex circuit 28. The PLL circuit 36 includes a phase comparator 40 to which the 19 KHZ pilot signal is added, a low-pass filter 41 connected to the phase comparison circuit 40, a VCO 42 connected to the low-pass filter 41, and an oscillator oscillated by the VCO 42. Frequency divider 43 for reducing the oscillation frequency of 76 KHZ to 1/2
And a frequency divider 44.

The VCO 42 turns on the first switch 45.
Then, the oscillation frequency is increased by Δfu, and when the second switch 46 is turned on, the oscillation frequency is decreased by Δfu.
The counter 47 has an input terminal, a first output terminal, a second output terminal, and a reference terminal REF. The reference input terminal REF
The reference signal Ref obtained by dividing the frequency of the clock oscillation signal oscillated by the clock signal oscillator 31 of the tuner circuit 27 by the frequency divider 48 is added. VCO4 is connected to the input terminal.
2 are applied.

The counter 47 counts the oscillation frequency of the oscillation signal from the VCO 42 applied to the input terminal with reference to the reference signal Ref applied to the reference input terminal REF. The oscillating frequency of the oscillating signal is counted, and when the counted value is equal to or less than the lower limit value A1, an output signal is generated from the first output terminal and the first switch 4
5 is turned on to increase the oscillation frequency by Δfu. When the count value is equal to or greater than the value Ah determined as the upper limit value, an output signal is generated from the second output terminal, the second switch 46 is turned on, and the oscillation frequency is reduced by Δfu. When the counter circuit is within the range between the upper limit and the lower limit, the previous output signal is held and the VCO continues to oscillate with the oscillation signal in that state.

The FM stereo broadcast signal received by the antenna 25 is transmitted to the tuner circuit 27 via the antenna circuit 26.
And amplified by the high-frequency amplifier circuit 30 of FIG. The FM stereo broadcast signal amplified by the high frequency amplifier circuit 30 is applied to a mixer circuit 33, mixed with a local oscillation signal oscillated by a VCO of a PLL circuit 32, and converted into an intermediate frequency signal.

The local oscillation signal is a clock signal oscillator 3
Received as a reference signal using the clock signal from
According to the stereo broadcast signal, the frequency difference from the FM stereo broadcast signal is set to a predetermined intermediate frequency. Accordingly, the mixer circuit 33 converts the frequency of the FM stereo broadcast signal into an intermediate frequency signal having a constant frequency.

The frequency-converted intermediate frequency signal is amplified by an intermediate frequency amplification circuit 34 and demodulated by an FM demodulation circuit 35 to demodulate a stereo composite signal. The stereo composite signal extracted from the FM demodulation circuit 35 is applied to a stereo multiplex circuit 28.
The added stereo composite signal is applied to the phase comparator 40 of the PLL circuit 36.

19 KH added to the phase comparator 40
The Z pilot signal is 76 KH oscillated by the VCO 42
The phase of the Z oscillation signal is compared with the frequency of the signal divided by the frequency divider 43 and the frequency divider 44, and the output signal adjusts the oscillation frequency of the VCO 42, and the 76 KHz oscillation signal is oscillated from the VCO 42. The 76 KHz oscillation signal is divided by a frequency divider 43.
Generates a 38 KHZ subcarrier signal.

On the other hand, the composite signal extracted from the FM demodulation circuit 35 of the tuner circuit 27 is
Is added to In the decoder 38, the PLL circuit 3
The main signal L + R, the sub-signals (LR) and-(LR) are taken out in conjunction with the function of the sub-carrier signal of 38 KHZ generated at 6 and added through the stereo switch circuit 37, and these signals are obtained. To extract the left signal L and the right signal R.

The PLL of the multiplex circuit 28
When a 19KHZ pilot signal is applied to the circuit 36, a 76KHZ oscillation signal is oscillated from the VCO 42 based on the 19KHZ pilot signal, and a 38KHZ signal is output from the frequency divider.
When the initial value of the oscillation frequency of the VCO 42 is misaligned, the phase of the reproduced subcarrier of 38 KHz shifts from the subcarrier of the composite signal.

The oscillation signal oscillated by the VCO 42 is applied to the input terminal of the counter 47. The counter 4
Reference numeral 7 counts the oscillation frequency of the oscillation signal from the VCO 42 applied to the input terminal with reference to the reference signal Ref applied to the reference terminal REF.

When the counted value is equal to or smaller than the lower limit value A1, an output signal is generated from the first output terminal, the first switch 45 is turned on, and the oscillation frequency is set to Δ
fu up. When the count value of the oscillating frequency of the oscillating signal is equal to or more than the value Ah defined as the upper limit, an output signal is generated from the second output terminal, the second switch 45 is turned on, and the oscillating frequency is reduced by Δfu.

When the count value is between A1 and Ah, the counter 47 holds the output signal of the previous state,
The VCO 42 continues to oscillate with the oscillation signal in that state.

Therefore, even if the initial set value of the oscillation frequency of the VCO 42 is slightly shifted, it can be kept in the range from Al to Ah. As an example, let the VCO oscillation frequency be 76 KHZ ± 2.
KHZ, that is, within the range of 74 KHZ to 78 KHZ. In this case, when the first switch 45 is turned on, VC
Suppose that control is performed to increase the oscillation frequency of O42 by Δfu = 3 KHz, and control is performed to decrease the oscillation frequency of VCO 42 by Δfu = 3 KHz when the second switch 46 is turned on. Is set to 76KHz-2KHz = 74KHZ, and Ah is set to 76KHz + 2KHz = 78KHZ.

In this state, the oscillation frequency of the VCO 42 becomes 8
If it is shifted to 0 kHz, an output signal is generated from the second output terminal of the counter 47 and the second switch 46 is turned on.
The VCO 42 is controlled down by 3 KHZ, and the VCO 42
Has an oscillation frequency of 77 KHZ.

The oscillation frequency of the VCO 42 is 71 kHz.
, The output signal is generated from the first output terminal of the counter 47, the first switch 45 is turned on, and the VCO 42
Is controlled by 3 KHZ, and the oscillation frequency of the VCO 42 becomes 74 KHZ. According to this method, even if the oscillation frequency of the VCO 42 varies from 71 KHz to 81 KHz, the oscillation frequency of the VCO 42 is changed from 74 KHz to 78 KHZ.
Z can be suppressed to the frequency range.

FIG. 2 shows another embodiment of the multiplexed frequency adjusting circuit according to the present invention. Reference terminal R of counter 47
The oscillation signal from the VCO 42 is frequency-divided into the FE by the frequency divider 48 and added as a reference signal Ref.
To the input terminal of the counter 47,
It is the same as FIG. 1 except that the counter 47 counts the frequency of the clock signal.

That is, the counter 47 counts the clock signal from the clock signal oscillator 31 applied to the input terminal using the oscillation signal from the VCO 42 applied to the reference terminal REF as the Ref signal. Then, the oscillation frequency of the clock signal is counted, and when the count value is equal to or less than a value AI defined as a lower limit value, an output signal is generated from the first output terminal, the first switch 45 is turned on, and the oscillation frequency of the VCO 42 is set to Δfu. Up. When the count value is equal to or greater than the value Ah set as the upper limit value, an output signal is generated from the second output terminal, the second switch 46 is turned on, and the VCO 4
2 is reduced by Δfu.

[0040]

According to the stereo multiplex frequency adjusting circuit of the present invention, the FM tuner circuit and the stereo multiplex circuit are formed on the same chip, and the oscillation frequency of the VCO incorporated in the stereo multiplex circuit is adjusted by the PLL of the FM tuner circuit. Since it can be corrected based on the clock signal from the clock signal oscillator built in the circuit,
After adjusting the oscillation frequency of the CVO built in the multiplex circuit on the chip, even if the oscillation frequency deviates from the set value due to the stress during molding, the variation is suppressed, and the yield increases.

[Brief description of the drawings]

FIG. 1 is a block diagram of a stereo multiplex frequency adjustment circuit of the present invention.

FIG. 2 is a block diagram showing another embodiment of the stereo multiplex frequency adjustment circuit of the present invention.

FIG. 3 is a block diagram of an FM stereo receiver using the stereo multiplex frequency adjustment circuit of the present invention.

FIG. 4 is a block diagram of a conventional FM stereo receiver.

FIG. 5 is a block diagram of a PLL used in a conventional FM stereo receiver.

[Explanation of symbols]

 27 Tuner circuit 28 Multiplex circuit 31 Clock signal oscillator 32 PLL 33 Mixer circuit 36 PLL circuit 38 Decoder 40 Phase comparator circuit 42 VCO 45 First switch 46 Second switch 47 Counter

Claims (3)

[Claims] 1. A PLL circuit for generating a local oscillation signal based on a clock signal oscillated from a clock signal oscillator, and a mixer for mixing an FM stereo broadcast signal received by an antenna with a local oscillation signal from the PLL circuit. An FM tuner circuit having a mixer circuit for converting to a frequency signal and demodulating a stereo composite signal; and a PLL circuit for extracting a pilot signal from the stereo composite signal from the FM tuner circuit and reproducing a subcarrier based on the pilot signal. And a stereo multiplex circuit having a decoder for generating a left signal and a right signal. An oscillation frequency of a VCO built in the stereo multiplex circuit, wherein the FM tuner circuit and the stereo multiplex circuit are formed on the same chip. In the PLL circuit of the FM tuner circuit Frequency adjusting circuit of a stereo multiplex, characterized in that modified based on the clock signal from that clock signal oscillator. 2. A clock signal oscillator built in the tuner circuit, comprising: a first switch for increasing the oscillation frequency when turned on to a VCO built in the stereo multiplex circuit; and a second switch for decreasing the oscillation frequency when turned on. A counter circuit that counts an oscillation frequency from a VCO incorporated in the stereo multiplex circuit with reference to a clock signal oscillated from the first multiplex circuit; and when the counter circuit becomes equal to or less than a value set as a lower limit, the first switch Is turned on to increase the oscillation frequency of the VCO. When the counter circuit has a value equal to or higher than a value set as an upper limit, the second switch is turned on to reduce the oscillation frequency of the VCO. When the value is within the lower limit range, the switch is held at the previous state and the VCO is activated in that state. Frequency adjusting circuit of a stereo multiplex according to claim 1, wherein the continuing to oscillate at the signal. 3. A VCO incorporated in the stereo multiplex circuit is provided with a first terminal whose oscillation frequency is increased when a first switch is turned on, and a second terminal whose oscillation frequency is decreased when a second switch is turned on. And a counter circuit that counts a clock signal oscillated from a clock signal oscillator built in the tuner circuit with reference to an oscillation signal oscillated from the tuner circuit. Turning on the first switch, increasing the oscillation frequency of the VCO, and turning on the second switch to decrease the oscillation frequency of the VCO when the value of the counter circuit becomes equal to or less than a lower limit. Is within the upper and lower limits, the switch is held in the previous state and the VCO oscillates with the oscillation signal in that state. Frequency adjusting circuit of a stereo multiplex according to claim 1, wherein the continued.