JP2002261590A - Delay unit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a delay unit which is capable of improving the delay time in accuracy, when it generates delay signals on the basis of input signals and enabling a delay time to cope easily with a frequency difference, even if input signals have arbitrary frequencies. SOLUTION: A ring oscillation circuit 28 comprises delay elements 21, 23 to 25. An oscillation control circuit 29 controls a switching circuit 22, on the basis of input signals and the output signals from a comparator 30 so as to stop the oscillation of the ring oscillation circuit 28. The comparator 30 binarizes analog signal which are inputted into the delay element 23, outputs the binarized signal as reference signals, and supplies the reference signals to the oscillation control circuit 29. A comparator 31 turns analog signals which are outputted from a delay element 26 into binary signals, and the binary signals are outputted as delay signals.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a PLL (Phas).
The present invention relates to a delay device applied to clock / data recovery (data strobe circuit) using an e-locked loop (e-locked loop) circuit.

[0002]

2. Description of the Related Art Clock data recovery is for recovering a clock component contained in data based on data detected by a pickup such as a CD player. For example, if there is data as shown in FIG. 7A, the data shown in FIG.
There should be a clock as shown in (B). Clock data recovery regenerates the clock from the data.

[0003] When the clock is generated, it is performed using a PLL circuit. However, the input data and the clock have different periods as shown in FIGS. 7A and 7B.
As shown in (A), there is a case where “1” and “0” are continuous, resulting in omission. For this reason, since the clock of the input data is different from the number of edges of the clock, the PLL operation cannot be realized by comparing the phases of the respective clocks.

Therefore, the clock and data recovery by the PLL circuit is performed by adding a delay device 4 and a general configuration of a phase comparator 1, a loop filter 2 and a VCO (voltage controlled oscillator) 3 as shown in FIG. And pulse mask circuit 5
Contains. In such a clock data recovery, input data as shown in FIG.
, The input data is delayed by the delay device 4 as shown in FIG.

[0005] The pulse mask circuit 5 generates a comparison clock based on the recovery clock output from the VCO 3 and the input data of the delay device 4. In other words, the pulse mask circuit 5 operates between the rising edge of the recovery clock and the next rising edge as shown in FIG.
When the edge of the input data shown in (A) is not detected, a comparison clock as shown in FIG. 9 (D) is generated by masking the recovery clock.

The phase comparator 1 compares each falling edge of the comparison clock generated by the pulse mask circuit 5 with both edges of the input data delayed by the delay device 4, and outputs a signal corresponding to the comparison result. Is output. Loop filter 2
Performs smoothing of the output signal from the phase comparator 1 and outputs it to the VCO 3. The VCO 3 generates a recovery clock whose transmission frequency changes according to the output from the loop filter 2. By such a series of operations, PL
L operation is realized.

As described above, P as shown in FIG.
The clock data recovery by the LL circuit requires a pulse mask circuit 5 that generates a comparison clock.
Further, since the same clock as the input data is required at a timing earlier than the input data to generate the comparison clock, a delay device for delaying the input data by, for example, T / 2 (T is the bit rate of the input data) 4 is required.

Therefore, an example of a conventional delay device will be described with reference to FIG. This delay device is shown in FIG.
0, a setting circuit 11, a plurality of delay elements 12 to 17, a delay circuit 18, and comparators 19 and 20.
And Here, the VCO 3 shown in FIG. 8 is configured by a ring oscillation circuit using an equivalent delay element,
The delay time of the delay elements 12 to 17 is determined by applying the bias voltage equivalent to the bias voltage applied to the delay elements constituting CO3 to the delay elements 12 to 17 in FIG.

For this reason, the VCO 3 is composed of, for example, four delay elements as shown in FIG. 12, and when the VCO 3 oscillates at the bit rate T of the input data, the VCO
The delay time of one of the delay elements constituting O3 is T /
It becomes 8. Therefore, the delay time per one of the delay elements 12 to 17 in FIG. 10 is T / 8. In such a delay device, when an input signal as shown in FIG. 11A is input to the setting circuit 11, the setting circuit 11
At the rising edge of the input signal, the input signal of the delay element 13 (the input signal of the comparator 19) is set to change from H level to L level. As a result, the input signal changes from H level to L level as shown in FIG.

Thereafter, the input signal is applied to the delay elements 13, 1
4 and the delay circuit 18 are delayed by the delay time T1 (T1 = T / 2) and input to the setting circuit 11, and the setting circuit 11
A reset operation is performed to release the fixed “L” level of the input signal of the delay element 13. As a result, the input signal attempts to return from the L level to the H level as shown in FIG. 11B, which passes through the four delay elements 13 to 16 for a delay time T2 (T2 = T / 2). The delay signal is generated as an output signal of the delay element 16 as shown in FIG.

Since the setting circuit 11 and the like have a delay, the delay circuit 18 expresses the amount of the delay equivalently, and there is no actual concrete circuit.

[0012]

In such a conventional delay device, the delay time T1 is shifted due to the difference between the initial state of the delay element and the transition state of the input signal.
This occurs because the delay time T1 from when the setting circuit 11 sets the input signal of the delay element 13 to the L level until the reset is applied does not match the delay time T / 2 (see FIG. 11B). ). The cause is the delay time T
This is because 1 is determined by the delay time T / 4 of the delay elements 13 and 14 and the fixed delay time of the delay circuit 18 expressed equivalently.

Further, in the conventional delay device, the delay time T
Since the delay circuit 18 having a fixed delay time is included in the element for determining 1, there is a problem that when the input signal has an arbitrary frequency, the delay time cannot easily cope with a difference in frequency. In view of the above, an object of the present invention is to improve the accuracy of a delay time when a delay signal is generated based on an input signal, and to reduce the delay time even if the input signal has an arbitrary frequency. An object of the present invention is to provide a delay device that can easily cope with a difference in frequency.

[0014]

Means for Solving the Problems In order to solve the above problems and to achieve the object of the present invention, the inventions according to claims 1 and 2 are configured as follows. In other words, the invention according to claim 1 constitutes a ring oscillation circuit in which a plurality of delay elements are cascaded, and an output side of a predetermined delay element is fed back to an input side of a first-stage delay element to perform self-oscillation. A delay circuit including the ring oscillation circuit, and a reference signal based on each output signal of at least two of the plurality of delay elements, and a delay signal having a predetermined delay time from the reference signal. Oscillation control for fixing a signal at an input terminal of a predetermined delay element of a plurality of delay elements constituting the output circuit and the ring oscillation circuit to a predetermined level and releasing the fixation for a predetermined time based on the input signal And an oscillation control circuit for performing the above operation.

The invention described in claim 2 is the first invention.
Wherein the oscillation control circuit performs the oscillation control based on the input signal and the reference signal. As described above, in the present invention, the ring oscillation circuit is formed by using the delay element, and the oscillation of the ring oscillation circuit is controlled by the oscillation control circuit. Therefore, according to the present invention,
Since the delay time when the delay signal is generated based on the input signal does not depend on the fixed delay amount as in the related art, the accuracy of the delay time can be improved.

Further, according to the present invention, since the input signal does not depend on a fixed delay amount as in the prior art, even if the input signal has an arbitrary frequency, the delay time can easily cope with a difference in frequency.

[0017]

Embodiments of the present invention will be described below with reference to the drawings. First, the configuration of an embodiment of the delay device of the present invention will be described with reference to FIG.
As shown in FIG. 1, the delay device according to this embodiment includes a delay element 21, a switch circuit 22, and delay elements 23 to 23.
27 are connected in cascade, and these constitute a delay circuit. Then, the output of the delay element 25 is fed back to the delay element 21 at the first stage, so that the ring oscillation circuit 2 is formed by the delay element 21, the switch circuit 22, and the delay elements 23 to 25.
8 is formed. Therefore, the ring oscillation circuit 28 is included in the delay circuit.

Here, the delay device having such a configuration is applied to a PLL circuit as shown in FIG. 8, and in this case, the delay device 4 in FIG. 8 is replaced with the delay device shown in FIG. It will be. The VCO 3 shown in FIG. 8 is constituted by a ring oscillation circuit using an equivalent delay element.
Each delay element constituting CO3 and each delay element 21 in FIG.
23 to 27 are provided with equivalent bias voltages.

Therefore, the VCO 3 shown in FIG. 8 is composed of, for example, four delay elements as shown in FIG.
Is oscillating at the bit rate T of the input data, the delay time per one of the delay elements constituting the VCO 3 is T / 8. Therefore, the delay element 21 of FIG.
The delay time per one of 23 to 27 is T / 8. The ring oscillation circuit 28 is controlled to stop oscillation by an oscillation control circuit 29 as described later. That is, the oscillation control circuit 29 stops the oscillation of the ring oscillation circuit 28 by controlling the switch circuit 22 based on the input signal and the output signal of the comparator 30 as described later.

In the delay device according to this embodiment,
A comparator 30 connected to the input side of the delay element 23 and a comparator 31 connected to the output side of the delay element 26 are provided as output circuits. The comparator 30 binarizes the analog signal input to the delay element 23, outputs the binarized signal as a reference signal, and supplies the reference signal to the oscillation control circuit 29. The comparator 31 binarizes the analog signal output from the delay element 26, and outputs the binarized signal as a delay signal delayed by the delay elements 23 to 26.

Next, an operation example of the embodiment shown in FIG. 1 having such a configuration will be described with reference to FIG.
Now, when an input signal as shown in FIG. 2A is input to the oscillation control circuit 29 and the input signal rises at time t1, the oscillation control circuit 29 outputs the input signal of the delay element 23 after the input signal rises. The switch circuit 22 is controlled so that a signal (input signal of the comparator 30) changes from H level to L level.

As a result, the switch circuit 22 operates as instructed, and the ring oscillation circuit 28 is released from the stop of the oscillation and enters the oscillation state. Therefore, the input signal of the delay element 23 becomes as shown in FIG. As shown, the level changes from the H level to the L level, and then changes to the H level again. This delay element 2
The output of the comparator 30 changes to the H level, the L level, and the H level in accordance with the level change of the input signal of No. 3, and the change is transmitted to the oscillation control circuit 29.

As shown in FIG. 2B, at time t2 after the input signal of the delay element 23 changes to the H level, the oscillation control circuit 29 sets the input signal of the delay element 23 to the H level. To control the switch circuit 22. As a result, the switch circuit 22 operates as instructed, and the input signal of the delay element 23 becomes “H” as shown in FIG.
The level is fixed to the level, and the ring oscillation circuit 28 is in a state where the oscillation is stopped.

Such a change in the input signal of the delay element 23 is transmitted after being delayed by, for example, T / 2 (T is the bit rate of the input signal) by the delay elements 23 to 26, and the output signal of the delay element 26 is shown in FIG. 2 (C). The H level of the input signal of the delay element 23 is fixed at time t
3 when the input signal of the oscillation control circuit 2 rises to the H level at time t3.
Controls the switch circuit 22 so that the H level of the input signal of the delay element 23 is released after the rise of the input signal. As a result, the stop of the oscillation of the ring oscillation circuit 28 is released and the ring oscillation circuit 28 enters the oscillation state.

By repeating such an operation, the input signal of the delay element 23 and the output signal of the delay element 26 are delayed by, for example, T / 2. And the comparator 30
Converts the input signal of the delay element 23 into a binary signal and outputs the binary signal as a reference signal. The comparator 31 binarizes the output signal of the delay element 26 and outputs the binarized signal as a delay signal.

As described above, in this embodiment,
A ring oscillation circuit 28 is formed using a delay element, and the oscillation of the ring oscillation circuit 28 is controlled by an oscillation control circuit 29. Therefore, according to this embodiment,
Since the delay time when the delay signal is generated based on the input signal input to the oscillation control circuit 29 does not depend on the fixed delay amount as in the related art, the accuracy of the delay time can be improved.

Also, in this embodiment, since the input signal does not depend on a fixed delay amount as in the prior art, even if the input signal has an arbitrary frequency, the delay time can easily cope with the difference in frequency. Note that, in the embodiment of FIG.
Although the description has been given of the case where the delay elements are connected, the number of connection of the delay elements can be set to an arbitrary number according to the delay time or the like. Further, the number of delay elements constituting the ring oscillation circuit 28 can be arbitrarily set according to a desired oscillation frequency. Furthermore, the position at which the comparator 30 outputs the reference signal and the position at which the comparator 31 outputs the delay signal can be set to any positions according to the delay time.

Next, a specific configuration of the oscillation control circuit 29 shown in FIG. 1 and an overall configuration including the same will be described with reference to FIG. As shown in FIG. 3, the oscillation control circuit 29 includes a D latch (D flip-flop) 291, a delay buffer 292, a two-input NAND circuit 293, and a D latch 294.

The D latches 291 and 294 are connected to the input terminal (D) at the rising edge of the signal input to the input terminal (C).
Has a set terminal (SN) in addition to the original D latch function of outputting the state of the signal input to the output terminal (Q),
It has a function of setting the output terminal (Q) to the H level when the input of the set terminal (SN) is at the L level.

More specifically, the input signal S11 is input to the input terminal (C) of the D latch 291 and the input terminal (D) is grounded to 0V. The output signal of the output terminal (Q) of the D latch 291 is input to the set terminal (SN) of the D latch 291 via the delay buffer 292. Further, the output signal S12 of the output terminal (Q) of the D latch 291 is supplied to one input terminal of the NAND circuit 293 and the set terminal (SN) of the D latch 294, and is output to the outside. ing. The output signal S14 of the NAND circuit 293 is supplied to the switch circuit 22.

The D-latch 294 has its input terminal (C) supplied with a reference signal which is the output of the comparator 30, and its input terminal (D) grounded to 0V. The output signal of the inverted output terminal (QN) of the D latch 294 is supplied to the other input terminal of the NAND circuit 293. Also, the delay elements 21, 23-2 in FIG.
7 is supplied with positive and negative bias voltages in order to adjust the delay amount of the delay element. As described above, the same bias voltage as that applied to each delay element (see FIG. 12) constituting the VCO 3 shown in FIG. 8 is supplied.

Since the configuration of the other parts of the circuit of FIG. 3 is the same as that of the circuit of FIG. 1, the same components are denoted by the same reference numerals and description thereof is omitted. Next, an example of the operation of the oscillation control circuit 29 having such a configuration will be described.
This will be described with reference to FIG. Now, it is assumed that an input signal S11 as shown in FIG. 4A is input to the input terminal (C) of the D latch 291. When the input signal S11 rises as shown in FIG.
The output signal S12 of the output terminal (Q) 91 changes from the H level to the L level as shown in FIG. 4B because the L level of the input terminal (C) is output.

Here, the period during which the output signal 12 is at the L level is defined by the pulse width of the delay buffer 292. The change in the output signal S12 as described above is also transmitted to the set terminal (SN) of the D latch 294.
As a result, the output terminal (Q) of the D latch 294 is set to the H level, and as a result, the output signal S13 of the inverted output terminal (QN) of the D latch 294 is set to the L level as shown in FIG. Is done.

In the NAND circuit 293, the logical product of the output signal S12 of the D latch 291 shown in FIG. 4B and the output signal S13 of the D latch 294 shown in FIG. 4C is calculated. Therefore, the output signal S14 of the NAND circuit 293
Changes from L level to H level as shown in FIG. On the basis of the change of the output signal S14 of the NAND circuit 293, the switch circuit 22 performs an operation of canceling the stop of the oscillation of the ring oscillation circuit 28 which has stopped the oscillation. As a result, the positive input signal S15 of the delay element 23
4E, the stop of the oscillation is released as shown in FIG. 4 (E) and the level starts to change, and the negative input signal S16 of the delay element 24 causes the stop of the oscillation as shown in FIG. Is released and the level starts to change.

The input signal S1 of such a delay element 23
5, based on the change in S16, the output signal (reference signal) S17 of the comparator 30 changes as shown in FIG.
Then, when the output signal S17 of the comparator 30 rises as shown in FIG. 4G, the L level of the input terminal (D) is output to the output terminal (Q) of the D latch 294. As a result, the output signal S13 of the inverted output terminal (QN) of the D latch 294 changes from L level to H level as shown in FIG.

As a result of this change, the output signal S14 of the NAND circuit 293 also changes from H level to L level. Based on this change, the switch circuit 22 performs an operation of stopping the oscillation of the ring oscillation circuit 28 that is currently oscillating. As a result, the positive input signal S15 of the delay element 23 is
As shown in (E), the oscillation is stopped and fixed at the H level, and the negative input signal S16 of the delay element 24 is stopped and fixed at the L level as shown in FIG. You.

Thereafter, the oscillation control circuit 29
Each time the input signal S11 input to 1 rises, the above operations are repeated, and the stop control of the oscillation of the ring oscillation circuit 28 is repeated. Next, the delay elements 21 and 23 shown in FIG.
The configuration of the delay element 23 is shown in FIG. 5, since the configuration of each of the delay elements 21 and 23 to 27 is the same.

As shown in FIG. 5, the delay element 23 includes NMOS transistors Q1 and Q2 formed of a differential pair. A negative input signal (inverted input signal) is applied to the gate of the MOS transistor Q1, and the MOS transistor Q2 The + input signal (non-inverted input signal) is applied to the gate of. The drain of the MOS transistor Q1
A load PMOS transistor Q3 is connected, and a + output signal (a non-inverted output signal) is output from the drain thereof.
Is output. A load PMOS transistor Q4 is connected to the drain of the MOS transistor Q2, and a negative output signal (inverted output signal) is output from the drain of the PMOS transistor Q4.

A common bias voltage is applied to each gate of the MOS transistors Q3 and Q4. An NMOS transistor Q constituting a current source is connected between the gates of the MOS transistors Q1 and Q2 and the ground.
5 is connected. The current flowing through the MOS transistor Q5 changes according to the bias voltage applied to its gate. Then, the bias voltage changes according to the oscillation frequency.

A capacitor C1 formed of an NMOS transistor is connected between the drain of the MOS transistor Q1 and the ground. Similarly, a capacitor C2 composed of an NMOS transistor is connected between the drain of the MOS transistor Q2 and the ground. Each of these capacitors C1 and C2 has a predetermined capacitance in order to obtain a predetermined time constant for determining the amount of delay of the delay element 23.

Next, FIG. 6 shows a specific configuration of the switch circuit 22 shown in FIG. As shown in FIG. 6, the switch circuit 22 includes a switch MOS transistor Q11 that is turned on / off by an output signal S14 of a NAND circuit 293 of the oscillation control circuit 29 of FIG.
To Q13 and MOS functioning as a dummy switch
The transistor Q14 includes a transistor Q14 and a MOS transistor Q15 functioning as a current source. The transistor Q14 extracts a positive output signal from the output terminal 221 and a negative output signal from the output terminal 222.

More specifically, the MOS transistor Q
In reference numeral 11, the output signal S14 is applied to the gate, the power supply voltage VDD is applied to the source, and the drain is connected to the output terminal 221. Also, MO
S transistor Q12 has output signal S14 at its gate.
Is applied, its source is connected to the output terminal 222, and its drain is connected to the source of the MOS transistor Q13 and the drain of the MOS transistor Q14, respectively.

Further, the output signal S14 is applied to the gate of the MOS transistor Q13, the drain is connected to the gate of the MOS transistor Q14, and the power supply voltage VDD is applied to the common connection. I have. The source of the MOS transistor Q14 is grounded via the MOS transistor Q15. A bias voltage for determining the current flowing therethrough is applied to the gate of the MOS transistor Q15.

The switch circuit 22 having such a configuration
When the output signal S14 of the oscillation control circuit 29 is at the L level as shown in FIG. 4D, the gate voltages of the MOS transistors Q11 and Q12 in FIG. 6 are at the L level. Therefore, the MOS transistors Q11 and Q12 are turned on, the output signal of the output terminal 221 is fixed at the H level, and the output signal of the output terminal 222 is fixed at the L level (FIG. 4E). F)))
The oscillation of the ring oscillation circuit 28 is stopped.

On the other hand, when the output signal S14 of the oscillation control circuit 29 is at the H level as shown in FIG.
The transistors Q11 and Q12 are turned off, the above state is released, and the oscillation stop state of the ring oscillation circuit 28 is released (see FIGS. 4E and 4F).

[0046]

As described above, in the present invention, a ring oscillation circuit is formed using a delay element, and the oscillation of the ring oscillation circuit is controlled by the oscillation control circuit.
Therefore, according to the present invention, the delay time when generating the delay signal based on the input signal does not depend on the fixed delay amount as in the related art, so that the accuracy of the delay time can be improved.

Further, according to the present invention, since the input signal does not depend on a fixed delay amount as in the prior art, even if the input signal has an arbitrary frequency, the delay time can easily cope with a difference in frequency.

[Brief description of the drawings]

FIG. 1 is a circuit diagram illustrating a configuration example of an embodiment of a delay device of the present invention.

FIG. 2 is a waveform chart for explaining the operation of the embodiment.

FIG. 3 is a circuit diagram showing a specific configuration of an oscillation control circuit and an overall configuration including the configuration.

FIG. 4 is a time chart showing an example of the operation of the oscillation control circuit.

FIG. 5 is a circuit diagram showing a specific configuration of a delay element.

FIG. 6 is a circuit diagram showing a specific configuration of a switch circuit.

FIG. 7 is a diagram illustrating an example of data input to clock data recovery and a clock included in the data.

FIG. 8 is a block diagram illustrating an example of a configuration of clock data recovery by a PLL circuit.

FIG. 9 is a time chart showing an operation example of the clock data recovery.

FIG. 10 is a block diagram showing a configuration of a conventional delay device.

FIG. 11 is a waveform chart for explaining the operation of the delay device.

12 is a diagram illustrating an example of the configuration of the VCO in FIG. 8;

[Explanation of symbols]

 21, 23 to 27 Delay element 22 Switch circuit 28 Ring oscillation circuit 29 Oscillation control circuit 30, 31 Comparator 291, 294 D latch 292 Delay buffer 293 NAND circuit

Claims (2)

[Claims] 1. A ring oscillation circuit in which a plurality of delay elements are connected in cascade, and an output side of a predetermined delay element is fed back to an input side of a delay element of a first stage to perform self-oscillation. A delay circuit including: a reference signal based on each output signal of at least two delay elements of the plurality of delay elements; and an output circuit that outputs a delay signal having a predetermined delay time from the reference signal; An oscillation control circuit for fixing the signal at the input terminal of the predetermined delay element of the plurality of delay elements constituting the oscillation circuit to a predetermined level, and performing an oscillation control for releasing the fixing for a predetermined time based on the input signal; and A delay device, comprising: 2. The delay device according to claim 1, wherein the oscillation control circuit performs the oscillation control based on the input signal and the reference signal.