JP2002260384A - Semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a semiconductor device in which destruction of data of a memory cell or causing erroneous read-out of data can be prevented without increasing current consumption with simple circuit constitution. SOLUTION: A dummy write-buffer 17 having circuit constitution being same as a write-buffer 10 is provided in a dummy memory circuit section 19, circuit constitution of the dummy memory circuit section 19 is made same as a memory circuit section 12 for performing write-in and read-out of data, while an internal control circuit 11 detects voltage of a dummy bit line DBL of the dummy memory circuit section 19 through a detecting circuit 18, discriminates finish of pre-charge, and controls pre-charge operation for a pre-charge circuit 6 and a pre-charge circuit 14.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

TECHNICAL FIELD The present invention relates to a static RA
M related to a semiconductor memory device configured by an IC memory,
In particular, the present invention relates to a semiconductor memory device capable of appropriately controlling the activation timing of a sense amplifier and a word line by using a dummy memory circuit for reducing current consumption and guaranteeing a precharge operation.

[0002]

2. Description of the Related Art Conventionally, in a memory circuit of a semiconductor memory device, a circuit that simulates an operation and performs self-control is generally used for the purpose of guaranteeing operation and reducing current consumption. A typical example is a dummy memory circuit. The dummy memory circuit simulates a series of operations until a memory cell is selected and read, and generates an internal activation control signal by detecting a bit line voltage and an output state of a sense amplifier with a pseudo circuit. It is to make it.

FIG. 11 is a schematic block diagram showing a configuration example of such a conventional semiconductor memory device.
12 is a timing chart showing waveforms at various parts in FIG. The operation of the conventional dummy memory circuit will be described with reference to FIGS. In the semiconductor memory device 100 of FIG. 11, external address data A0 to An
Is input to the address input circuit 101, the address input circuit 101 outputs the input address data A0 to An.
Is output to the row decoder 102 and the column decoder 103, respectively, and a predetermined signal ATD indicating that the address data has been input is output to the internal control circuit 104 which controls the operation of each unit.

The internal control circuit 104 has a predetermined signal ATD
Is activated, the precharge circuit 105 and the dummy precharge circuit 111 are activated for a predetermined time set in advance. When the precharge circuit 105 and the dummy precharge circuit 111 are activated, the corresponding bit line pair BL1 and BL1B and the dummy bit line pair DBL and DBLB are precharged, respectively.

After precharging is performed for a predetermined time, the internal control circuit 104 deactivates the precharge circuit 105 and the dummy precharge circuit 111, and also includes a row decoder 102, a column decoder 103, and a sense amplifier 106. , Input / output circuit 107 and dummy sense amplifier 1
12 are each activated. Further, the internal control circuit 10
4 activates the dummy precharge circuit 111 and the dummy sense amplifier 112 of the dummy memory circuit 110.

Address data from the address input circuit 101 is supplied to a row decoder 102 and a column decoder 103.
, And the row decoder 102 activates a word line connected to the memory cell MC specified by the address data. Also, the column decoder 103
The bit line pair connected to the memory cell MC specified by the address data is connected to the column gate 109 to the sense amplifier 106 and the write buffer 110, respectively.

Further, the column decoder 103 connects the pair of bit lines DBL and DBLB of the dummy memory cell array 113 to the dummy sense amplifier 112 with respect to the dummy column gate 114. In this way, the SRAM
In the memory cell array 108 and the dummy memory cell array 113, a desired memory cell MC and a dummy memory cell DMC corresponding to the memory cell MC are activated.

For example, when data is read from a desired memory cell MC of the memory cell array 108, the bit line pair BL1, BL1B connected to the activated memory cell MC is connected to the data line pair DL by the column gate 109.
, And DLB, the sense amplifier 106 outputs the read data to the input / output circuit 107. Further, the read data is output from the input / output circuit 107 to the outside via the output terminal DOUT.

Similarly, the dummy column gate 114
The dummy bit line pair DBL and DBLB connected to the activated dummy memory cell 113 is connected to the dummy sense amplifier 112 via the dummy data line pair DDL and DDLB.
And a data signal DSO indicating read data from the dummy sense amplifier 112 to the internal control circuit 104.
Is output.

When a predetermined data signal DSO is input, the internal control circuit 104 deactivates the row decoder 102, the column decoder 103, the sense amplifier 106, the input / output circuit 107, and the dummy sense amplifier 112, respectively. , The precharge circuit 105 and the dummy precharge circuit 111 are activated. The precharge circuit 105, the sense amplifier 106, the input / output circuit 107, the memory cell array 108, the column gate 109, and the write buffer 110 constitute a memory circuit unit, and the dummy precharge circuit 111, the dummy sense amplifier 112, and the dummy memory cell array 113 and the dummy column gate 114 constitute a dummy memory circuit portion.

As described above, when the address data A0 to An are input, one word line and one pair of bit lines are activated, respectively, and one memory cell MC of the memory cell array MA is selected. The dummy memory cell DMC connected to the activated word line is selected. Since the dummy memory cell DMC is connected to the same bit line and sense amplifier as the selected memory cell MC, the state of the data read operation can be simulated. If the completion of the data read can be detected, the internal control circuit 104 deactivates the word line and terminates the operation of the sense amplifier by deactivating each unit, thereby reducing unnecessary current consumption. I have.

Next, when writing data to a desired memory cell MC of the memory cell array 108, the desired memory cell MC is activated by externally input address data A0 to An. The write data input from the input terminal DIN to the input / output circuit 107 is transmitted to the bit line pair BL via the write buffer 110 and the column gate 109.
1 and BL1B, and are written to desired memory cells MC of the memory cell array 108. On the other hand, a voltage of a predetermined level is applied to each flip-flop constituting each dummy memory cell DMC, and predetermined data is written.

Further, in an asynchronous semiconductor memory device as shown in FIG. 11 in which each section is activated by input of address data, a synchronous semiconductor memory in which each section is activated by a change in the signal level of a clock signal. Unlike a storage device, since there is no period in which a precharge circuit precharges a memory cell array, a precharge period must be secured by a precharge control signal PRC. If the precharge period is too short, the previous data remains on the bit line, preventing new data reading. If the precharge period is too long,
This leads to a delay in data reading. Therefore, optimizing the precharge period leads to improvement in operation performance.

[0014]

However, the problem here is the precharge period immediately after data writing. Since the voltage difference between the bit line pair is the largest in the data write state (hereinafter, this state is referred to as a full swing state), it is necessary to lengthen the precharge period t in the next data read. Normally, all precharge periods are set in accordance with this time t. However, such a method has a problem that the precharge period in the data read cycle is too long. Also, when setting the precharge period, conventionally, it is not possible to cope with a change in memory size, so it is necessary to set a value having a margin that can cope with each memory size or all of them. I had to.

On the other hand, there is a method of controlling a precharge period in a dummy memory circuit. In this method, a detection circuit for detecting a precharge state is provided on a bit line of a dummy memory circuit, and an activation control state of the precharge circuit is performed according to the precharge state detected by the detection circuit. By doing so, it is possible to respond to changes in memory size without performing extra precharge during a data read cycle, but it is possible to respond to a precharge state immediately after writing data. Did not.

Normally, the main purpose of using a dummy memory circuit is to reduce current consumption during data reading. Therefore, the dummy memory circuit has not been provided with an unnecessary write buffer at the time of data reading. Therefore, in the data write state, as shown in FIG.
A write buffer composed of a transistor having a large gate size causes a pair of bit lines BL1 and BL1B, which suddenly enter a full swing state, to a dummy bit line pair D1.
BL and DBLB have small changes in voltage difference as in the data read state.

[0017] Therefore, in a case where each cycle of data reading and data writing is short such as a high-speed SRAM, when transitioning to a data reading operation from another address immediately after data writing, the voltage of the bit line pair is reduced. Difference and,
Due to the difference in the voltage difference between the dummy bit line pairs, the precharge period could not be monitored sufficiently.
As a result, data destruction of a memory cell or erroneous reading of data may occur.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problem. A dummy write buffer is provided in a dummy memory circuit having a dummy memory cell and a dummy bit line to perform either data reading or data writing. Simulates a suitable bit line voltage even in the state described above, and controls the precharge period according to the bit line voltage, without increasing current consumption with a simple circuit configuration.
An object of the present invention is to provide a semiconductor memory device capable of preventing occurrence of data destruction of a memory cell or erroneous reading of data.

[0019]

A semiconductor memory device according to the present invention has at least a memory cell array having a plurality of memory cells and at least input / output of complementary signals of opposite signal levels to corresponding memory cells. One bit line pair, each word line transmitting an activation control signal to each corresponding memory cell, and amplifying a signal from a bit line pair connected to the memory cell when reading data from a desired memory cell. A write amplifier for writing data to a desired memory cell via a corresponding bit line pair at the time of data writing; and
In a semiconductor memory device having a memory circuit portion having a precharge circuit for precharging a bit line pair, a plurality of dummy cells connected to the same word line as a corresponding memory cell having the same configuration as a memory cell of a memory cell array A dummy memory cell array comprising memory cells, simulating the operation of the memory cell array; a dummy bit line pair for inputting / outputting a complementary signal of an opposite signal level to each corresponding dummy memory cell of the dummy memory cell array; A dummy write buffer for writing predetermined data to a memory cell; a dummy precharge circuit for precharging a dummy bit line pair; a dummy memory circuit for simulating the operation of the memory circuit; Check the voltage of one dummy bit line in the line pair. A detection circuit for, in which a control unit for controlling the operation of the precharge circuit and the dummy precharge circuit performs determination of the precharge state for the bit line pair from the voltage detected by the detection circuit unit.

More specifically, the dummy memory cell array includes dummy memory cells connected to each word line, and each of the dummy memory cells has a signal level opposite to a dummy bit line pair. To input and output the complementary signal of.

Further, the dummy memory circuit section, when reading data from a desired dummy memory cell, amplifies a signal from a dummy bit line pair connected to the dummy memory cell and outputs the amplified signal to a control section. With
The control unit may control activation of the sense amplifier and the word line in the memory circuit unit in accordance with a signal from the dummy sense amplifier.

Specifically, each of the dummy memory cells is
A predetermined voltage is always applied so as to store and hold predetermined data.

[0023]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described in detail based on an embodiment shown in the drawings. FIG. 1 is a block diagram showing a configuration example of a semiconductor memory device according to an embodiment of the present invention. Note that FIG. 1 shows a case where the memory cell array is formed of one column of memory cells as an example for easy understanding.

In FIG. 1, a semiconductor memory device 1 has an address input circuit 2 to which address data A0 to An are input from outside, and word lines WL0 to WLm (m is a natural number).
, A row decoder 3 that controls the activation of
And a memory cell array 5 composed of each memory cell MC of the SRAM in one column (m + 1) row. The semiconductor memory device 1 includes a precharge circuit 6 for precharging a bit line pair of the memory cell array 5, a desired bit line pair and a data line pair DL,
And a column gate 7 for connection to the DLB.

Further, the semiconductor memory device 1 has a data line pair D
A sense amplifier 8 to which read data is input via L and DLB, and an input / output circuit 9 for outputting a data signal output from the sense amplifier 8 via an output terminal DOUT
And a write buffer 10 that outputs write data input from the input terminal DIN via the input / output circuit 9 to the pair of data lines DL and DLB. The semiconductor memory device 1 includes a row decoder 3, a column decoder 4, a precharge circuit 6, a sense amplifier 8, an input / output circuit 9, and an internal control circuit 11 for controlling activation of the write buffer 10. The memory circuit unit 12 is formed by the memory cell array 5, the precharge circuit 6, the column gate 7, the sense amplifier 8, and the write buffer 10.

On the other hand, the semiconductor memory device 1 has a dummy memory cell array 13 composed of each dummy memory cell DMC of the SRAM and a dummy precharge for precharging the bit line pair DBL, DBLB of the dummy memory cell array 13. Circuit 14 and dummy memory cell array 1
3 dummy column gates 1 for connecting the dummy bit line pairs DBL, DBLB to the dummy data line pairs DDL, DDLB.
5 is provided.

Further, the semiconductor memory device 1 includes a dummy sense amplifier 16 to which data read via the dummy data line pair DDL and DDLB is input, and a dummy for outputting predetermined write data to the dummy data line pair DDL and DDLB. A write buffer 17 and a detection circuit 18 for detecting the voltage of the dummy bit line DBL and outputting the detected voltage to the internal control circuit 11 are provided. In addition, the dummy memory cell array 13, the dummy precharge circuit 14, the dummy column gate 15, the dummy sense amplifier 16, and the dummy write buffer 17 form a dummy memory circuit unit 19. The internal control circuit 11 forms a control unit, and the detection circuit 18 forms a detection circuit unit.

The dummy memory cell array 13 has the same configuration as one memory cell column in the memory cell array 5, and (m + 1) dummy memory cells DMC connected corresponding to the word lines WL0 to WLm. It is composed of The detection circuit 18 is formed of an inverter. In the inverter, an input terminal is connected to the dummy bit line DBL, and an output terminal is connected to the internal control circuit 11.

The detection circuit 18 may detect the voltage level of the dummy bit line DBL according to a predetermined control signal.
It is preferable to use an input NAND circuit. In the NAND circuit, one input terminal is connected to the dummy bit line DBL, the output terminal is connected to the internal control circuit 11, and a predetermined control signal is input to the other input terminal. A signal corresponding to the voltage level of bit line DBL is output to internal control circuit 11.

When external address data A0 to An is input to the address input circuit 2, the address input circuit 2
Outputs the input address data A0 to An to the row decoder 3 and the column decoder 4, respectively, and outputs a predetermined signal ATD indicating that the address data has been input to the internal control circuit 11.

When a predetermined signal ATD is inputted, the internal control circuit 11 outputs a high (High) level precharge control signal PRC to the precharge circuit 6 and the dummy precharge circuit 14, respectively. And the voltage of the dummy bit line DBL input from the detection circuit 18 is monitored. When the precharge circuit 6 and the dummy precharge circuit 14 are activated, all the bit line pairs in the memory cell array 5 and the dummy memory cell array 13 are precharged.

Thereafter, when detecting that the voltage of dummy bit line DBL has risen to a predetermined voltage, internal control circuit 11 determines that precharge by precharge circuit 6 has been completed, and outputs a precharge control signal PRC. By falling to a low level, the precharge operation is stopped for the precharge circuit 6 and the dummy precharge circuit 14.
At the same time, the internal control circuit 11 activates the row decoder 3 and the column decoder 4 and simultaneously activates the sense amplifier 8,
A predetermined control signal SEN is output to the input / output circuit 9 and the dummy sense amplifier 16 to activate the same, and further, the write buffer 10 and the dummy write buffer 17 are
A write control signal WEN corresponding to a write enable signal WEB input from outside is output.

The address data from the address input circuit 2 is decoded by a row decoder 3 and a column decoder 4, respectively. The row decoder 3 activates a word line connected to a memory cell MC specified by the address data. To In addition, the column decoder 4 connects the bit line pair BL1 and BL1B connected to the memory cell MC specified by the address data to the column gate 7 to the data line pair DL and
Sense amplifier 8 and write buffer 10 via DLB
To each other.

Further, the column decoder 4 includes a dummy column gate 1
5, a pair of dummy bit line pairs DBL and DBLB of the dummy memory cell array 13 are connected to the dummy data line pair DD.
L and DDLB are connected to the dummy sense amplifier 16 and the dummy write buffer 17, respectively. In this way, in the memory cell array 5 and the dummy memory cell array 13, a desired memory cell MC and a dummy memory cell DMC corresponding to the memory cell MC are activated.

Here, for example, when reading data from a desired memory cell MC of the memory cell array 5, the internal control circuit 11 sends an external write enable signal WE to the internal control circuit 11.
B becomes high level and becomes inactive, and outputs a low (Low) level control signal WEN to the write buffer 10 and the dummy write buffer 17 to make them inactive respectively. The memory cell M activated by the column gate 7 controlled by the column decoder 4
The bit line pair BL1 and BL1B connected to C is connected to the sense amplifier 8 via the data line pair DL1 and DL1B, and the read data input to the sense amplifier 8 is amplified by the sense amplifier 8 and the input / output circuit 9 and further output from the input / output circuit 9 to the outside via the output terminal DOUT.

Similarly, a dummy bit line pair DBL, DBL, connected to an activated dummy memory cell DMC by a dummy column gate 15 controlled by a column decoder 4.
DBLB is connected to dummy sense amplifier 16 via dummy data line pair DDL, DDLB. The read data input to the dummy sense amplifier 16 is amplified by the dummy sense amplifier 16 and output to the internal control circuit 11 as a data signal DSO. When a predetermined data signal DSO is input, the internal control circuit 11 deactivates the row decoder 3, the column decoder 4, the sense amplifier 8, the input / output circuit 9, the dummy sense amplifier 16, and the dummy write buffer 17, respectively. At the same time, the precharge circuit 6 and the dummy precharge circuit 14 are activated.

Next, the precharge circuit 6 and the dummy precharge circuit 14, the column gate 7 and the dummy column gate 15, the sense amplifier 8 and the dummy sense amplifier 16, and the write buffer 10 and the dummy write buffer 17 have the same circuit configuration. , And a specific circuit example of each unit will be described. First, FIG. 2 is a circuit diagram showing an example of a memory cell MC, and FIG. 3 is a circuit diagram showing an example of a dummy memory cell DMC. Note that FIGS. 2 and 3 show a memory cell MC and a dummy memory cell DMC connected to an arbitrary word line WLx (0 ≦ x ≦ m) as an example.

In FIG. 2 and FIG. 3, a memory cell MC and a dummy memory cell DMC are respectively an inverter INV1, INV2 forming a flip-flop and an N-channel type having a gate connected to the same word line and forming a transfer gate for the flip-flop. MOS transistors (hereinafter referred to as NMOS transistors) QN1 and QN
2 is comprised.

In the memory cell MC, the inverter IN
One connecting portion between V1 and INV2 is connected to bit line BL1 via NMOS transistor QN1, and the other connecting portion between inverters INV1 and INV2 is
It is connected to bit line BL1B via transistor QN2. In the dummy memory cell DMC, one connection between the inverters INV1 and INV2 is connected to NM
Dummy bit line DBL via OS transistor QN1
The other connection between the inverters INV1 and INV2 is supplied with a predetermined voltage such as a power supply voltage VDD, and is further connected to a dummy bit line DBLB via an NMOS transistor QN2. From this, in each dummy memory cell DMC of the dummy memory cell array 13, at the time of data reading, the dummy bit line DBL goes low and the dummy bit line DBLB goes high.

FIG. 4 is a diagram showing a circuit example of the precharge circuit 6. As shown in FIG. 4, the precharge circuit 6 includes transmission gates TM1 to TM3 and an inverter INV3. The precharge control signal PRC from the internal control circuit 11 is input to the gate of each NMOS transistor constituting the transmission gates TM1 to TM3. In addition, each P constituting the transmission gates TM1 to TM3
A gate of a channel type MOS transistor (hereinafter, referred to as a PMOS transistor) has a gate connected to a precharge control signal PR from an internal control circuit 11 via an inverter INV3.
C has been input.

The transmission gate TM1 controls the application of the power supply voltage VDD to the bit line BL1.
Transmission gate TM2 is connected to bit line BL1B
Of the power supply voltage VDD is controlled. Transmission gate TM3 is connected to bit line pair BL1, B
Performs L1B equalization. When, for example, a high-level signal ATD is input from the address input circuit 2, the internal control circuit 11 outputs a high-level precharge control signal PRC.
And the voltage of the dummy bit line DBL input from the detection circuit 18 is monitored.

Each of the transmission gates TM1 to TM3 of the precharge circuit 6 is turned on to be in a conductive state, so that each of the bit lines BL1 and BL1B is precharged, and a bit line pair BL1, BL
1B is equalized. Further, when the voltage of the dummy bit line DBL rises to a predetermined voltage, the internal control circuit 11 determines that the precharge by the precharge circuit 6 has been completed, and lowers the precharge control signal PRC to a low level. Each of the transmission gates TM1 to TM3 of the charge circuit 6 is turned off and cut off, and the precharge and equalize operations for the bit line pair BL1 and BL1B are stopped. At this time, the internal control circuit 11
, The precharge operation is similarly stopped.

When the signal ATD from the address input circuit 2 is at a low level, the internal control circuit 11 outputs a low-level precharge control signal PRC so that the transmission gates TM 1 to T
M3 is turned off and cut off, and the bit line pair B
Precharge and equalization are not performed on L1 and BL1B. 5 is a diagram showing a circuit example of the dummy precharge circuit 14, except that the bit line BL1 in FIG. 4 is replaced with a dummy bit line DBL and the bit line BL1B in FIG. 4 is replaced with a dummy bit line DBLB. Since it is the same as that described above, the description is omitted.

FIG. 6 is a diagram showing a circuit example of the sense amplifier 8. 6, a sense amplifier 8 includes a PMOS transistor QP forming a current mirror circuit.
1 and QP2 and NMOS transistors QN3 to QN5. In the PMOS transistors QP1 and QP2, the power supply voltage VDD is applied to each source, each gate is connected, and the connection is connected to the drain of the PMOS transistor QP1. On the other hand, the PMOS transistors QP1 and QP1
Each drain of P2 is connected to a corresponding NMOS transistor Q
Connected to the drains of N3 and QN4, respectively.
The sources of S transistors QN3 and QN4 are connected, and an NMOS transistor Q is connected between the connection and ground.
N5 is connected, and the NMOS transistor QN5 forms a current source.

The data line DL is connected to the gate of the NMOS transistor QN3, and the data line DLB is connected to the gate of the NMOS transistor QN4. NMO
The gate of the S transistor QN5 has an internal control circuit 11
, And the connection between the PMOS transistor QP2 and the NMOS transistor QN4 is
An output terminal of the sense amplifier 8 is provided, and an output signal SO is output to the input output circuit 9 from the output terminal. Internal control circuit 11
Is, for example, a high-level signal A from the address input circuit 2.
When TD is input, the activation control signal SE at a high level
By outputting N, the NMOS transistor QN5 of the sense amplifier 8 is activated, and the sense amplifier 8 is activated.

On the other hand, when the high level signal ATD is not input from the address input circuit 2, the internal control circuit 11 sets the activation control signal SEN to low level, and the NMOS transistor QN 5 of the sense amplifier 8 Deactivates and the operation of the sense amplifier 8 stops. FIG.
FIG. 3 is a diagram illustrating a circuit example of a dummy sense amplifier 14,
The data line DL in FIG. 6 is replaced with a dummy data line DDL.
The data line DLB in FIG.
And the output signal SO of FIG.
6 except that the output signal DSO is output to the internal control circuit 11 and the description thereof is omitted.

Next, FIG. 8 is a diagram showing a circuit example of the write buffer 10, and FIG.
7 is a diagram illustrating a circuit example of FIG. 8, the write buffer 10 includes NMOS transistors QN6 to QN9,
NAND circuits NA1 and NA2 and inverters INV4 to
INV6. A series circuit of NMOS transistors QN6 and QN7 and a series circuit of NMOS transistors QN8 and QN9 are connected in parallel between the power supply voltage VDD and the ground. NMOS transistor Q
A data line DL is connected to a connection between N6 and QN7, and a data line DLB is connected to a connection between NMOS transistors QN8 and QN9.
Are connected respectively.

The data signal SI input from the input / output circuit 9 is input to one input terminal of the NAND circuit NA1 and is input to one input terminal of the NAND circuit NA2 via the inverter INV6. The control signals WEN from the internal control circuit 11 are input to the other input terminals of the NAND circuits NA1 and NA2, respectively. N
An output terminal of the AND circuit NA1 is connected to a connection portion of each gate of the NMOS transistors QN7 and QN8 via an inverter INV4, and an output terminal of the NAND circuit NA2 is
NMOS transistor QN via inverter INV5
6 and QN9.

At the time of data reading in which the high-level write enable signal WEB is input to the internal control circuit 11, the write buffer 10 receives the low-level control signal WEN from the internal control circuit 11 and performs NAND operation regardless of the data signal SI. The output terminals of the circuits NA1 and NA2 are:
Both become high level. For this reason, all the NMOS transistors QN6 to QN9 are turned off and cut off.

Next, at the time of data writing in which the low-level write enable signal WEB is input to the internal control circuit 11, the write buffer 10 receives the high-level control signal WEN from the internal control circuit 11. Accordingly, the output terminal of the NAND circuit NA1 has a signal level obtained by inverting the signal level of the data signal SI from the input / output circuit 9, and the output terminal of the NAND circuit NA2 has the output terminal
Has the same signal level as the data signal SI. Therefore, the data line DL is connected to the data signal S from the input / output circuit 9.
The voltage level is the same as I, and the data line DLB has a voltage level obtained by inverting the signal level of the data signal SI from the input / output circuit 9.

On the other hand, the dummy write buffer 17 shown in FIG.
Indicates that the data line DL in FIG.
The data line DLB in FIG.
8 is the same as FIG. 8 except that the power supply voltage VDD is applied instead of the input data signal SI in FIG. At the time of data reading, the internal control circuit 11
Becomes low level, and the NAND circuits NA1 and NA2 in the dummy write buffer 17
Are at a high level. Therefore, the NMOS transistor Q in the dummy write buffer 17
N6 to QN9 are all turned off to be in the cutoff state.

Next, in the dummy write buffer 17 at the time of data writing, the control signal WEN from the internal control circuit 11 goes high, the output terminal of the NAND circuit NA1 goes low and the output terminal of the NAND circuit NA2 goes high. Level. Therefore, the dummy data line DD
L goes high and the dummy data line DDLB goes low.

FIG. 10 shows the semiconductor memory device 1 shown in FIG.
5 is a timing chart showing waveforms of respective parts of FIG. Figure 1
0, when the address data A0 to An are input and the high-level signal ATD is input to the internal control circuit 11, first, the internal control circuit 11
A high-level precharge control signal PRC is output to the dummy precharge circuit 14 to perform precharge for setting the voltages of the bit lines and the dummy bit lines to the initial state.

At this time, the internal control circuit 11
By monitoring the voltage of the dummy bit line DBL obtained from No. 8 and detecting whether or not the precharge is completed, it can be seen that the precharge period hardly exists at the time of data reading. Therefore, the selection of a word line by the row decoder 3 is started immediately, so that the speed of data reading can be increased. In addition, the transition of each unit to the inactive state is performed promptly.

Next, when the external write enable signal WEB changes from the high level to the low level in order to shift from the data read operation to the data write operation, data write to the address specified by the address data A0 to An is performed. Therefore, a desired word line, that is, the word line WLm in FIG. 10 is selected by the row decoder 3 activated by the internal control circuit 11, and the internal control circuit 11 further activates the control signal WEN to a high level to be activated. You. In such a state, the bit line pair BL1 and BL1B are immediately brought into the full swing state where the voltage difference is the largest by the write buffer 10.

Since dummy write buffer 17 is also provided in dummy memory circuit 19, dummy bit line pair DBL, DBLB immediately enters a full swing state, and internal control circuit 11 causes dummy bit line DBL.
The voltage state of BL is monitored. At this time, the dummy write buffer 17 outputs predetermined inconsistent data to the dummy data line pair DDL and DDLB so that the same data as the fixed data previously stored in the dummy memory cell DMC is written. You should do so.

Immediately after such a data write operation is completed, when the next data read is performed by changing the address data A0 to An, conventionally, the precharge is performed from the state where the dummy bit line pair does not fully swing. It was done. On the other hand, in the semiconductor memory device 1, since the state of the dummy bit line DBL is accurately monitored by the internal control circuit 11, the precharge performed on the bit line pair BL 1 and BL 1 B of the memory cell array 5 is performed. A time similar to the time t1 is a dummy bit line pair DBL, DBL.
It is required for precharging the BLB. Therefore, the internal control circuit 11 can accurately recognize that the precharge has been completed without erroneously determining early.

As described above, in the semiconductor memory device according to the present embodiment, the dummy memory circuit section 19 is provided with the dummy write buffer 17 having the same circuit configuration as the write buffer 10 so that the dummy memory circuit section 19 can write and read data. The internal control circuit 11 detects the voltage of the dummy bit line DBL of the dummy memory circuit unit 19 via the detection circuit 18 and has a circuit configuration similar to that of the memory circuit unit 12 for reading data. Completion determination is performed, and the precharge circuit 6 and the dummy precharge circuit 14
Control of the precharge operation for.

Therefore, while the time required for precharging from the full swing state in the bit line pair immediately after data writing is set as the precharge period, the dummy write buffer uses The state of writing or data reading is simulated reliably, and precharge can be performed for a precharge time according to the state. Therefore, in a data read cycle in which normal data read continues, useless precharge time can be reduced, and the speed of the data read operation can be increased.

When the data reading state continues continuously at the time of reading data, for example, when used for image processing, operation at a high-speed cycle becomes possible, and a great effect can be obtained. In the data read cycle immediately after data writing, the dummy bit line pair is in the full swing state by the dummy write buffer in the same manner as the bit line pair is in the full swing state, so that the precharge is performed only for the necessary time. Be executed. As described above, even during the same data reading, the precharge time can be made variable in accordance with the previous operation state, so that high-speed operation without wasteful operation is possible.

In the above description, the case where the memory cell array is formed of one column of memory cells in the memory circuit section 12 is shown as an example, but this is merely an example, and the present invention is not limited to this. However, the present invention can be similarly applied to a memory cell array composed of a plurality of columns of memory cells. The "B" at the end of the code of the signal and the code of the data line indicates the inversion of the signal level and indicates that the signal is low active.

[0062]

As is apparent from the above description, according to the semiconductor memory device of the present invention, the dummy memory circuit portion includes the dummy write buffer for writing predetermined data to the dummy memory cell, Simulating the operation of the memory circuit unit at the time of writing with the dummy memory circuit unit, detecting the voltage of one of the dummy bit lines in the dummy bit line pair, and judging the precharge state for the bit line pair from the detected voltage. By doing so, the operation of the precharge circuit and the dummy precharge circuit is controlled. As a result, it is possible to control the precharge operation while accurately detecting the precharge state of the bit line pair without increasing the current consumption by simply adding a simple circuit. Since the optimum precharge time can always be provided according to the precharge state of the bit line pair without adding a delay circuit or the like, the time required for precharge can be shortened, and the memory cell size can be reduced. Data destruction or erroneous data reading can be prevented. Further, it is possible to guarantee an operation margin for precharge by following a characteristic change due to a manufacturing variation or the like.

More specifically, the dummy memory cell array is composed of dummy memory cells connected to each word line, and each of the dummy memory cells has a signal level opposite to the dummy bit line pair. Input / output of complementary signals. Accordingly, the control unit can accurately determine the precharge state of each bit line pair in the memory circuit unit based on the detection voltage from the detection circuit unit.

Further, the activation control of the sense amplifier and the word line in the memory circuit section is performed in accordance with the signal from the dummy sense amplifier. From this,
Using the output signal from the dummy sense amplifier, the state of data read from the memory circuit portion can be detected to control the activation state of the sense amplifier and word line, and the through current in the sense amplifier and the bit line can be controlled. , The charge / discharge current in the battery can be suppressed.

Specifically, each of the above dummy memory cells is
A predetermined voltage is always applied so as to store and hold predetermined data. This makes it possible to accurately detect the data read state using the output signal from the dummy sense amplifier.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration example of a semiconductor memory device according to an embodiment of the present invention.

FIG. 2 is a circuit diagram showing an example of a memory cell MC in FIG.

FIG. 3 is a circuit diagram showing an example of a dummy memory cell DMC in FIG.

FIG. 4 is a diagram illustrating a circuit example of a precharge circuit 6 in FIG. 1;

FIG. 5 is a diagram illustrating a circuit example of a dummy precharge circuit 14 in FIG. 1;

FIG. 6 is a diagram showing a circuit example of a sense amplifier 8 in FIG. 1;

FIG. 7 is a diagram showing a circuit example of a dummy sense amplifier 14 in FIG.

FIG. 8 is a diagram showing a circuit example of a write buffer 10 in FIG. 1;

FIG. 9 is a diagram illustrating a circuit example of a dummy write buffer 17 in FIG. 1;

FIG. 10 is a timing chart showing waveforms of respective parts of the semiconductor memory device 1 shown in FIG.

FIG. 11 is a schematic block diagram showing a configuration example of a conventional semiconductor memory device.

FIG. 12 is a timing chart showing waveforms of respective parts of the semiconductor memory device 100 shown in FIG.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Semiconductor memory device 2 Address input circuit 3 Row decoder 4 Column decoder 5 Memory cell array 6 Precharge circuit 7 Column gate 8 Sense amplifier 9 Input / output circuit 10 Write buffer 11 Internal control circuit 12 Memory circuit part 13 Dummy memory cell array 14 Dummy precharge Circuit 15 Dummy column gate 16 Dummy sense amplifier 17 Dummy write buffer 18 Detection circuit 19 Dummy memory circuit section MC Memory cell DMC Dummy memory cell BL1, BL1B Bit line DBL, DBLB Dummy bit line DL, DLB Data line DDL, DDLB Dummy data line

Claims (4)

[Claims] 1. A memory cell array having a plurality of memory cells, at least one bit line pair for inputting / outputting a complementary signal of an opposite signal level to each corresponding memory cell, and a memory cell array for each corresponding memory cell. Each word line for transmitting an activation control signal, a sense amplifier for amplifying and outputting a signal from a bit line pair connected to the memory cell when reading data from a desired memory cell, and a sense amplifier for writing data. A semiconductor memory device comprising: a write buffer for writing data to a desired memory cell via a bit line pair; and a memory circuit portion having a precharge circuit for precharging the bit line pair. Multiple dummy cells connected to the same word line as the corresponding memory cell A dummy memory cell array configured by memory cells and simulating the operation of the memory cell array; a dummy bit line pair for inputting / outputting a complementary signal of an opposite signal level to each corresponding dummy memory cell of the dummy memory cell array; A dummy write buffer for writing predetermined data to the dummy memory cell, and a dummy memory circuit unit having a dummy precharge circuit for precharging the dummy bit line pair, and simulating the operation of the memory circuit unit; A detection circuit unit for detecting a voltage of one dummy bit line in the dummy bit line pair; a precharge circuit for judging a precharge state of the bit line pair from the voltage detected by the detection circuit unit; A control unit for controlling the operation of the dummy precharge circuit. The semiconductor memory device according to claim. 2. The dummy memory cell array according to claim 1, wherein each of the dummy memory cells is connected to each of the word lines, and each of the dummy memory cells has a signal level opposite to that of the dummy bit line pair. 2. The semiconductor memory device according to claim 1, wherein input / output of a complementary signal is performed. 3. The dummy memory circuit section, when reading data from a desired dummy memory cell, amplifies a signal from a dummy bit line pair connected to the dummy memory cell and outputs the amplified signal to the control section. Equipped with an amplifier,
3. The semiconductor memory device according to claim 1, wherein the control unit controls activation of the sense amplifier and the word line in the memory circuit unit in response to a signal from the dummy sense amplifier. 4. The semiconductor memory device according to claim 3, wherein a predetermined voltage is constantly applied to each of said dummy memory cells so as to store and hold predetermined data.