JP2002259484A - 回路設計の解析方法 - Google Patents

回路設計の解析方法

Info

Publication number
JP2002259484A
JP2002259484A JP2001345968A JP2001345968A JP2002259484A JP 2002259484 A JP2002259484 A JP 2002259484A JP 2001345968 A JP2001345968 A JP 2001345968A JP 2001345968 A JP2001345968 A JP 2001345968A JP 2002259484 A JP2002259484 A JP 2002259484A
Authority
JP
Japan
Prior art keywords
design
node
memory
cell
edge
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP2001345968A
Other languages
English (en)
Japanese (ja)
Other versions
JP2002259484A5 (enExample
Inventor
S Brandon Keller
エス・ブランドン・ケラー
Gregory Dennis Rogers
グレゴリー・デニス・ロジャース
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
HP Inc
Original Assignee
Hewlett Packard Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hewlett Packard Co filed Critical Hewlett Packard Co
Publication of JP2002259484A publication Critical patent/JP2002259484A/ja
Publication of JP2002259484A5 publication Critical patent/JP2002259484A5/ja
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Tests Of Electronic Circuits (AREA)
JP2001345968A 2001-02-12 2001-11-12 回路設計の解析方法 Withdrawn JP2002259484A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/782,407 US6536021B2 (en) 2001-02-12 2001-02-12 Method and system for representing hierarchical extracted resistance-capacitance files of a circuit model
US09/782,407 2001-02-12

Publications (2)

Publication Number Publication Date
JP2002259484A true JP2002259484A (ja) 2002-09-13
JP2002259484A5 JP2002259484A5 (enExample) 2005-06-23

Family

ID=25125953

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2001345968A Withdrawn JP2002259484A (ja) 2001-02-12 2001-11-12 回路設計の解析方法

Country Status (2)

Country Link
US (1) US6536021B2 (enExample)
JP (1) JP2002259484A (enExample)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6425113B1 (en) * 2000-06-13 2002-07-23 Leigh C. Anderson Integrated verification and manufacturability tool
US6931613B2 (en) * 2002-06-24 2005-08-16 Thomas H. Kauth Hierarchical feature extraction for electrical interaction calculations
US7712068B2 (en) * 2006-02-17 2010-05-04 Zhuoxiang Ren Computation of electrical properties of an IC layout
CN117236236B (zh) * 2023-11-10 2024-04-16 杭州行芯科技有限公司 一种芯片设计数据管理方法、装置、电子设备及存储介质

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4831543A (en) * 1986-02-21 1989-05-16 Harris Semiconductor (Patents) Inc. Hierarchical net list derivation system
US5301318A (en) * 1988-05-13 1994-04-05 Silicon Systems, Inc. Hierarchical netlist extraction tool
US5815402A (en) * 1996-06-07 1998-09-29 Micron Technology, Inc. System and method for changing the connected behavior of a circuit design schematic
US5903475A (en) * 1996-07-18 1999-05-11 Lsi Logic Corporation System simulation for testing integrated circuit models
US6113647A (en) * 1996-11-06 2000-09-05 Vlsi Technology, Inc. Computer aided design system and method using hierarchical and flat netlist circuit representations
US6301691B1 (en) * 1999-04-27 2001-10-09 Hewlett-Packard Company System and method for detecting NFETs that pull up to VDD and PFETs that pull down to ground

Also Published As

Publication number Publication date
US20020112216A1 (en) 2002-08-15
US6536021B2 (en) 2003-03-18

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