JP2002259213A - Parallel computer system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve the problem that the acceleration of address conversion by a TLB(translation lookaside buffer) cache can not be expected because the possibility that the TLB cache overflows becomes high when many pieces of long data spreading over a plurality of pages are transferred in a system that exchanges data while performing address conversion between a plurality of nodes. SOLUTION: A field showing whether or not to be overwriteable is prepared on each page entry of the TLB cache, and a means for attaching a priority is provided so as to be able to immediately overwrite in the case of a halfway page entry of data to be transferred and also not to immediately overwrite in the case of the front or last part of the data when a page entry is registered.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a computer system comprising a plurality of computers connected by a network, and more particularly to a computer system for performing address conversion when many computers transmit and receive packets via local and wide area networks. Involved.

[0002]

2. Description of the Related Art As a means for communicating messages between a plurality of computing nodes, there is a "computer system" disclosed in Japanese Patent Application Laid-Open No. Hei 7-262152.

In this known example, a transmission data address, a transmission flag address, a reception data address, and a reception flag address indicate real addresses of a local memory, and data can be transmitted and received in a continuous area in the local memory. In a system such as this known example, when data is transmitted and received in an address space larger than the real address space of the local memory, that is, in a virtual address space, an address conversion mechanism is provided in the transmission circuit and the reception circuit. There is a need.
When a transmitting circuit or a receiving circuit provided with an address conversion mechanism performs address conversion during data transmission / reception, it is necessary to access an address conversion table indicating a relationship between a virtual address and a real address. However, if the relationship between the virtual address and the real address is to be finely performed, the hardware amount of the address conversion table becomes large, and it is difficult to realize the hardware by the hardware logic. Therefore, this can be easily realized by providing the memory in the local memory, but the access time to the address conversion table is lengthened, and the overhead of the address conversion is increased. Therefore, a limited amount of hardware is input, and a TLB cache for storing a part of the address conversion table is provided to shorten the access time to the address conversion table.

[0004]

As a general method of controlling the TLB cache, there are a FIFO method and an LRU method, and the TLB cache is managed using these methods. FIG. 9 shows an example of data in the virtual address space and the real address space. Here, an address conversion unit in which the data 701 to be transferred indicates the relationship between the virtual address space 702 and the real address space 703 is called a page 704. The page 704 of the virtual address space 702 can be freely allocated to the real address space 703 in this manner by an address conversion table including a plurality of entries describing the relationship between the page number and the start address of the real address space.
In this example, the data 701 extends over a wide range from page numbers 1 to 4, and when converting to a real address, TLB
It is necessary to register four page entries for the cache. Since only a limited number of page entries can be stored in the TLB cache, if a large number of long data items 701, such as a plurality of pages 704, are transferred, they become full and overflow immediately. The page entries that are not yet used for data transfer such as page numbers 1 and 4 and are likely to be reused immediately, and the page entries that are all used for data transfer such as page numbers 2 and 3 are: Because they are handled sensibly, they are more likely to be flooded by another data transfer before being reused. If the page entry in the TLB cache overflows and disappears before reuse, it is necessary to access the local memory again, and the TLB cache cannot be expected to speed up the address translation.

[0005]

In order to achieve the above object, all entries in the TLB cache are provided with an overwrite field indicating whether or not overwriting may be prioritized. Next, when registering an entry of the address translation table in the local memory in the TLB cache,
If there is an entry for which the overwrite field is valid, means for overwriting the entry is provided. Further, after registering the page entry in the TLB cache, a means for determining whether the page entry is the first entry, the middle entry, or the last entry of the data is provided. Means are provided for enabling the overwrite field when the entry is an entry, and disabling the overwrite field when the entry is the first or last entry of data. By providing the overwrite field in this manner, the page entry that is unlikely to be immediately reused is overwritten with the page entry of the subsequent data first, and the TLB that has a high possibility of being reused is given priority over the TLB. Since the data can be left in the cache, it is effective in a system for transferring a large number of long data over a plurality of pages.

[0006]

FIG. 1 shows this embodiment. It comprises a plurality of nodes connected by a network 101. For convenience, only one of the nodes 102 is shown in FIG. Although the illustrated node 102 is used to indicate both a transmitting node and a receiving node, in practice these nodes are different. Each node 102 is an instruction processor 10
3. Local memory 104 with appropriate capacity, transmission circuit 1
05 and the receiving circuit 106. The address and data bus 107 issues commands to the transmitting circuit 105, transfers data between the instruction processor 103 and the local memory 104, and transfers data between the local memory 104 and the transmitting circuit 105 and the receiving circuit 106. Used for These four connections are realized by the address and data bus 107, each having an independent address / data bus.
It may be a data line.

The network 101 receives the packets 108 d from the transmission circuit 105 in the node 102 and sends them to the reception circuits 106 of the other nodes 102 according to the contents of the destination node number 112 included in each packet 108. In this example, the network 101 transfers the packets 108 to the receiving circuit 106 in the order of transmission.

FIG. 2 is a block diagram of the transmission circuit 105. The transmission sequencer 130 controls the entire transmission circuit 105. The transmission command is a transmission control word block 12
9 (hereinafter referred to as TCWB), which is stored in the local memory 104 by the instruction processor 103.

The TCWB address register 131 is a register writable by the instruction processor 103.
The TCWB buffer 117 is a register file used to temporarily hold a copy of the TCWB 129. It has the same format as TCWB, and packet type 132, packet split enable 13
3, transmission data offset 134, data length 111, destination node number 112, reception data offset 113, reception flag offset 114, transmission flag offset 13
5 is included.

The transmission FIFO data buffer 136 is a first-in first-out (FIFO) data buffer, and includes a local memory 104 and a network 101.
Used for buffering data between. The transmission direct memory access controller 137 (hereinafter, referred to as a transmission DMAC) is a circuit that can write the transmission status flag 124 to the local memory 104 or can read a block from the local memory 104. For this block read operation, the transmit DMAC 137 includes a length counter and an address counter that are initialized to the length of the block and the start address of the block.

A command to the transmission DMAC 137 is obtained from the transmission address conversion circuit 138 and the transmission sequencer 130. For a block read operation, a local memory read request is generated using the current value of the address counter output to the address and data bus 107, and the address counter is incremented and decremented from the length counter until the length becomes zero. Is done.

The data read from the local memory 104 is stored in the TCWB buffer 117 or the transmission FIFO data buffer 136 under the control of the transmission sequencer 130. The transmission node number register 139 stores each node 1
02, including a number that identifies that node.

The page size register 140 indicates a page size per page when the virtual address space is divided into a plurality of pages. The TLB address register 141 indicates the start address of the transmission address conversion table 125 in the local memory 104.

The packet assembler 142 extracts information from the transmission node number register 139 to form a packet header in the TCWB buffer 117, extracts data from the transmission FIFO data buffer 136, and
, And sends out the complete packet 108 to the network 101.

To send one or more packets 108 for node 102 to one or more other nodes 102, instruction processor 103 in transmitting node 102 first sends a local The TCWB 129 is created in the memory 104.

The instruction processor 104 includes a TCWB 12
Initialize each field included in 9. Type 13
2 indicates an initialized packet type. In this example, since all packet types are the same, the type 132 is a fixed value.

The division enable 133 specifies whether to limit the length of data transmitted in one packet.
The transmission data offset 134 indicates the head address of transmission data in the virtual address space, and
When the transmission data is read from the address No. 4, it is necessary to convert the data into a real address, which will be described later. The data length 111 indicates the length of data to be transferred. Destination node number 112 identifies the destination node for the packet. The received data offset 113 indicates the head address of the received data in the virtual address space. When writing the received data to the local memory 104, it is necessary to convert the received data into a real address, which will be described later. The reception flag offset 114 is the local memory 1 of the destination node.
04 shows where the reception state flag 127 should be pointed. To point it, it is necessary to convert it into a real address, which will be described later.

To start the packet transmission process, the instruction processor 104 uses the address and data bus 107 to set the start address of the TCWB 129 to the TCW.
Write to the B address register 131. Transmission sequencer
xxx starts operation by writing to this register.

First, the transmission sequencer 130 instructs the transmission DMAC 137 to read the TCWB 129 using the address written in the TCWB address register 131. TCWB 129 is an address and data bus 10
7 and read from local memory 104 and T
It is stored in the CWB buffer 117. Next, when the transmission sequencer 130 instructs the transmission address conversion circuit 138 to read out transmission data, it is necessary to pass three pieces of information: offset information, transmission data length information, and division pattern information. However, the value differs depending on whether the division enable 133 in the TCWB buffer 129 is valid or invalid.

If the split enable 133 is invalid,
In this example, when it is 0 ', the transmission address conversion circuit 138
, The transmission data length information, and the division pattern information are as follows. (Offset information) = (Transmission data offset 134 in TCWB buffer 117) (Transmission data length information) = (Data length 111) (Division pattern information) = 00 'When division enable 133 is valid, 1' in this example.
, The data length 11 in the TCWB buffer 117
The processing of the transmission sequencer 130 is divided into two depending on whether 1 is larger or smaller than the fragmented packet length (in this example, a fixed value).

When the data length 111 is equal to or smaller than the fragmented packet length, the transmission data offset 134, the data length 111, and the fragmentation pattern information 00 'in the TCWB buffer 117 are transmitted as in the case where the fragmentation enable 133 is 0'. This is passed to the conversion circuit 138.

When the data length 111 is larger than the divided packet length, the packet is transmitted in a plurality of packets so that the data length of the packet is not larger than the divided packet length. Therefore, the transmission sequencer 130 issues a transmission data read command to the transmission address conversion circuit 138 by dividing the transmission data into a plurality of pieces.

In the first transmission data read command of the division, the offset information, the transmission data length information, and the division pattern information are as follows. (Offset information) = (Transmission data offset 134 in TCWB buffer 117) (Transmission data length information) = Division packet length (Division pattern information) = 10 ′ In a read instruction of transmission data in the middle of division, offset information and transmission data length The information and the division pattern information are as follows. (Offset information) = (Transmission data offset 134 in TCWB buffer 117) + ((Division packet length) ×
((Order from start of division) -1)) (transmission data length information) = division packet length (division pattern information) = 11 'In the last transmission data read command of division, offset information, transmission data length information, division The pattern information is as follows. (Offset information) = (Transmission data offset 134 in TCWB buffer 117) + ((Division packet length) ×
((Order from start of division) -1)) (Transmission data length information) = (Remainder of transmission data length divided by division packet length) (Division pattern information) = 01 'FIG. 5 shows virtual address space and real address space. Shows the relationship. The virtual address space 149 is divided into a plurality of pages 150, and is assigned to a continuous area on the real address space 151 in page units. The page size is determined by the page size register 140. In addition, transmission data 1
Since the size of 23 is not related to the page size, it may extend over a plurality of pages 150. However, in this example, the case where the transmission data 123 does not extend over a plurality of pages 150 is described. When the corresponding page number is determined, it is converted to a real address by referring to the transmission address conversion table 125 in the local memory 104. The transmission address conversion table 125 is arranged in a continuous address area on the local memory 104 in order from page number 0, 1, 2,... N, and the head address of the transmission address conversion table 125 is TLB.
This is shown in the address register 141. The head address of the transmission data in the virtual address space is indicated by the transmission data offset 134 in the TCWB 129, and it is possible to determine on which page the transmission data 123 exists. The head real address of the corresponding page 150 is obtained from the transmission address conversion table. Further, the remainder obtained by dividing the transmission data offset 134 by the page size is the transmission data offset in the page, and the value obtained by adding this offset to the top real address of the corresponding page 150 obtained earlier is the top real address of the transmission data. Become.

The transmission address conversion circuit 138 obtains the head real address and transmission data length of the transmission data in the local memory 104, instructs the transmission DMAC 137 to read the data, and improves the efficiency of the conversion from the virtual address to the real address. Of the transmission TLB cache 143 to be used for Details are performed according to the procedure shown in FIGS.

First, the transmission address conversion circuit 138
To determine the page number in the virtual address space, the quotient is calculated by dividing the offset information by the value of the page size register.

Second, the transmission address conversion circuit 138 checks whether or not the transmission TLB cache 143 has the previously obtained page number. Transmission TLB cache 1
As shown in FIG. 2, a plurality of entries 43 include a valid element 145, an overwrite 146, a page number 147, and a head real address 148 in the page as one entry 144. Transmission TLB cache 14
By looking at all entries 144 of the third entry, a search is made to determine whether there is an entry 144 in which the valid 145 is valid and has the same page number. When the entry 144 exists, the process proceeds to the processing of the tenth item.

Third, if the same entry 144 does not exist, the transmission address conversion table 12 in the local memory 104
It is necessary to find the start address of the entry in 5. The page number previously obtained is multiplied by a TLB entry size, in this example, a fixed value, and the TLB address register 14
Add the value of 1.

Fourth, when the head address of the entry is obtained, the transmission DMAC 137 is instructed to read the entry from the local memory 104.

Fifth, wait for an entry to be read from local memory 104.

Sixth, it is determined whether or not the entry 144 in the transmission TLB cache 143 has an entry 144 that can be overwritten. Specifically, it is determined whether or not an entry with an overwrite 146 of 1 ′ exists in the entry 144 in the transmission TLB cache 143.

Seventh, if there is an entry 144 whose validity 145 is 1 'and the overwrite 146 is 1' among the entries 144 in the transmission TLB cache 143, the local memory is assigned to the entry 144. Overwrite the entry read from 104. Specifically, the page number obtained by the above calculation and the local memory 104
Then, the head real address of the corresponding page in the entry read out is written. If there is no entry 144 in which the valid 145 is 1 'and the overwrite 146 is 1', one TLB entry is selected according to a rule such as the FIFO method or the LRU method. If the valid 145 of the selected TLB entry is 1 ', the read entry is overwritten, and if the valid 145 is 0', a newly read entry is registered. Creating an entry means
In addition to the above-described overwriting process, a valid 145
To 1 ′. The valid 145 indicates whether the entry 144 itself is valid or invalid, and is generally information on the entry 144 managed by a FIFO method, an LRU method, or the like.

Eighth, entry 1 overwritten or registered
It is determined whether to perform the overwriting setting for 44. The overwrite setting is the overwrite 1 of the entry 144
46 is set. There are the following four determination conditions. Condition 1 is the entry of the first page of the transmission data with the division pattern information of 00 '. Condition 2 An entry of the last page of the transmission data with the division pattern information of 00 '. Condition 3 The division pattern information is 10 'and the entry of the first page of the transmission data. Condition 4 The division pattern information is 01 'and the entry is the last page of the transmission data.

Ninth, if none of the above four conditions is satisfied, the overwrite 146 is set to 1 '. If either of these holds, the overwrite 146 is set to 0 '. By setting the overwrite 146 of the entry of the first and last pages of the transmission data of the undivided packet to 0 'according to the above conditions 1 and 2,
Although the overwriting in the above-described item 7 is not performed, the overwriting in the item 7 is performed by setting the overwrite 146 of the entry of the middle page to 1 ′. Also, according to the above conditions 3 and 4, the entry of the first page of the transmission data of the divided first packet and the overwrite 146 of the entry of the first page of the transmission data of the divided last packet are set to 0 '. , The overwriting in the seventh term is not performed. However, when attention is paid to continuous transmission data before division, the overwriting 146 of the entry of the middle page is set to 1 ′, thereby overwriting in the seventh term. Will be performed.

Tenth, the T of the page number obtained in the fourth item
The head real address of the transmission data is obtained by using the head real address of the corresponding page in the LB entry. The value obtained by dividing the head address information of the transmission data by the page size and adding the remainder to the head real address of the corresponding page is the head real address of the transmission data.

As described above, the transmission address conversion circuit 1
Numeral 38 obtains the head real address of the transmission data and transfers it to the transmission DMAC 137 together with the transmission data length information to instruct data reading.

The transmission sequencer transmits the transmission data read from the local memory 104 to the FIFO data buffer 14.
1 and then pass the divided pattern information to the packet assembling section 142 to instruct the start of transmission of the packet 108.

The packet assembling section 142 first sets a fixed start code 1 for marking the start of the packet 108.
Send 09. Also, the packet assembling unit 142
WB buffer 117 and transmission node number register 139,
3 of the divided pattern information passed from the transmission sequencer 130
Then, a type 132, a division pattern 110, a destination node number 112, a reception data offset 113, a reception flag offset 114, and a transmission source node number 115 are extracted and transmitted.

Next, the packet assembler 142 sends the transmission F
The transmission data is taken out from the IFO data buffer 136 and sent to form the packet data 116. The transmission FIFO data buffer 136 stores the transmission data read from the local memory 104 by the transmission DMAC 137 in parallel with this.

When all the transmission data has been transmitted, the packet assembling section 142 notifies the transmission sequencer 130 of the completion of the packet transmission processing. The transmission sequencer 130 passes the transmission flag offset 135 stored in the TCWB buffer 117 to the transmission address conversion circuit 138, and sends a value indicating that the packet has been transmitted to the transmission state flag 1
24 to be written. In this example, the transmission status flag 124 may have one of two possible values, meaning that the packet 108 has been transmitted or not yet transmitted.

In this example, the transmission status flag 124 is smaller than the page size in the virtual address space, and the value of the transmission flag offset 135 is limited in advance so as not to cross two pages. Therefore, the case where the transmission status flag 124 does not extend over a plurality of pages will be described as in the case of the transmission data read command.

First, the transmission address conversion circuit 138
To determine the page number in the virtual space, the quotient is calculated by dividing the transmission flag offset by the value of the page size register.

Second, the transmission address conversion circuit 138 checks whether or not the transmission TLB cache 143 has the previously obtained page number. Specifically, the transmission TLB
By looking at all the entries 144 in the cache 143, it is searched whether there is an entry 144 in which the valid 145 is valid and has the same page number. If the entry 144 exists, the process proceeds to the processing in the ninth section.

Third, if there is no identical entry, the page number previously obtained is multiplied by the entry size, in this embodiment, a fixed value, in order to find the entry address in the local memory 104. Add values.

Fourth, when the entry address is obtained, the transmission DMAC 137 is instructed to read the entry indicated by the entry address from the local memory 104.

Fifth, wait for an entry to be read from local memory 104.

Sixth, it is checked whether or not the entry 144 in the transmission TLB cache 143 has an entry 144 that can be overwritten. Specifically, it is determined whether or not an entry with an overwrite 146 of 1 ′ exists in the entry 144 in the transmission TLB cache 143.

Seventh, if there is an entry in the transmission TLB cache 143 whose validity 145 is 1 'and whose overwrite 146 is 1',
The entry 144 is overwritten with the entry read from the local memory 104. Specifically, the page number obtained by the above calculation and the head real address of the corresponding page in the read entry are written. Valid 145
Is 1 'and the overwrite 146 is 1', there is no entry 144 according to a rule such as the FIFO method or the LRU method. When the valid 145 of the selected entry 144 is 1 ', the read entry is overwritten, and the valid 145 becomes 0'.
If so, the newly read entry 144 is registered. The registration of the entry 144 indicates that the valid 145 is set to 1 'in addition to the above-described process at the time of overwriting.

Eighth, entry 1 overwritten or registered
44 is overwritten. The overwrite setting refers to setting the overwrite 146 of the entry. Since the transmission state flag 124 is smaller than the page size as described above and may be reused, the overwrite 146 is set to 0 '.

Ninth, the head real address 148 of the relevant page in the entry 144 of the page number obtained in the fourth item
Is used to determine the actual start address of the transmission status flag 124. The value obtained by dividing the transmission flag offset 135 by the page size and adding the remainder to the head real address 148 of the corresponding page is the head real address of the transmission state flag 124.

As described above, the transmission address conversion circuit 1
38 determines the head real address of the transmission status flag 124 and passes it to the transmission DMAC 137 to send the transmission status flag 12
4 is instructed.

The network 101 receives the packet 108 from the transmitting circuit 105, and receives the destination node number 112
In the receiving circuit 106 of the destination node.
08 is transferred. The network 101 of the present example is configured such that, when a plurality of packets 108 are sent from one node to another node, the packets 108 enter the transmission order.

FIG. 6 is a block diagram of the receiving circuit 106. The reception sequencer 501 sets the packet reception status flag 1
The entire reception circuit 106 including the writing process 27 is controlled. Packet header buffer 502 is used to temporarily store a copy of the packet header. The format of this buffer 502 is almost the same as that of the packet header, that is, the packet type 503,
It includes a division pattern 504, a data length 505, a reception data offset 506, a reception flag offset 507, and a source node number 508.

When the packet 101 arrives, the packet receiving unit 509 notifies the reception sequencer 501 of the arrival, and stores the packet header in the packet header buffer 502 and the received data in the reception FIFO data buffer 510. Receive FIFO data buffer 510
Is a buffer that receives data from the network 101 and buffers the data before it is written to the local memory 104.

Receive direct memory access controller 51
2 (hereinafter referred to as reception DMAC) is a reception state flag 12
7 can be written to the local memory 104, or a block can be written to the local memory 104. For this block write operation,
The receive DMAC 512 includes a length counter and an address counter that are initialized to the length of the block and the start address of the block.

A command to receive DMAC 512 is obtained from receive address conversion circuit 511 and receive sequencer 501. For a block write operation, a local memory write request is generated using the current value of the address counter output on the address and data bus 107, and the address counter is incremented and decremented from the length counter until the length becomes zero. Is done.

Hereinafter, the operation of the receiving circuit 106 will be described.
The packet receiving unit 509 in the receiving circuit 106
When the start marker 109 of 08 is received, the reception sequencer 501 is notified of the arrival of the packet. Markers from the rest of the received packet are separated and discarded. Of the packet header, only the field corresponding to the header buffer 502 is stored in the header buffer 502, and the data is stored in the reception FIFO data buffer 510 using the data length 111 of the packet header.

When the reception sequencer 501 instructs the reception address conversion circuit 511 to write the reception data, the reception sequencer 501 passes three pieces of information: offset information, reception data length information, and division pattern information. The three pieces of information are as follows. (Offset information) = (Packet header buffer 502)
(Received data length information) = (Received data length 505) (Divided pattern information) = (Packet header buffer 502)
The received address conversion circuit 511 determines the head real address of the received data in the local memory 104 and the length of the received data and writes the data to the receive DMAC 512, and the conversion efficiency of the virtual address to the real address. The reception TLB cache 513 used for improvement is managed. Details are performed according to the procedure shown in FIGS.

First, the reception address conversion circuit 511
To determine the page number in the virtual address space, the quotient is calculated by dividing the offset information by the value of the page size register.

Second, the reception address conversion circuit 511 checks whether or not the reception TLB cache 513 has the previously obtained page number. Receive TLB cache 5
As shown in FIG. 6, a plurality of entries 516 include a valid element 517, an overwrite 518, a page number 519, and a four-element real address 520 as one entry 516. Receive TLB cache 51
By looking at all of the entries 516 of No. 3, it is determined whether there is an entry 516 in which the valid 517 is valid and has the same page number. If the entry 516 exists, the process proceeds to the processing of the tenth item.

Third, when the same entry 516 does not exist, the reception address conversion table 12 of the local memory 104
It is necessary to find the start address of the entry in the block 8. The page number previously obtained is multiplied by a TLB entry size, in this example, a fixed value, and the TLB address register 51 is multiplied.
The value of 5 is added.

Fourth, when the head address of the entry is obtained, the receiving DMAC 512 is instructed to read the entry from the local memory 104.

Fifth, wait for an entry to be read from local memory 104.

Sixth, it is checked whether or not the entry 516 in the reception TLB cache 513 has an entry 516 that can be overwritten. Specifically, it is checked whether or not an entry with an overwrite 518 of 1 'exists in the entries 516 in the reception TLB cache 513.

Seventh, if there is an entry 516 whose validity 517 is 1 'and its overwrite 518 is 1' among the entries 516 in the reception TLB cache 513, the local memory is assigned to the entry 516. Overwrite the entry read from 104. Specifically, the page number obtained by the above calculation and the local memory 104
Then, the head real address of the corresponding page in the entry read out is written. If there is no entry 516 in which the valid 517 is 1 'and the overwrite 518 is 1', one TLB entry is selected according to a rule such as the FIFO method or the LRU method. When the valid 517 of the selected TLB entry is 1 ', the read entry is overwritten, and when the valid 517 is 0', the newly read entry is registered. Creating an entry means
In addition to the above-described overwriting process, a valid
To 1 ′. The valid 517 indicates whether the entry 516 itself is valid or invalid, and is generally information on the entry 516 managed by the FIFO method, the LRU method, or the like.

Eighth, the overwritten or registered entry 5
Then, it is determined how to perform the overwrite setting for the 16. The overwrite setting is the overwrite 5 of the entry 516.
18 is set. There are the following four determination conditions. Condition 1 is the entry of the first page of the received data with the division pattern information of 00 '. Condition 2 The division pattern information is 00 'and the entry is the last page of the received data. Condition 3 The division pattern information is 10 'and the entry is the first page of the received data. Condition 4 The division pattern information is 01 'and the entry is the last page of the received data.

Ninth, if none of the above four conditions is satisfied, the overwrite 518 is set to 1 '. If either of these holds, the overwrite 518 is set to 0 '. By setting the overwrite 518 of the entry of the first and last pages of the received data of the undivided packet to 0 'according to the above conditions 1 and 2,
Although the overwriting in the above-described item 7 is not performed, the overwriting in the item 7 is performed by setting the overwrite 518 of the entry of the middle page to 1 ′. Also, according to the above conditions 3 and 4, the entry of the first page of the received data of the divided first packet and the overwrite 518 of the entry of the first page of the received data of the divided last packet are set to 0 '. , The overwriting in the seventh term is not performed. However, when attention is paid to continuous received data before division, the overwriting 518 of the entry of the middle page is set to 1 ′, thereby overwriting in the seventh term. Will be performed.

Tenth, the T of the page number obtained in the fourth item
The head real address of the received data is obtained by using the head real address of the corresponding page in the LB entry. The value obtained by dividing the head address information of the received data by the page size and adding the remainder to the head real address of the corresponding page is the head real address of the received data.

As described above, the reception address conversion circuit 5
Numeral 11 finds the start real address of the received data and transfers it to the receiving DMAC 1512 together with the received data length information to instruct data writing.

When the length counter in the reception DMAC 512 is 0
When this happens, all of the received data has been written to the local memory 104. The reception sequencer 501 passes the reception flag offset 507 stored in the packet header buffer 502 to the reception address conversion circuit 511, and sets a value indicating that the packet has been received to the reception state flag 1
27 is written. In this example, the reception state flag 1
27 may have one of two possible values meaning that the packet 108 has been received or not yet received. In this example, the reception state flag 127 is smaller than the page size in the virtual address space, and the value of the reception flag offset 507 is limited in advance so as not to cross two pages. As in the case of the received data write command, a case where the reception state flag 127 does not extend over a plurality of pages will be described.

First, the transmission address conversion circuit 138
To determine the page number in the virtual space, the quotient is calculated by dividing the transmission flag offset by the value of the page size register.

Second, the reception address conversion circuit 511 checks whether or not the reception TLB cache 513 has the previously obtained page number. Specifically, the reception TLB
By looking at all the entries 516 in the cache 513, it is searched whether there is an entry 516 in which the valid 517 is valid and has the same page number. If the entry 516 exists, the process proceeds to the processing in the ninth section.

Third, if there is no identical entry, the page number previously obtained is multiplied by the entry size, in this embodiment, a fixed value, in order to find the entry address in the local memory 104. Add values.

Fourth, when the entry address is obtained, the receiving DMAC 512 is instructed to read the entry indicated by the entry address from the local memory 104.

Fifth, wait for an entry to be read from local memory 104.

Sixth, it is confirmed whether or not the entry 516 in the reception TLB cache 513 has an entry 516 that can be overwritten. Specifically, it is checked whether or not an entry with an overwrite 517 of 1 ′ exists among the entries 516 in the reception TLB cache 513.

Seventh, if there is an entry in the reception TLB cache 513 whose validity 517 is 1 'and whose overwrite 518 is 1',
The entry 516 is overwritten with the entry read from the local memory 104. Specifically, the page number obtained by the above calculation and the head real address of the corresponding page in the read entry are written. Valid 517
Is 1 'and the overwrite 518 is 1', there is no entry 516, and one entry 516 is selected by a rule such as the FIFO method or the LRU method. If the valid 517 of the selected entry 516 is 1 ', the read entry is overwritten, and the valid 517 is 0'.
If so, the newly read entry 516 is registered. The registration of the entry 516 indicates that the valid 517 is set to 1 ′ in addition to the above-described process at the time of overwriting.

Eighth, the overwritten or registered entry 5
16 is overwritten. The overwrite setting refers to setting the overwrite 518 of the entry. As described above, the reception state flag 127 is smaller than the page size, and there is a possibility of being reused. Therefore, the overwrite 518 is set to 0 '.

Ninth, the head real address 520 of the relevant page in the entry 516 of the page number obtained in the fourth item
Is used to determine the head real address of the reception status flag 127. The value obtained by dividing the reception flag offset 506 by the page size and adding the remainder to the head real address 520 of the corresponding page is the head real address of the reception status flag 127.

As described above, the reception address conversion circuit 5
11 obtains the head real address of the reception status flag 127 and passes it to the reception DMAC 512 to obtain the reception real flag 12.
7 is written.

The instruction processor 103 of the destination node can confirm the reception of the packet 108 by reading the reception state flag 127 of the packet 108 at an arbitrary time.

According to the embodiment of the present invention, when transferring continuous data between a plurality of nodes, the use efficiency of the TLB cache is increased by preventing the address conversion table entry having a low use efficiency from being resident in the TLB cache. This provides a means for speeding up address translation.

[0082]

In the parallel computer system of the present invention, a field is provided to indicate whether each page entry in the TLB cache can be overwritten or not. Can be prioritized so that data can be overwritten immediately or at the end of data. As a result, there is a page entry corresponding to the first or last page of data that is not yet used for data transfer and is likely to be reused, and all areas are used for data transfer. Since the page entries can be handled separately, the possibility of overflow due to another data transfer before reuse is reduced, and the use efficiency of the TLB cache is increased, so that high-speed address translation can be expected.

[Brief description of the drawings]

FIG. 1 is a block diagram of hardware incorporating an address conversion function and a packet division function.

FIG. 2 is a block diagram of a transmission circuit incorporating the present invention.

FIG. 3 is a diagram showing an address conversion processing procedure of transmission data in a transmission address conversion circuit incorporating the present invention.

FIG. 4 is a view showing a procedure of an address conversion process of transmission data subsequent to FIG. 3A.

FIG. 5 is a diagram illustrating a relationship between a virtual address space, a real address space, and an address conversion table when an address of transmission data is converted;

FIG. 6 is a block diagram of a receiving circuit incorporating the present invention.

FIG. 7 is a diagram showing an address conversion processing procedure of reception data in a reception address conversion circuit incorporating the present invention.

FIG. 8 is a view showing a procedure of an address conversion process of received data following FIG. 7a.

FIG. 9 is a diagram showing a conventional relationship between a virtual address space and a real address space when converting addresses of data to be transferred.

[Explanation of symbols]

101 network, 102 node, 103 instruction processor, 104 local memory, 105 transmission circuit,
106: receiving circuit, 107: address and data bus, 108: packet, 109: start code, 11
0: division pattern, 111: data length, 112: destination node number, 113: reception data offset, 114: reception flag offset, 115: destination node number, 116
... Data, 117 ... TCWB buffer, 118 ... Transmission controller, 121 ... Reception controller, 123 ... Transmission data, 124 ... Transmission status flag, 125 ... Transmission address conversion table, 126 ... Reception data, 127 ... Reception status flag, 128 ... Reception Address conversion table, 129
Transfer control word block (TCWB), 131 ... TCW
B address register, 132 type, 133 division enable, 134 transmission data offset, 135 transmission flag offset, 136 transmission FIFO data buffer, 137 transmission DMAC, 138 transmission address conversion circuit, 139 transmission node number register 140, page size register, 141, TLB address register, 142, packet assembler, 143, transmission TLB
Cache, 144: Page entry, 145: Valid, 146: Overhead, 147: Page number, 1
48: top real address in page; 149: virtual address space; 150: page; 151: real address space;
1 ... Reception sequencer, 502 ... Packet header buffer, 503 ... Type, 504 ... Division pattern, 505 ... Data length, 506 ... Reception data offset, 507 ... Reception flag offset, 508 ... Source node number, 509
.., A packet reception unit, 510, a reception FIFO data buffer, 511, a reception address conversion circuit, 512, a reception DM
AC, 513: TLB cache received, 514: Page size register, 515: TLB address register, 5
16 page entry, 517 valid, 518 overwrite, 519 page number, 520 top real address in page, 701 data, 702 virtual address space, 703 real address space, 704 page.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) G06F 15/163 650 G06F 15/163 650A

Claims (2)

[Claims] 1. A computer system comprising a plurality of processing nodes connected by a network and transferring data between nodes via a network while performing address conversion, comprising an address translation entry corresponding to the data to be transferred. A parallel computer system wherein a position corresponding to data to be transferred of an address translation entry can be determined when selecting from an address translation table and registering it in an address translation table cache. 2. A computer system comprising a plurality of processing nodes connected by a network and transferring data between nodes via a network while performing address conversion, wherein an address translation entry corresponding to the data to be transferred is stored in a computer system. When selecting from the address translation table and registering it in the address translation table cache, information that can be prioritized in the cache by a position corresponding to the data to be transferred of the address translation entry is included in the entry of the cache. Parallel computer system.