JP2002259204A - Storage processing method for flash memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To access data in a short time without increasing the memory capacity of a flash memory. SOLUTION: Data are written to the flash memory 4, and the last address of the data stored in the flash memory 4 is also stored in a nonvolatile memory 8. In the case of reading data, the last address of the data is detected from the nonvolatile memory 8 to read the data of the flash memory 4. The flash memory 4 has to store only data, does not have to store an address, etc., and therefore, does not need memory capacity so much. The data of the flash memory 4 can be read in a short period of time because the data can be read from the last address stored in the nonvolatile memory 8. For service interruption, etc., in particular, the data are stored in the above manner, the data of the flash memory 4 can be quickly read when a CPU 1 is restarted in the case the service is restored.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flash memory storage processing method, and is particularly useful for retaining data during a power failure.

[0002]

2. Description of the Related Art FIG. 9 is a memory block diagram of a conventional flash memory disclosed in, for example, Japanese Patent Application Laid-Open No. Hei 8-17192. FIG. FIG. 9 is an explanatory diagram of a method of overwriting.

FIG. 10 (a) shows one memory block of FIG. 9 taken out. At the first power failure, the first data (shown as 1st) is written from the beginning of the block, and the pointer is set to a bit ( The data position is displayed by placing it at the tail of the block (unit) and dropping one bit at a time.

FIG. 10 (b) shows the second data (2) in the next power failure following the data written in FIG. 10 (a).
nd) is written next to the first data,
The pointer is dropped from "1" to "0" at the position immediately to the left of the first data pointer, and the address is written.

[0005] Similarly, FIG.
0 (c) is the third data (3rd
Is written, and the pointer is dropped from “1” to “0” and stored at the position immediately to the left of the second data pointer.

[0006]

A conventional flash memory storage processing method is formed as described above. A plurality of data and an address of the data are stored in a memory block (sector), and the address is stored in the address. Since data is accessed based on this, there is a problem that the data capacity in a memory block (sector) increases and the access time to data increases.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and provides a method of accessing data in a short time without increasing the memory capacity of a memory block (sector), and at the time of power interruption or power failure. It is an object of the present invention to provide a flash memory storage processing method in which the address of data lastly stored in the flash memory can be accessed in a short time when the CPU is restarted in a recovery after an hour.

In the present invention, a nonvolatile memory is used separately from the flash memory. However, it is necessary to extend the life of the nonvolatile memory so as not to exceed the allowable number of times of writing. A second object is to obtain a stable flash memory storage processing method by extending the life of a nonvolatile memory.

[0009]

According to the storage processing method of a flash memory according to the present invention, the step of writing the last address of each data into the nonvolatile memory includes the steps of: writing a plurality of addresses in a memory area of the nonvolatile memory; Assign the final address of the data as the write address,
The step of allowing the plurality of addresses to be written in a ring and sequentially writing the final address of the arbitrary data to enable continuous writing, and the step of detecting the final address of the data to be read stored in the nonvolatile memory, This is a step of detecting the last address stored in the last written address among the plurality of addresses in a ring shape.

The step of writing the last address of each data to the nonvolatile memory includes allocating a plurality of addresses to the memory area of the nonvolatile memory as addresses for writing the last address of any data, In the form of a ring and sequentially writing the final address of the arbitrary data to enable continuous writing. The step of detecting the final address of the data to be read stored in the non-volatile memory includes a plurality of ring-shaped steps. This is a step of detecting the last address stored in the last written address among the addresses.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1 FIG. 1 is a circuit block diagram illustrating a flash memory storage method according to Embodiment 1 of the present invention. In FIG. 1, 1 is a CPU.
(Central processing unit), externally input data 2
Is stored in an internal buffer 3 and a flash memory (Fush. El.) Connected by an address bus 5 and a data bus 6
electricallyly. Erasable. Progr
available. Read. Only. Memory) 4
Is controlled by the control signal 7.

Reference numeral 8 denotes a nonvolatile memory (Electrica)
lly. Erasable. Programmable.
Read. Only. Memory), data is transmitted and received to and from the CPU by a serial signal 9, and is controlled by a control signal 10. Reference numeral 11 denotes a capacitor for performing data processing during a power failure.

FIG. 2 is a flowchart for explaining a data write operation according to the first embodiment of the present invention, and FIG. 3 is a diagram showing a memory area of the flash memory and the nonvolatile memory at the time of data write. Hereinafter, the data write operation will be described with reference to FIGS. (1) The CPU 1 reads the external data 2 (n-byte data X and m-byte data Y) and stores them in the buffer 3. (Step 201)

(2) While controlling the flash memory 4 by the control signal 7, the CPU 1 designates a write address (An) by the address bus 5, writes data X by the data bus 6, and writes data X to the address A. Repeat n times until memorizing. (Step 202, Step 203)

(3) The last address A of the flash memory 4 is stored at a predetermined address a of the nonvolatile memory 8. (Step 204) (4) The m-byte data Y stored in the buffer 3 is similarly written to the address A + 1. The processing is repeated m times until the data Y is stored at the address A + m + 1. (Step 205, Step 206) (5) The last address A + m + 1 of the flash memory 4 is stored at a predetermined address b in the nonvolatile memory 4. (Step 207) As shown in FIG. 3, the data and the final address of each data are stored. Note that these data are usually written byte by byte in a predetermined sector.

FIG. 4 is a flowchart for explaining a data read operation according to the first embodiment of the present invention, and FIG. 5 is a diagram showing a memory area of the flash memory and the nonvolatile memory when data is written. The data read operation will be described with reference to FIG. 1, FIG. 4 and FIG. (11) The CPU 1 reads the last address A of the flash memory 4 from the address a of the nonvolatile memory 4. (Step 301)

(12) While controlling the flash memory 4 by the control signal 7, the CPU 1 designates a read address (An) by the address bus 5 and reads data X by the data bus 6. This operation is repeated n times until the data X at the address A is read. (Step 302, Step 30
3) The CPU 1 recognizes that data is read from the address (An) to the address A, and performs the operation of reading the data X.

(13) The read n-byte data X is stored in the buffer 3. (Step 304) (14) Similarly, the CPU 1 reads the last address A + m + 1 of the flash memory 4 from the address b of the nonvolatile memory 4. (Step 305)

(15) While controlling the flash memory 4 with the control signal 7, the CPU 1 specifies a read address (A + m + 1) by the address bus 5 and reads data Y by the data bus 6. The processing is repeated m-1 times until the data Y at the address A + 1 is read. (Step 306,
307) (16) Store the read m-byte data Y in the buffer 3. (Step 308) As shown in FIG. 5, the final address of the data and the data are read.

As described above, according to the first embodiment, data can be accessed in a short time without increasing the memory capacity of a memory block (sector). In particular, at the time of a power failure, data is stored by the stored power of the capacitor 11, and the data stored in the flash memory 4 is read from the last address of the flash memory 4 written in the nonvolatile memory 8 at the time of power recovery. Since the flash memory stores only data, it is not necessary to increase the memory capacity, and data can be accessed in a short time.

Embodiment 2 FIG. Although the last address of each data is stored in the non-volatile memory in the first embodiment,
Non-volatile memories have a lifetime, and cannot be stored when the number of times of writing exceeds a predetermined number of times. For example, the number of times of writing to the same memory area is said to be 100,000 times. The second embodiment of the present invention is intended to prevent the memory from becoming unstorable due to exceeding the number of times of writing permitted by the nonvolatile memory.

FIG. 6 is a diagram for explaining a memory area of the nonvolatile memory according to the second embodiment of the present invention. FIG. 7 is a diagram for explaining a data read operation from the nonvolatile memory according to the second embodiment of the present invention. FIG. FIG. 8 is a diagram showing a relationship with the memory area of the nonvolatile memory according to the first embodiment. Hereinafter, an operation of reading data from the nonvolatile memory according to the second embodiment of the present invention will be described.

In FIG. 6, a plurality of addresses from address c to address c + 2 are used as a memory area of the nonvolatile memory 8 for storing the last address of one data, and these addresses are formed into a ring shape to form the final address. Each time is written, the address is sequentially advanced. And FIG.
When updating data as shown in (a) to (b), the address c
When writing of data to the address +1 is completed, the previous address c is erased (all 1s) to enable continuous writing. By doing so, the number of times the same memory area is used is reduced, and the life of the nonvolatile memory can be extended.

When data is stored in the flash memory 4 at the time of a power failure and the last address of the data is stored in the nonvolatile memory 8, reading of data at the next power recovery is shown in the flowchart of FIG. .

(101) The data at the address c in the non-volatile memory is read (step 401), and it is confirmed that the data is all 1s. (Step 402) (102) If the address is other than all 1, the last address of the flash memory is set (Step 407), and the above-described read processing from the flash memory 4 (Step 30 in FIG. 4)
2, 306). (103) If it is all 1, address c + 1 is read out (step 403), and it is confirmed that it is all 1. (Step 404)

(104) If the address is other than all 1, the last address of the flash memory is set (step 407), and the above-described read processing from the flash memory 4 (steps 302 and 306 in FIG. 4) is performed. (105) Thereafter, similarly, address c + 2 is read and data other than 1 is confirmed. (Steps 405 and 406)

As described above, since the final address of the data to be stored in the nonvolatile memory 8 is continuously written in a ring shape, the number of times of writing to the same location of the nonvolatile memory 8 can be reduced. Thus, the life of the memory can be extended.

FIG. 8 shows that the final addresses of the data X and data Y described in the first embodiment are stored in the address a and the address b of the nonvolatile memory 8, respectively.
Is an example showing the relationship with the address c shown in FIG. In FIG. 8, the final addresses of the data X and data Y are written to the addresses a and b of the nonvolatile memory 8, and when the next data (for example, data Z) is written, the final addresses of the nonvolatile memory 8 are written. When writing to address c and then writing to address c, write to address c + 1.

In FIG. 8, the address a of the nonvolatile memory 8 is also assigned to the addresses a + 1 and a + 2 and the memory area, and the address b is assigned to the addresses b + 1 and b + 2 and the memory area. .

[0030]

As described above, according to the present invention, data can be accessed in a short time without increasing the memory capacity of the flash memory. This is particularly useful when data is stored during a power outage and data is read out when the power is restored.

Further, the life of the nonvolatile memory can be extended.

[Brief description of the drawings]

FIG. 1 is a circuit block diagram illustrating a flash memory storage method according to a first embodiment of the present invention.

FIG. 2 is a flowchart illustrating a data write operation according to the first embodiment of the present invention.

FIG. 3 is a diagram illustrating a memory area when writing data in the flash memory and the nonvolatile memory according to the first embodiment of the present invention;

FIG. 4 is a flowchart illustrating a data read operation according to the first embodiment of the present invention.

FIG. 5 is a diagram illustrating a memory area at the time of data reading of the flash memory and the nonvolatile memory according to the first embodiment of the present invention.

FIG. 6 is a diagram illustrating a memory area of a nonvolatile memory according to a second embodiment of the present invention.

FIG. 7 is a diagram illustrating a memory area of a nonvolatile memory according to a second embodiment of the present invention. It is a flowchart explaining.

FIG. 8 is a diagram illustrating a memory area of a nonvolatile memory according to a second embodiment of the present invention.

FIG. 9 is a memory block diagram of a conventional flash memory.

FIG. 10 is a diagram illustrating a method of overwriting data at an address of the flash memory in FIG. 9 where data is written.

[Explanation of symbols]

1 CPU, 2 external data inputs, 3 buffers, 4
Flash memory, 5 address bus, 6 data bus, 7 control signal, 8 nonvolatile memory, 9
Serial data, 10 control signals, 11 capacitors.

Claims (2)

[Claims] In a flash memory storage processing method for reading and writing data in a flash memory based on a command from a CPU, when writing data in the flash memory, each data is stored in a sector of the flash memory for each byte. A writing step, and a step of preparing a nonvolatile memory and writing a final address of each data written in the flash memory. When reading data from the flash memory, the nonvolatile memory stores the data. A flash memory storage processing method, comprising: detecting a last address of data to be read; and reading corresponding data of the flash memory based on the detected last address. 2. The step of writing the last address of each data to the nonvolatile memory includes allocating a plurality of addresses to a memory area of the nonvolatile memory as addresses to write the last address of arbitrary data, The step of making the address a ring shape and sequentially writing the last address of the arbitrary data to enable continuous writing is performed, and the step of detecting the last address of the data to be read stored in the nonvolatile memory is formed in a ring shape. 2. The flash memory storage method according to claim 1, further comprising the step of detecting the last address stored in the last written address among the plurality of addresses.