JP2002252555A - Output circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an output circuit which has relatively small area and large current driving capability and can reduce ringing noise. SOLUTION: This output circuit comprises P channel transistors(TR) 3, 4, and 5 and N channel TRs 6, 7, and 8; and the gates and drains of the P channel TR 4 and N channel TR 7 are connected and signals are inputted to the P channel TR 5 and N channel TR 8 through a delay circuit 9 and a delay circuit 10 respectively.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an output circuit provided at a portion for outputting a signal in a semiconductor device.
In particular, the present invention relates to an output circuit capable of reducing ringing noise in an output signal.

[0002]

2. Description of the Related Art Conventionally, a CMOS inverter is usually used for an output circuit of a semiconductor device. However, there is a problem that ringing noise occurs when a large load capacitance is connected to the output terminal, when the semiconductor device operates at high speed, and the like. FIG. 7 is a circuit diagram showing a configuration of a conventional output circuit capable of reducing ringing noise described in, for example, Japanese Patent Application Laid-Open No. 5-110402. 7, 101 is a voltage source, 102 is a grounding portion, 103, 104, and 105 are P-channel transistors, 106, 107, and 108 are N-channel transistors, 109 is an input portion, 110 is an output terminal, and 111 is a P-channel transistor 103. Drain, P-channel transistor 104 drain and P-channel transistor 1
Reference numeral 05 denotes a connection portion with the source, and 112 denotes a drain of the N-channel transistor 107 and the N-channel transistor 10.
8 is a connection portion between the drain of the transistor 8 and the source of the N-channel transistor 106. P-channel transistor 103 and P-channel transistor 104, and N-channel transistor 107 and N-channel transistor 10
8 are connected in parallel. The gate and the drain of each of the P-channel transistor 104 and the N-channel transistor 108 are connected. The gate of the P-channel transistor 103 is connected to the ground portion 102 and is always on. The N-channel transistor 107 has a gate connected to the voltage source 101 and is always on. Also, P-channel transistors 104 and 105 and N-channel transistors 106,
Reference numeral 108 is formed to have a large current driving capability for realizing high speed.

Next, the operation will be described. Input unit 109
When the input signal supplied to the transistor changes from the H level to the L level, the P-channel transistor 105 is turned on and the N-channel transistor 106 is turned off. P
When the channel transistor 105 is turned on, the voltage level of the output terminal 110 becomes
Of the P-channel transistor 104
Turns on. The P-channel transistors 104 and 105 are formed so as to have a large current driving capability.
A large current can flow to zero, and the voltage level of the output terminal 110 rises rapidly. This output current is
The current is divided into a P-channel transistor 103 and a P-channel transistor 104 connected in parallel.

The voltage level of the output terminal 110 increases in response to the current flowing from the voltage source 101, and the voltage level of the connection portion 111 changes from the power supply voltage (Vdd) to the threshold voltage (Vth) of the P-channel transistor 104.
When the voltage becomes higher than the voltage (Vdd-Vthp) minus p), the P-channel transistor 104 is turned off. After the P-channel transistor 104 is switched off, the current flows only through the P-channel transistor 103 which is always on, so that the amount of current is limited by the on-resistance of the P-channel transistor 103.

When the input signal applied to input section 109 changes from L level to H level, N channel transistor 106 turns on and P channel transistor 105 turns off. N-channel transistor 1
06 is turned on, the voltage level of the output terminal 110 is applied to the gate of the N-channel transistor 108,
The N-channel transistor 108 turns on. Since N-channel transistors 106 and 108 are formed to have a large current driving capability, a large current can flow from output terminal 110 to ground 102 after a signal change, and the voltage level of output terminal 110 can be rapidly increased. Let go down. This output current is supplied to the P-channel transistor 107 and the P-channel transistor 108 connected in parallel.
And shunted.

When the voltage level at output terminal 110 decreases as current is drawn to grounding section 102, and accordingly the voltage level at connection portion 112 becomes lower than the threshold voltage (Vthn) of N-channel transistor 108,
The N-channel transistor 108 turns off. After the N-channel transistor 108 is turned off, the current flows only through the N-channel transistor 107 which is always on, so that the amount of current is limited by the on-resistance of the N-channel transistor 107.

As described above, after a signal change, a large current can flow through the P-channel transistor 104 or the N-channel transistor 108 having a large current driving capability, so that the voltage level of the output terminal 110 can be quickly changed to a desired level. It can be changed to near the voltage level corresponding to the logical value. When the voltage level of output terminal 110 reaches a voltage level near a desired voltage level, current flows only through P-channel transistor 103 or N-channel transistor 107, so that the respective on-resistances have appropriate values. By forming the transistors 103 and 107 as described above, it is possible to make the change in the amount of current in the vicinity of the end point of the rise or fall of the output signal a desired gradual one, and reduce ringing noise. .

[0008]

Since the conventional output circuit is constructed as described above, the transistor size of the P-channel transistor 103 which is always on (here, it means the channel width of the transistor) In the case where the transistor size of the P-channel transistor 105 is considerably smaller than that of the P-channel transistor 105, the on-resistance of the P-channel transistor 105 becomes considerably larger than the on-resistance of the P-channel transistor 103. P-channel transistor 103 and P-channel transistor 105 when P-channel transistor 105 changes to L level and is turned on
And the connection part 11
1 becomes higher than (Vdd-Vthp), and the P-channel transistor 104 cannot be turned on. That is, the P-channel transistor 103
When the size ratio of the transistor size of the P-channel transistor 105 with respect to the transistor size is smaller than a predetermined value, the voltage difference between the voltage source 101 and the connection portion 111 becomes smaller than the threshold voltage Vthp of the P-channel transistor 104. And P-channel transistor 1
04 cannot be turned on, and the output terminal 110
Cannot be rapidly changed to the vicinity of the voltage level corresponding to the L level. Therefore, P
In order to turn on the channel transistor 104 and obtain a desired operation, the P-channel transistor 1 is set to have a transistor size equal to or larger than a predetermined size ratio based on the transistor size of the P-channel transistor 103.
05 must be formed. In addition, in order to obtain a desired current driving capability, it is necessary to form the P-channel transistor 104 so that the transistor size has a predetermined size ratio or more based on the transistor size of the P-channel transistor 103. Further, since the amount of current flowing after the P-channel transistor 104 is turned off greatly depends on the P-channel transistor 103 having the largest on-resistance, the P-channel transistor 103 needs to have a certain size to obtain a desired amount of current. It must be formed to have a size. From the above, the P-channel transistors 103, 104,
The area occupied by the semiconductor device 105 becomes considerably large.

Further, N-channel transistors 106, 1
Since the same relationship holds true for the transistor sizes of the transistors 07 and 108, the area occupied by the N-channel transistors 106, 107 and 108 on the semiconductor device is considerably large. Therefore, the conventional output circuit has a problem that the occupied area on the semiconductor device is large.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and has as its object to provide an output circuit which has a relatively small area, has a large current driving capability, and can reduce ringing noise.

[0011]

An output circuit according to the present invention is connected between a first P-channel transistor and a first P-channel transistor between a voltage source and an output terminal and in parallel with each other. The second P to be connected
A channel transistor and a third P-channel transistor; first delay means connected to the gate of the third P-channel transistor; and one or more N-channel transistors disposed between the ground and the output terminal. And a gate and a drain are connected in the second P-channel transistor, and an input signal is supplied to the gate of the first P-channel transistor, the first delay means, and the gate of at least one N-channel transistor. It was done.

An output circuit according to the present invention includes one or more P-channel transistors disposed between a voltage source and an output terminal; a first N-channel transistor; A second N-channel transistor and a third N-channel transistor connected in series to one N-channel transistor and connected in parallel to each other; and a second delay means connected to the gate of the third N-channel transistor A gate and a drain are connected in the second N-channel transistor;
An input signal is supplied to the gate of the first N-channel transistor, the second delay means, and the gate of at least one P-channel transistor.

An output circuit according to the present invention includes a first P-channel transistor and a second P-channel transistor connected in series between the voltage source and an output terminal and connected in parallel with each other. A P-channel transistor, a third P-channel transistor, and a third P-channel transistor.
First delay means connected to the gate of the channel transistor, a first N-channel transistor, and a series connection of the first N-channel transistor between the ground and the output terminal, and a connection in parallel with each other. Second
N-channel and third N-channel transistors, and second delay means connected to the gate of the third N-channel transistor. The second P-channel transistor and the second N-channel transistor The drain is connected to the gate of the first P-channel transistor, the gate of the first N-channel transistor, and the input signal is supplied to the first delay means and the second delay means.

An output circuit according to the present invention includes one or more fourth P-channel transistors connected in parallel to a second P-channel transistor and a third P-channel transistor, and one or more fourth P-channel transistors. One or a plurality of third delay units each connected to the gate of the channel transistor and providing a longer delay time than the first delay unit.

An output circuit according to the present invention includes one or more fourth N-channel transistors connected in parallel to a second N-channel transistor and a third N-channel transistor, and one or more fourth N-channel transistors. One or a plurality of fourth delay units each connected to the gate of the channel transistor and providing a longer delay time than the second delay unit.

In the output circuit according to the present invention, the first resistor is arranged between the gate and the drain of the second P-channel transistor.

In the output circuit according to the present invention, the second resistor is arranged between the gate and the drain of the second N-channel transistor.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below. Embodiment 1 FIG. FIG. 1 is a circuit diagram showing a configuration of an output circuit according to Embodiment 1 of the present invention. In FIG. 1, 1
Is a voltage source, 2 is a ground portion, 3 is a P-channel transistor (first P-channel transistor), 4 is a P-channel transistor (second P-channel transistor), and 5 is P
Channel transistor (third P-channel transistor), 6 is N-channel transistor (first N-channel transistor), 7 is N-channel transistor (second N-channel transistor), 8 is N-channel transistor (third N-channel transistor) Transistors, 9 a delay circuit (first delay means), 10 a delay circuit (second delay means), 11 an input section, 12 an output terminal, 13 a drain of the P-channel transistor 4 and a P-channel transistor 5 And 14 is a connection portion between the drain of the N-channel transistor 7, the drain of the N-channel transistor 8, and the source of the N-channel transistor 6. P-channel transistor 4 and P-channel transistor 5, and N-channel transistor 7 and N-channel transistor 8 are respectively connected in parallel. The gate and the drain of each of the P-channel transistor 4 and the N-channel transistor 7 are connected. P
A delay circuit 9 and a delay circuit 10 are connected to the gates of the channel transistor 5 and the N-channel transistor 8, respectively, so that an input signal applied to the input unit 11 is transmitted with a predetermined delay. Also, P
The channel transistors 3, 4 and the N-channel transistors 6, 7 are formed so as to have a large current driving capability in order to realize a high speed operation.

Next, the operation will be described. When the input signal applied to the input unit 11 changes from the H level to the L level, the P-channel transistor 3 turns on and the N-channel transistor 6 turns off. When the P-channel transistor 3 is turned on, the voltage level of the connection part 13 changes to the ground level which is the voltage level of the output terminal 12. Then, the voltage level of the connection portion 13 is a voltage (Vdd-Vthp) obtained by subtracting the threshold voltage (Vthp) of the P-channel transistor 4 from the power supply voltage (Vdd).
If it becomes smaller, the P-channel transistor 4 turns on. After the P-channel transistor 4 is turned on, the L-level signal is delayed by a predetermined time by the delay
When applied to the gate of channel transistor 5, P channel transistor 5 is turned on. Since P-channel transistors 3 and 4 are formed to have a large current driving capability, a large current can flow from voltage source 1 to output terminal 12 after a signal change, and the voltage level of output terminal 12 can be rapidly increased. To raise. The delay time given by the delay circuit 9 is appropriately set so that the P-channel transistor 5 is turned on after the voltage level of the connection portion 13 becomes lower than (Vdd-Vthp).
P-channel transistor 4 can be reliably turned on.

When the voltage level of the output terminal 12 increases in response to the current flowing from the voltage source 1 and the voltage level of the connection portion 13 becomes higher than (Vdd-Vthp), the voltage source 1 and the connection portion 13 And the potential difference between
When the voltage becomes lower than the threshold voltage (Vthp) of the channel transistor 4, the P-channel transistor 4 is turned off. P
After the channel transistor 4 is switched off, the current flows only through the P-channel transistor 5 in the ON state, and the amount of current is limited by the ON resistance of the P-channel transistor 5. Therefore, the P-channel transistor 5 is set so that the on-resistance becomes an appropriate value.
Is formed, it is possible to make a desired gradual change in the amount of current near the end of the rising edge of the output signal, and it is possible to reduce ringing noise.

When the input signal applied to the input section 11 changes from L level to H level, the N-channel transistor 6 is turned on and the P-channel transistor 3 is turned off. When the N-channel transistor 6 is turned on, the voltage level of the connection part 14 changes to the power supply voltage level which is the voltage level of the output terminal 12. Then, when the voltage level of the connection portion 14 becomes higher than the threshold voltage (Vthn) of the N-channel transistor 7, the N-channel transistor 7 is turned on. After the N-channel transistor 7 is turned on, the H-level signal is delayed by a predetermined time by the delay circuit 10 so that the N-channel transistor 8
, The N-channel transistor 8 is turned on. Since N-channel transistors 6 and 7 are formed to have a large current driving capability, a large current can flow from output terminal 12 to ground 2 after a signal change, and the voltage level of output terminal 12 can be rapidly increased. Let go down. By properly setting the delay time given by the delay circuit 10 so that the N-channel transistor 8 is turned on after the voltage level of the connection portion 14 becomes higher than the threshold voltage (Vthn), the N-channel transistor 8 can be reliably connected. Can be turned on.

When the voltage level of the output terminal 12 decreases as the current is drawn to the ground portion 2 and the voltage level of the connection portion 14 correspondingly becomes lower than the threshold voltage (Vthn) of the N-channel transistor 7, N The channel transistor 7 turns off. After the N-channel transistor 7 is switched off, the current flows only through the N-channel transistor 8 in the ON state, and the amount of current is limited by the ON resistance of the N-channel transistor 8. Therefore, by forming the N-channel transistor 8 so that the on-resistance becomes an appropriate value, it becomes possible to make a desired gradual change in the amount of current near the end of the fall of the output signal. Ringing noise can be reduced.

As described above, by passing a large current through the P-channel transistor 4 or the N-channel transistor 7 having a large current driving capability after a signal change,
The voltage level of the output terminal 12 is rapidly changed to the vicinity of a voltage level corresponding to a desired logic value to achieve high speed, and a P-channel transistor having a small current driving capability near the end of the rising or falling edge of the output signal. Ringing noise is reduced by flowing a current only through the 5 or N-channel transistor 8.

FIG. 2 is a circuit diagram showing a configuration of a modification of the output circuit according to the first embodiment of the present invention. 2, the same reference numerals as those in FIG. 1 denote the same or corresponding parts, and a description thereof will not be repeated. Reference numeral 21 denotes a connection portion between the source of the P-channel transistor 4, the source of the P-channel transistor 5, and the drain of the P-channel transistor 3, and 22 denotes the source of the N-channel transistor 7, the source of the N-channel transistor 8, and the drain of the N-channel transistor 6. Is the connection site. This modified example is different from the output circuit shown in FIG.
The point that the order in which the channel transistor 5 and the P-channel transistor 3 are connected in series between the voltage source 1 and the output terminal 12 is reversed, and the N-channel transistor 7
The difference is that the order in which N-channel transistor 8 and N-channel transistor 6 are connected in series between ground unit 2 and output terminal 12 is reversed.

Next, the operation of the output circuit shown in FIG. 2 will be described. When the input signal applied to the input unit 11 changes from the H level to the L level, the P-channel transistor 3 turns on and the N-channel transistor 6 turns off. When the P-channel transistor 3 is turned on, the voltage level of the connection portion 21 changes to the power supply voltage level. At this time, since the voltage level of the output terminal 12 is a voltage level near the ground level,
Is higher than the threshold voltage (Vthp) of P-channel transistor 4, P-channel transistor 4 is turned on. After the P-channel transistor 4 is turned on, when the L-level signal is delayed by a predetermined time by the delay circuit 9 and applied to the gate of the P-channel transistor 5, the P-channel transistor 5 is turned on. Since P-channel transistors 3 and 4 are formed to have a large current driving capability, a large current can flow from voltage source 1 to output terminal 12 after a signal change, and the voltage level of output terminal 12 can be rapidly increased. To raise. The P-channel transistor 4 is reliably turned on by appropriately setting the delay time given by the delay circuit 9 so that the P-channel transistor 5 is turned on after the voltage level of the connection portion 21 becomes higher than (Vthp). Can be done.

The voltage level of the output terminal 12 increases in response to the current flowing from the voltage source 1, and the potential difference between the connection portion 21 and the output terminal 12 accordingly changes the threshold voltage (Vthp) of the P-channel transistor 4. If it becomes smaller, the P-channel transistor 4 turns off. After the P-channel transistor 4 is switched off, the current flows only through the P-channel transistor 5 which is in the on-state. Therefore, the change in the amount of current near the end point of the rising edge of the output signal should be a desired gradual change. And ringing noise can be reduced.

When the input signal applied to the input section 11 changes from L level to H level, the N-channel transistor 6 is turned on and the P-channel transistor 3 is turned off. When the N-channel transistor 6 is turned on, the voltage level of the connection part 22 changes to the ground level. At this time, since the voltage level of the output terminal 12 is a voltage level near the power supply voltage level, the voltage level of the connection portion 22 is a voltage obtained by subtracting the threshold voltage (Vthn) of the N-channel transistor 7 from the power supply voltage (Vdd). (Vdd-Vthn), the N-channel transistor 7 is turned on. After the N-channel transistor 7 is turned on, when the H-level signal is delayed by a predetermined time by the delay circuit 10 and applied to the gate of the N-channel transistor 8, the N-channel transistor 8 is turned on. Since N-channel transistors 6 and 7 are formed to have a large current driving capability, a large current can flow from output terminal 12 to ground 2 after a signal change, and the voltage level of output terminal 12 can be rapidly increased. Let go down. Note that the voltage level of the connection part 22 is (Vdd−Vt).
hn) after being smaller than N-channel transistor 8
The N-channel transistor 8 is set by appropriately setting the delay time given by the delay circuit 10 so that
Can be reliably turned on.

The voltage level of the output terminal 12 decreases as the current is drawn to the ground 2, and accordingly, the potential difference between the connection portion 22 and the output terminal 12 becomes the threshold voltage (Vthn) of the N-channel transistor 7. ), The N-channel transistor 7 is turned off. After the N-channel transistor 7 is switched off, the current flows only through the N-channel transistor 8 which is in the ON state, so that the change in the amount of current near the end of the fall of the output signal is set to a desired gradual one. This makes it possible to reduce ringing noise.

As described above, also in the modification of the output circuit according to the first embodiment shown in FIG. 2, a large current flows through P-channel transistor 4 or N-channel transistor 7 having a large current driving capability after a signal change. By flowing the output signal, the voltage level of the output terminal 12 is rapidly changed to near the voltage level corresponding to the desired logical value to achieve high speed, and the current driving capability is reduced near the end of the rising or falling edge of the output signal. Small P-channel transistor 5 or N-channel transistor 8
The ringing noise is reduced by flowing the current only through the ring.

As described above, according to the first embodiment, the P-channel transistor 4 having a large current driving capability and the P-channel transistor 5 having a small current driving capability are connected in parallel, and the N-channel transistor having a large current driving capability is connected. By connecting the transistor 7 and the N-channel transistor 8 having a small current driving capability in parallel, it is possible to realize a high-speed circuit operation and to reduce the ringing noise, and to provide an input signal to the P-channel transistor 5 via the delay circuit 9, Further, since the input signal is provided to the N-channel transistor 8 via the delay circuit 10, the P-channel transistor 4 and the N-channel transistor 7 can be reliably turned on when the signal changes.
The transistor size of the P-channel transistor 3 can be set arbitrarily without being restricted by the size ratio based on the P-channel transistor 5, and without being restricted by the size ratio based on the N-channel transistor 8. It is possible to arbitrarily set the transistor size of the N-channel transistor 6, and it is possible to reduce the area occupied by the output circuit on the semiconductor device.

In the first embodiment, the voltage source 1
And three output terminals 12, and three P-channel transistors 3, 4, and 5, and between the grounding part 2 and the output terminal 12 include three N-channel transistors 6, 7, and 8 as an example. For example, three P-channel transistors 3, 4 and 5 are provided between the voltage source 1 and the output terminal 12, and an N-channel transistor 6 is provided between the ground part 2 and the output terminal 12. A P-channel transistor 3 is provided between the voltage source 1 and the output terminal 12, and a P-channel transistor 3 is provided between the ground 2 and the output terminal 12.
A configuration including two N-channel transistors 6, 7, 8 may be employed. In the former case, the transistor size of the P-channel transistor 3 can be set without being restricted by the size ratio based on the P-channel transistor 5, and the area occupied by the output circuit on the semiconductor device can be reduced. It works. In the latter case, it is possible to set the transistor size of the N-channel transistor 6 without being restricted by the size ratio based on the N-channel transistor 8, thereby reducing the area occupied by the output circuit on the semiconductor device. It has the effect of being able to.

Embodiment 2 FIG. 3 is a circuit diagram showing a configuration of an output circuit according to Embodiment 2 of the present invention. FIG.
1, the same reference numerals as those in FIG. 1 denote the same or corresponding parts, and a description thereof will not be repeated. 31 is a P-channel transistor (fourth P-channel transistor) connected in parallel to the P-channel transistor 4 and the P-channel transistor 5, 32 is a delay circuit, 33 is the drain of the P-channel transistor 4 and the drain of the P-channel transistor 5. A connection portion between the drain of the P-channel transistor 31 and the source of the P-channel transistor 3, 34 is an N-channel transistor (a fourth N-channel transistor) connected in parallel to the N-channel transistor 7 and the N-channel transistor 8, and 35 is a delay A circuit 36 is a connection portion between the drain of the N-channel transistor 7, the drain of the N-channel transistor 8, the drain of the N-channel transistor 34, and the source of the N-channel transistor 6. By connecting the delay circuit 9 and the delay circuit 32, a delay means (third delay means) for delaying the input signal by the sum of the delay time of the delay circuit 9 and the delay time of the delay circuit 32 is provided. Be composed. By connecting the delay circuit 10 and the delay circuit 35, a delay means (fourth delay means) for delaying the input signal by the sum of the delay time of the delay circuit 10 and the delay time of the delay circuit 35 is provided. Be composed. The gate of P-channel transistor 31 is connected to delay circuit 32, so that an input signal applied to input section 11 for a time obtained by adding the delay time of delay circuit 9 and the delay time of delay circuit 32 is added. It is transmitted with a delay. The gate of the N-channel transistor 34 is connected to the delay circuit 35, so that the input unit 11 has a time corresponding to the sum of the delay time of the delay circuit 10 and the delay time of the delay circuit 35.
Is transmitted with a delay.

Next, the operation will be described. Note that the basic operation is the same as the operation of the output circuit according to the first embodiment shown in FIG. 1, and therefore, here, there is a difference as compared with the operation of the output circuit shown in FIG. An operation specific to the output circuit according to the second embodiment will be mainly described.
When the input signal applied to the input unit 11 changes from the H level to the L level, the P-channel transistor 3 is turned on, and the voltage level of the connection part 33 becomes (Vdd-Vth).
If it becomes smaller than p), the P-channel transistor 4 turns on. After the P-channel transistor 4 is turned on, L
When the level signal is delayed by the delay time generated by delay circuit 9 and applied to the gate of P-channel transistor 5, P-channel transistor 5 is turned on. Furthermore, L
The level signal is delayed by the delay circuit 9 and the delay circuit 3
When the signal is applied to the gate of P-channel transistor 31 after being delayed by the sum of the delay time of P-channel transistor 31, P-channel transistor 31 is turned on. As described above, after the P-channel transistor 5 is turned on, the amount of current decreases to some extent, and then the P-channel transistor 31 is sequentially turned on to increase the current driving capability. Can be made more gradual. Therefore, when compared with the output circuit according to the first embodiment in which the P-channel transistor 5 is provided as a current driving means that becomes active in a steady state in which the input signal does not change, the change in the amount of current near the end of the rise of the output signal The P-channel transistor 5 and P
It is possible to give a larger current driving capability to the current driving means which is active in the steady state including the channel transistor 31. That is, the current characteristic in the steady state (hereinafter, referred to as DC current characteristic) is determined by P-channel transistor 3, P-channel transistor 5, and P-channel transistor 31 when outputting an H-level signal. DC current characteristics can be improved.

When the input signal applied to the input section 11 changes from L level to H level, the N-channel transistor 6 is turned on, and the voltage level at the connection portion 36 is changed to the threshold voltage of the N-channel transistor 7 ( Vthn), the N-channel transistor 7 turns on.
After the N-channel transistor 7 is turned on, if the H-level signal is applied to the gate of the N-channel transistor 8 with a delay of the delay time generated by the delay circuit 10,
The channel transistor 8 turns on. Further, when the H-level signal is applied to the gate of N-channel transistor 34 after being delayed by the sum of the delay time of delay circuit 10 and the delay time of delay circuit 35, N-channel transistor 34 is turned on. As described above, after the amount of current is reduced to some extent after the N-channel transistor 8 is turned on, the N-channel transistor 34 is sequentially turned on to increase the current driving capability, so that the current near the end of the fall of the output signal is reduced. The change in volume can be made more gradual. Therefore, when compared with the output circuit according to the first embodiment in which the N-channel transistor 8 is provided as a current driving means that is active in a steady state, the change in the current amount near the end point of the fall of the output signal is not required. Within the range that satisfies the required performance,
N-channel transistor 8 and N-channel transistor 3
4, it is possible to give a larger current driving capability to the current driving means that is active in the steady state. That is, the DC current characteristics are such that when outputting an L-level signal, the N-channel transistor 6, the N-channel transistor 8, and the N-channel transistor 34
Therefore, the DC current characteristics can be improved.

FIG. 4 is a circuit diagram showing a configuration of a modification of the output circuit according to the second embodiment of the present invention. 4, the same reference numerals as those in FIG. 3 denote the same or corresponding parts, and a description thereof will not be repeated. Reference numeral 41 denotes a connection portion between the source of the P-channel transistor 4, the source of the P-channel transistor 5, the source of the P-channel transistor 31, and the drain of the P-channel transistor 3, and the reference numeral 42 denotes the source of the N-channel transistor 7 and the source of the N-channel transistor 8. This is a connection portion between the source of the N-channel transistor 34 and the drain of the N-channel transistor 6. This modification is different from the output circuit shown in FIG. 3 in that P-channel transistor 4, P-channel transistor 5, P-channel transistor 31 and P-channel transistor 3 are connected in series between voltage source 1 and output terminal 12. The connection order is reversed, and the order in which N-channel transistor 7, N-channel transistor 8, and N-channel transistor 34 and N-channel transistor 6 are connected in series between ground 2 and output terminal 12 is reversed. Differs in that

The operation of the output circuit differs from the output circuit shown in FIG. 3 in the timing at which the P-channel transistor 4 and the N-channel transistor 7 are turned on or off. One operation is described in the first embodiment shown in FIG.
Has already been described in the description of the modified example of the output circuit, and the description is omitted here.

As described above, according to the second embodiment, the same effects as those of the first embodiment can be obtained, and P-channel transistor 4 and P-channel transistor 5
A P-channel transistor 31 connected in parallel to
A delay circuit 32 connected to the gate of the channel transistor 31, an N-channel transistor 34 connected in parallel to the N-channel transistor 7 and the N-channel transistor 8, and a delay circuit 35 connected to the gate of the N-channel transistor 34 Because it was configured to prepare
In the vicinity of the end of the rise or fall of the output signal, after the P-channel transistor 5 is turned on and the amount of current decreases to some extent, the P-channel transistor 3
1 or the N-channel transistor 34 can be turned on after the current amount has decreased to some extent after the N-channel transistor 8 has been turned on, and the change in the current amount near the end point can be made more gradual. Since it becomes possible, the current driving means that is active in the steady state within a range that satisfies the performance required for the change in the current amount near the end of the rising or falling of the output signal has a larger current driving capability. This makes it possible to improve the DC current characteristics of the output circuit.

In the second embodiment, the voltage source 1
And four output terminals 12, and four P-channel transistors 3, 4, 5, and 31, and between ground unit 2 and output terminal 12 four N-channel transistors 6, 7, 8, and 34. Is disclosed as an example, but four P-channel transistors 3, 4, 5, and 5 are connected between the voltage source 1 and the output terminal 12, for example.
31 and an N-channel transistor 6 between the ground unit 2 and the output terminal 12, or a P-channel transistor 3 between the voltage source 1 and the output terminal 12 and the ground unit 2 and the output terminal 12
Between the four N-channel transistors 6, 7,
It is also possible to adopt a configuration including 8, 34 or the like. Further, as current driving means connected in series to the P-channel transistor 3 or the N-channel transistor 6 and active in a steady state, the P-channel transistor 5 and the P-channel transistor 31 or the N-channel transistor 8 and the N-channel transistor 34
However, it is also possible to provide a configuration in which three or more P-channel transistors or three or more N-channel transistors are provided, and these three or more transistors are sequentially turned on. With this configuration, the change in the amount of current near the end of the rising or falling of the output signal can be made more gradual, and the DC current characteristics can be improved.

Embodiment 3 FIG. 5 is a circuit diagram showing a configuration of an output circuit according to Embodiment 3 of the present invention. FIG.
3, the same reference numerals as those in FIG. 3 denote the same or corresponding parts, and a description thereof will not be repeated. Reference numeral 51 denotes a resistor (first transistor) disposed between the gate and the drain of the P-channel transistor 4.
, 52 are resistors (second resistors) arranged between the gate and the drain of the N-channel transistor 7.

Next, the operation will be described. Note that the basic operation is the same as the operation of the output circuit according to the second embodiment shown in FIG. 3, and thus the description will focus on the operation relating to the resistors 51 and 52. Output terminal 1
2 has a positive potential ESD (ElectroStatic).
In this case, the ESD is converted to heat before being applied to the gate of the P-channel transistor 4 or the ESD is converted to the P-channel transistors 4 and 5 because the resistor 51 is inserted. 31 to the power supply line. Thereby, C
It is possible to improve the resistance of a DM (Charged Device Model) to ESD.

When a negative potential ESD acts on the output terminal 12, the resistor 52 is inserted,
Either the ESD is converted to heat before being applied to the gate of N-channel transistor 7, or the ESD escapes from the drain side of N-channel transistors 7, 8, 34 to the ground line. Thereby, the resistance of the CDM to ESD can be improved.

FIG. 6 is a circuit diagram showing a configuration of a modification of the output circuit according to the third embodiment of the present invention. 6, the same reference numerals as those in FIG. 5 denote the same or corresponding parts, and a description thereof will not be repeated. This modification is different from the output circuit shown in FIG. 5 in that the P-channel transistor 4, the P-channel transistor 5, and the P-channel transistor 31
, P-channel transistor 3 and voltage source 1 and output terminal 1
2 and the N-channel transistor 7, the N-channel transistor 8, and the N-channel transistor 34 and the N-channel transistor 6 are connected in series between the ground 2 and the output terminal 12. The difference is that the order performed is reversed. In addition,
The operation is the same as that of the output circuit shown in FIG. 5, and a description thereof will be omitted.

As described above, according to the third embodiment, the same effects as those of the second embodiment can be obtained, the resistor 51 is arranged between the gate and the drain of the P-channel transistor 4, and the N-channel Since the resistor 52 is arranged between the gate and the drain of the transistor 7, an effect that the resistance of the CDM to ESD can be improved.

In the third embodiment, the resistor 51 disposed between the gate and the drain of the P-channel transistor 4 and the resistor 52 disposed between the gate and the drain of the N-channel transistor 7 The invention is disclosed by taking as an example the configuration including: a configuration including only the resistor 51 disposed between the gate and the drain of the P-channel transistor 4; A configuration including only the disposed resistor 52 can be adopted. In the former case, there is an effect that the resistance of the positive potential CDM to ESD can be improved. In the latter case, there is an effect that the resistance of the negative potential CDM to ESD can be improved.

[0045]

As described above, according to the present invention, the first
A second P-channel transistor and a third P-channel transistor connected in series with the first P-channel transistor between the voltage source and the output terminal and connected in parallel with each other;
One or more Ns disposed between the ground and the output terminal
Since the second P-channel transistor has a gate and a drain connected to each other, the second P-channel transistor has a large current driving capability when the input signal changes from the H level to the L level. A third P-channel transistor formed to flow a large current through the second P-channel transistor to realize a high-speed circuit operation and to have a small current driving capability near the end of the rising edge of the output signal , The ringing noise is reduced by flowing current only through the first P-channel transistor and the first delay means connected to the gate of the third P-channel transistor is provided. Signal, the second P-channel transistor is reliably turned off when the signal changes. Since it is possible to, the third P
There is an effect that the transistor size of the first P-channel transistor can be set arbitrarily without being limited by the size ratio based on the channel transistor, and the area occupied by the output circuit on the semiconductor device can be reduced.

According to the present invention, one or more P-channel transistors disposed between the voltage source and the output terminal, the first N-channel transistor, and the first terminal connected between the ground and the output terminal. A second N-channel transistor connected in series with the N-channel transistor and connected in parallel with each other;
A channel transistor and a third N-channel transistor are provided, and the second N-channel transistor is configured such that the gate and the drain are connected. Therefore, when the input signal changes from the L level to the H level, a large current is applied. A large current is made to flow through a second N-channel transistor formed to have a driving capability to realize a high-speed circuit operation, and to have a small current driving capability near the end of the fall of the output signal. A current flows only through the formed third N-channel transistor to reduce ringing noise,
Since the second delay means connected to the gate of the channel transistor is provided, the signal is input to the third N-channel transistor with a delay. Since the transistor can be reliably turned on, the transistor size of the first N-channel transistor can be set arbitrarily without being restricted by the size ratio based on the third N-channel transistor, and the output circuit of the semiconductor device There is an effect that the occupied area can be reduced.

According to the present invention, the first P-channel transistor and the first P-channel transistor are provided between the voltage source and the output terminal.
A second P-channel transistor, a third P-channel transistor, a first N-channel transistor, and a first P-channel transistor connected in series to the channel transistor and connected in parallel with each other;
A second N-channel transistor and a third N-channel transistor connected in series with each other and connected in parallel with each other, and the second P-channel transistor and the second N-channel transistor have a gate and Since the configuration is such that the drain is connected, the speeding up of the circuit operation and the reduction of the ringing noise are realized, and the first delay means and the third N connected to the gate of the third P-channel transistor are realized. And the second delay means connected to the gate of the channel transistor, so that the transistor size of the first P-channel transistor can be reduced without being restricted by the size ratio based on the third P-channel transistor. Can be set arbitrarily, and size based on the third N-channel transistor To be able to arbitrarily set the transistor size of the first N-channel transistor without being constrained to an effect that it is possible to reduce the area occupied by the output circuit in the semiconductor device.

According to the present invention, one or more fourth P-channel transistors connected in parallel to the second P-channel transistor and the third P-channel transistor, and one or more fourth P-channel transistors And one or a plurality of third delay means connected to the gates of the first and second delay circuits, respectively, to provide a longer delay time than the first delay means. In the vicinity of the end point of the rising edge of the output signal, after the third P-channel transistor is turned on and the amount of current is reduced to some extent, one or more fourth
Can be sequentially turned on, and the change in the amount of current near the end point can be made more gradual. Therefore, the performance required for the change in the amount of current near the end point can be reduced. Within the range that satisfies, it is possible to provide a larger current driving capability to the current driving unit that is active in a steady state including the third P-channel transistor and one or a plurality of fourth P-channel transistors. This has the effect of improving the DC current characteristics of the circuit.

According to the present invention, one or more fourth N-channel transistors connected in parallel to the second N-channel transistor and the third N-channel transistor, and one or more fourth N-channel transistors And one or a plurality of fourth delay units connected to the gates of the first and second gates, respectively, to provide a longer delay time than the second delay unit. In the vicinity of the end of the fall of the output signal, after the third N-channel transistor is turned on and the amount of current decreases to some extent,
Can be sequentially turned on, and the change in the amount of current near the end point can be made more gradual. Therefore, the performance required for the change in the amount of current near the end point can be reduced. Within the range that satisfies, it is possible to provide a larger current driving capability to the current driving unit that is active in a steady state including the third N-channel transistor and one or a plurality of fourth N-channel transistors. This has the effect of improving the DC current characteristics of the circuit.

According to the present invention, since the first resistor is arranged between the gate and the drain of the second P-channel transistor, the ESD of the positive potential CDM is performed.
This has the effect of improving the resistance to odor.

According to the present invention, since the second resistor is arranged between the gate and the drain of the second N-channel transistor, the ESD of the negative potential CDM is performed.
This has the effect of improving the resistance to odor.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of an output circuit according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a configuration of a modification of the output circuit according to the first embodiment of the present invention.

FIG. 3 is a circuit diagram showing a configuration of an output circuit according to a second embodiment of the present invention.

FIG. 4 is a circuit diagram showing a configuration of a modification of the output circuit according to the second embodiment of the present invention;

FIG. 5 is a circuit diagram showing a configuration of an output circuit according to a third embodiment of the present invention.

FIG. 6 is a circuit diagram showing a configuration of a modification of the output circuit according to the third embodiment of the present invention.

FIG. 7 is a circuit diagram showing a configuration of a conventional output circuit.

[Explanation of symbols]

1 voltage source, 2 ground, 3 P-channel transistor (first P-channel transistor), 4 P-channel transistor (second P-channel transistor), 5 P
Channel transistor (third P-channel transistor), 6 N-channel transistor (first N-channel transistor), 7 N-channel transistor (second N-channel transistor), 8 N-channel transistor (third N-channel transistor), 9 delay circuit (first delay means), 10 delay circuit (second delay means), 11 input section, 12 output terminal, 13, 14, 2
1, 22, 33, 36, 41, 42 connection site, 31
P-channel transistor (fourth P-channel transistor), 32 delay circuit, 34 N-channel transistor (fourth N-channel transistor), 35 delay circuit,
51 resistance (first resistance), 52 resistance (second resistance).

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5F038 BH07 BH19 CD09 DF01 EZ20 5J055 AX07 AX25 AX55 AX64 BX16 CX24 DX12 DX56 DX72 DX73 DX83 EX07 EX21 EY21 EZ07 EZ50 FX12 FX17 FX35 GX01 5J056 AA04 BB12 EE12 EE12 FF08 GG03

Claims (7)

[Claims] 1. A first P-channel transistor, a second P-channel transistor connected in series with the first P-channel transistor between a voltage source and an output terminal, and a second P-channel transistor and a second P-channel transistor connected in parallel with each other. 3 P-channel transistors, first delay means connected to the gate of the third P-channel transistor, and one or more N-channel transistors disposed between a ground and the output terminal. In the second P-channel transistor, a gate and a drain are connected, and an input signal is supplied to a gate of the first P-channel transistor, the first delay unit, and a gate of at least one of the N-channel transistors. An output circuit, characterized by: 2. A power supply circuit according to claim 1, wherein said first terminal is arranged between a voltage source and an output terminal.
Alternatively, a plurality of P-channel transistors, a first N-channel transistor, and a second N-channel transistor connected in series to the first N-channel transistor and connected in parallel with each other between a ground and the output terminal. A channel transistor and a third N-channel transistor;
A second delay unit connected to a gate of the third N-channel transistor, wherein a gate and a drain are connected to each other in the second N-channel transistor, and a gate of the first N-channel transistor; 2. An output circuit, wherein an input signal is provided to two delay means and a gate of at least one of the P-channel transistors. 3. A first P-channel transistor, a second P-channel transistor connected in series with the first P-channel transistor between a voltage source and an output terminal, and a second P-channel transistor and a second P-channel transistor connected in parallel with each other. A third P-channel transistor, first delay means connected to the gate of the third P-channel transistor, and a first N-channel transistor.
A channel transistor; a second N-channel transistor and a third N-channel transistor connected in series to the first N-channel transistor and connected in parallel with each other between a ground and the output terminal; A second delay means connected to the gate of a third N-channel transistor, wherein the second P-channel transistor and the second N
In the channel transistor, a gate and a drain are connected, and an input signal is supplied to the gate of the first P-channel transistor, the gate of the first N-channel transistor, the first delay unit, and the second delay unit. An output circuit, characterized by: 4. One or more fourth P-channel transistors connected in parallel to the second P-channel transistor and the third P-channel transistor, and a gate of the one or more fourth P-channel transistors. 4. The output circuit according to claim 1, further comprising one or a plurality of third delay units connected to each other to provide a longer delay time than the first delay unit. 5. One or more fourth N-channel transistors connected in parallel to the second N-channel transistor and the third N-channel transistor, and a gate of the one or more fourth N-channel transistors. 4. The output circuit according to claim 2, further comprising one or a plurality of fourth delay means connected to each other to provide a longer delay time than the second delay means. 6. The output circuit according to claim 1, wherein a first resistor is arranged between a gate and a drain of the second P-channel transistor. 7. The output circuit according to claim 2, wherein a second resistor is arranged between a gate and a drain of the second N-channel transistor.