JP2002252237A - Method and apparatus for manufacturing semiconductor device - Google Patents

Method and apparatus for manufacturing semiconductor device

Info

Publication number
JP2002252237A
JP2002252237A JP2001047866A JP2001047866A JP2002252237A JP 2002252237 A JP2002252237 A JP 2002252237A JP 2001047866 A JP2001047866 A JP 2001047866A JP 2001047866 A JP2001047866 A JP 2001047866A JP 2002252237 A JP2002252237 A JP 2002252237A
Authority
JP
Japan
Prior art keywords
electrode
semiconductor
sealing body
wiring
individual
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2001047866A
Other languages
Japanese (ja)
Inventor
Kenji Furumoto
建二 古本
Satoyuki Takashita
智行 高下
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP2001047866A priority Critical patent/JP2002252237A/en
Publication of JP2002252237A publication Critical patent/JP2002252237A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • H01L24/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

PROBLEM TO BE SOLVED: To improve loading accuracy of a ball electrode. SOLUTION: A sealing body is divide into individual sealing bodies in the unit of each semiconductor element, before a solder ball is loaded to an external electrode of the sealing body which is sealed by loading a plurality of semiconductor elements on a wiring board, an amount of warpage of the sealing body which is generated at the time of sealing is divided to each individual sealing body. For this reason, the ball electrode can be loaded in a condition in which flatness of the external electrode on a back surface of the sealing body is kept good, and the high loading accuracy of the ball electrode can be realized.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、半導体素子の封止
体の外部電極または半導体素子の電極にボール電極を搭
載する半導体装置の製造方法および製造装置に関するも
のであり、特に複数のボール電極を同時に配線基板の外
部電極に搭載する半導体装置の製造方法および製造装置
に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method and an apparatus for manufacturing a semiconductor device in which a ball electrode is mounted on an external electrode of a sealing body of a semiconductor element or an electrode of the semiconductor element. The present invention also relates to a method and an apparatus for manufacturing a semiconductor device mounted on external electrodes of a wiring board.

【0002】[0002]

【従来の技術】近年、電子機器の小型化および実装信頼
性の向上が要求され、それにともなって、半導体装置と
配線基板との電気的な接続方法についても種々提案され
ている。
2. Description of the Related Art In recent years, there has been a demand for miniaturization of electronic equipment and improvement in mounting reliability, and accordingly, various methods for electrically connecting a semiconductor device to a wiring board have been proposed.

【0003】以下、従来の半導体装置の製造方法につい
て説明する。
Hereinafter, a conventional method for manufacturing a semiconductor device will be described.

【0004】図7は、従来の半導体装置の製造工程のフ
ロー図である。
FIG. 7 is a flow chart of a conventional semiconductor device manufacturing process.

【0005】図7に示すように、まず、半導体素子の裏
面を配線基板の表面に接着剤を用いて接着する(ダイボ
ンディング工程)。
As shown in FIG. 7, first, the back surface of a semiconductor element is bonded to the front surface of a wiring board using an adhesive (die bonding step).

【0006】次に、半導体素子の電極と配線基板の表面
に形成された電極部とを金属細線で電気的に接続する
(金属細線接続工程)。
Next, an electrode of the semiconductor element and an electrode portion formed on the surface of the wiring board are electrically connected by a thin metal wire (a thin metal wire connecting step).

【0007】次に、複数の半導体素子が搭載された配線
基板の表面において複数の半導体素子を封止樹脂によっ
て封止する(封止工程)。
Next, the plurality of semiconductor elements are sealed with a sealing resin on the surface of the wiring board on which the plurality of semiconductor elements are mounted (sealing step).

【0008】その後、配線基板の表面の電極部と配線基
板内部のスルーホールによって電気的に接続された配線
基板の裏面の外部電極に対して、ボール電極を搭載する
(ボール電極搭載工程)。
Thereafter, a ball electrode is mounted on the external electrode on the back surface of the wiring board electrically connected to the electrode portion on the front surface of the wiring board by a through hole inside the wiring board (ball electrode mounting step).

【0009】このボール電極が搭載された状態の配線基
板を一定温度以上の雰囲気中を通過させてボール電極を
溶融させた後、室温中でハンダを固化させる(リフロ工
程)。
After the wiring board on which the ball electrodes are mounted is passed through an atmosphere at a certain temperature or higher to melt the ball electrodes, the solder is solidified at room temperature (reflow process).

【0010】そして、半導体素子ごとの配線基板の境界
部をブレードを用いて切断し、個別の封止体に分割する
(封止体分割工程)。
[0010] Then, a boundary portion of the wiring board for each semiconductor element is cut using a blade and divided into individual sealing bodies (sealing body dividing step).

【0011】[0011]

【発明が解決しようとする課題】しかしながら、従来の
半導体装置の製造方法は、半導体素子の封止体を個別封
止体に切断する前に、配線基板の裏面の外部電極に複数
のボール電極を同時に搭載していたので、以下の点が課
題となっていた。
However, in the conventional method of manufacturing a semiconductor device, a plurality of ball electrodes are formed on the external electrodes on the back surface of the wiring board before the sealing body of the semiconductor element is cut into individual sealing bodies. At the same time, it had the following issues.

【0012】図8は、従来のボール電極搭載工程を示す
断面図である。
FIG. 8 is a sectional view showing a conventional ball electrode mounting process.

【0013】図8に示すように、複数の半導体素子1が
搭載された配線基板2の外部電極3に、ボール電極4が
搭載される。半導体素子1の電極と配線基板2の表面に
形成された電極部(図示せず)とは金属細線5によって
電気的に接続され、また、配線基板2の表面の電極部と
配線基板2の裏面の外部電極3とは、配線基板2の内部
に形成されたスルーホールによって電気的に接続されて
いる。
As shown in FIG. 8, a ball electrode 4 is mounted on an external electrode 3 of a wiring board 2 on which a plurality of semiconductor elements 1 are mounted. The electrodes of the semiconductor element 1 are electrically connected to electrode portions (not shown) formed on the surface of the wiring board 2 by thin metal wires 5. Are electrically connected to the external electrodes 3 by through holes formed inside the wiring board 2.

【0014】一方、ボール電極4はボール電極搭載ヘッ
ド6の吸着穴7において吸着されている。
On the other hand, the ball electrode 4 is sucked in the suction hole 7 of the ball electrode mounting head 6.

【0015】以上のような配線基板2とボール電極搭載
ヘッド6との位置関係において、配線基板2の複数の外
部電極3に対して、複数のボール電極4が同時に搭載さ
れるが、配線基板2は封止工程で加熱されたために、内
部応力により反りが発生している。ところが、複数のボ
ール電極が吸着されたボール電極搭載ヘッド6の吸着穴
の位置は、封止工程で加熱の影響を受ける前の平坦な配
線基板2の外部電極3の位置に合わせて設計されてい
る。したがって、配線基板2の外部電極3の位置とボー
ル電極搭載ヘッド6の吸着穴7に吸着されたボール電極
4の位置はずれてしまい、全てのボール電極4が配線基
板2の外部電極3に精度よく搭載できず、なかには外部
電極3からはみ出してしまうボール電極4が発生する。
In the above positional relationship between the wiring board 2 and the ball electrode mounting head 6, a plurality of ball electrodes 4 are simultaneously mounted on the plurality of external electrodes 3 of the wiring board 2. Since is heated in the sealing step, warpage occurs due to internal stress. However, the positions of the suction holes of the ball electrode mounting head 6 where the plurality of ball electrodes are sucked are designed in accordance with the positions of the external electrodes 3 of the flat wiring board 2 before being affected by heating in the sealing step. I have. Therefore, the positions of the external electrodes 3 on the wiring board 2 and the positions of the ball electrodes 4 sucked in the suction holes 7 of the ball electrode mounting head 6 deviate, and all the ball electrodes 4 are accurately positioned on the external electrodes 3 of the wiring board 2. A ball electrode 4 which cannot be mounted and protrudes from the external electrode 3 is generated.

【0016】次に、配線基板の外部電極に対するボール
電極搭載精度について説明する。
Next, the accuracy of mounting the ball electrodes on the external electrodes of the wiring board will be described.

【0017】図9は、配線基板が反っている状態で、1
つのボール電極を配線基板の外部電極に搭載する場合、
ボール電極の外部電極に対するズレ量を示す図である。
FIG. 9 shows a state in which the wiring board is warped.
When mounting two ball electrodes on the external electrodes of the wiring board,
FIG. 4 is a diagram illustrating a deviation amount of a ball electrode from an external electrode.

【0018】図9に示すように、配線基板2が反ること
によって、外部電極3が本来の位置から距離d降下する
と、外部電極3の中心とボール電極4の中心とのズレ8
が発生する。このズレ8、ボール電極4および外部電極
3のサイズの関係によっては、ボール電極4が外部電極
3からはみ出して搭載されてしまう。
As shown in FIG. 9, when the wiring substrate 2 warps and the external electrode 3 falls a distance d from its original position, a deviation 8 between the center of the external electrode 3 and the center of the ball electrode 4 is obtained.
Occurs. Depending on the relationship between the deviation 8, the size of the ball electrode 4 and the size of the external electrode 3, the ball electrode 4 protrudes from the external electrode 3 and is mounted.

【0019】また、近年の半導体ウェハーの大口径化に
伴って、封止樹脂によって封止する前にすでに、半導体
ウェハーが反っている場合があるので、封止工程前に半
導体ウェハーの電極および半導体ウェハーの電極に接続
した外部電極に、各々同時にボール電極を搭載する場合
にも、同様にボール電極の高精度な搭載が困難になる。
Further, with the recent increase in the diameter of the semiconductor wafer, the semiconductor wafer may be warped before being sealed with a sealing resin. Similarly, when ball electrodes are simultaneously mounted on the external electrodes connected to the electrodes of the wafer, it is difficult to mount the ball electrodes with high accuracy.

【0020】一方、配線基板2の反りを吸収する方法と
して、ボール電極搭載ヘッド6によって配線基板2を加
圧して配線基板2の反りを矯正する方法も考えられる
が、配線基板2を加圧するため、配線基板2に形成され
ている配線の断線およびクラック等の不具合が発生す
る。
On the other hand, as a method of absorbing the warpage of the wiring board 2, a method of correcting the warpage of the wiring board 2 by applying pressure to the wiring board 2 by the ball electrode mounting head 6 can be considered. In addition, problems such as disconnection and cracking of the wiring formed on the wiring board 2 occur.

【0021】さらに、半導体素子または配線基板に不良
品が存在していても、その不良品に相当する配線基板の
裏面電極部に対してボール電極を一括搭載するため、不
必要なボール電極を消費してしまう。
Furthermore, even if a defective product is present in the semiconductor element or the wiring board, unnecessary ball electrodes are consumed because the ball electrodes are collectively mounted on the back surface electrode portion of the wiring substrate corresponding to the defective product. Resulting in.

【0022】本発明は前記従来の課題を解決するもので
あり、ボール電極の搭載精度を向上させるための半導体
装置の製造方法および製造装置を提供することを目的と
する。
An object of the present invention is to solve the above-mentioned conventional problems, and an object of the present invention is to provide a method and an apparatus for manufacturing a semiconductor device for improving the mounting accuracy of a ball electrode.

【0023】[0023]

【課題を解決するための手段】前記従来の課題を解決す
るために、本発明の半導体装置の製造方法は、少なくと
も上面に配線電極と底面に前記配線電極と電気的に接続
した外部電極を有した配線基板の上面に複数の半導体素
子が搭載され、その上面に実質的全面が封止樹脂で封止
された封止体に対して、各半導体素子単位に前記配線基
板を切断して個別封止体を得る工程と、前記個別封止体
の裏面の外部電極側を上にして複数個配列する工程と、
前記配列された複数の個別封止体の裏面の外部電極上に
各々同時にボール電極を搭載する工程とよりなる。
In order to solve the above-mentioned conventional problems, a method of manufacturing a semiconductor device according to the present invention comprises a wiring electrode on at least an upper surface and an external electrode electrically connected to the wiring electrode on a bottom surface. A plurality of semiconductor elements are mounted on the upper surface of the wiring substrate thus formed, and the wiring substrate is cut into individual semiconductor elements and individually sealed with respect to a sealing body in which substantially the entire surface is sealed with a sealing resin. A step of obtaining a stationary body, and a step of arranging a plurality of pieces with the external electrode side of the back surface of the individual sealing body facing upward,
And a step of simultaneously mounting ball electrodes on the external electrodes on the back surfaces of the plurality of individual sealing bodies arranged.

【0024】このように、半導体素子の封止体を個別封
止体に分割した後に、複数のハンダボールを個別封止体
の裏面の外部電極に各々同時にボール電極を搭載するこ
とにより、封止体の反りの影響を受けることなく平坦性
の高い状態で配線基板の外部電極にボール電極を搭載す
ることができるので、外部電極にボール電極を高精度に
搭載することができる。
As described above, after dividing the sealing body of the semiconductor element into individual sealing bodies, a plurality of solder balls are simultaneously mounted on the external electrodes on the back surface of the individual sealing body, respectively, whereby the sealing is performed. Since the ball electrode can be mounted on the external electrode of the wiring board in a state of high flatness without being affected by the warpage of the body, the ball electrode can be mounted on the external electrode with high accuracy.

【0025】また、少なくとも上面に配線電極と底面に
前記配線電極と電気的に接続した外部電極を有した配線
基板の上面に複数の半導体素子が搭載され、その上面に
実質的全面が封止樹脂で封止された封止体に対して、各
半導体素子単位に前記配線基板を切断して個別封止体を
得る工程において、前記封止体は上方または下方に反っ
ている封止体であり、個別封止体に切断することにより
その反りを減少させる。
A plurality of semiconductor elements are mounted on an upper surface of a wiring substrate having at least a wiring electrode on an upper surface and external electrodes electrically connected to the wiring electrode on a lower surface, and a substantially entire surface of the upper surface is formed of a sealing resin. In the step of cutting the wiring substrate for each semiconductor element unit to obtain an individual sealing body with respect to the sealing body sealed with, the sealing body is a sealing body that is warped upward or downward. By cutting into individual sealing bodies, the warpage is reduced.

【0026】これにより、封止工程において封止体が加
熱されて反っても、個別封止体に切断することによって
反りが減少するので、ボール電極と外部電極とのズレ量
を減少させることが可能となり、ボール電極を外部電極
に高精度に搭載することができる。
With this, even if the sealing body is heated and warped in the sealing step, the warpage is reduced by cutting the sealing body into individual sealing bodies, so that the amount of deviation between the ball electrode and the external electrode can be reduced. This makes it possible to mount the ball electrode on the external electrode with high accuracy.

【0027】また、少なくとも上面に配線電極と底面に
前記配線電極と電気的に接続した外部電極を有した配線
基板の上面に複数の半導体素子が搭載され、その上面に
実質的全面が封止樹脂で封止された封止体に対して、各
半導体素子単位に前記配線基板を切断して個別封止体を
得る工程では、回転ブレードにより各半導体素子単位に
分割する。
A plurality of semiconductor elements are mounted on an upper surface of a wiring board having a wiring electrode on at least an upper surface and external electrodes electrically connected to the wiring electrode on a lower surface, and a substantially entire surface of the upper surface is formed of a sealing resin. In the step of cutting the wiring substrate for each semiconductor element unit to obtain an individual sealed body with respect to the sealed body sealed by the above, the semiconductor device is divided into each semiconductor element unit by a rotating blade.

【0028】このように、回転ブレードを用いることに
より、短時間で高精度に封止体を切断し、個別封止体を
形成することができる。
As described above, by using the rotating blade, the sealing body can be cut with high accuracy in a short time, and an individual sealing body can be formed.

【0029】また、少なくとも上面に配線電極と底面に
前記配線電極と電気的に接続した外部電極を有した配線
基板の上面に複数の半導体素子が搭載され、その上面に
実質的全面が封止樹脂で封止された封止体に対して、各
半導体素子単位に前記配線基板を切断して個別封止体を
得る工程において、配線基板は1枚の基板上に複数の半
導体素子が搭載でき、個々の半導体素子ごとに切断する
ことができる配線基板である。
A plurality of semiconductor elements are mounted on an upper surface of a wiring board having a wiring electrode on at least an upper surface and external electrodes electrically connected to the wiring electrode on a lower surface, and a substantially entire surface is formed of a sealing resin. In the step of cutting the wiring board for each semiconductor element unit to obtain an individual sealed body for the sealed body sealed with, the wiring board can mount a plurality of semiconductor elements on one substrate, This is a wiring board that can be cut for each individual semiconductor element.

【0030】このように、複数の半導体素子が搭載でき
る配線基板を用いることにより、複数の半導体素子を一
括して同時に封止することが可能であるので、生産性の
向上を実現できる。
As described above, by using a wiring board on which a plurality of semiconductor elements can be mounted, a plurality of semiconductor elements can be collectively sealed at the same time, thereby improving productivity.

【0031】また、半導体素子の電極に形成されたバン
プと配線基板の配線電極とを電気的に接続する。
Further, the bumps formed on the electrodes of the semiconductor element are electrically connected to the wiring electrodes of the wiring board.

【0032】これにより、小型化とともに配線長の短縮
が可能となり、高周波デバイスにも適用できる。
As a result, it is possible to reduce the wiring length as well as the size, and the present invention can be applied to a high-frequency device.

【0033】また、半導体素子の裏面と配線基板の上面
とを接着し、前記半導体素子の電極と配線基板の配線電
極とを金属細線で電気的に接続する。
Further, the back surface of the semiconductor element is bonded to the upper surface of the wiring board, and the electrode of the semiconductor element and the wiring electrode of the wiring board are electrically connected by a thin metal wire.

【0034】これにより、ワイヤボンディング装置を用
いて半導体素子の電極と配線基板の表面の電極部との電
気的接続が可能となる。
This makes it possible to electrically connect the electrodes of the semiconductor element to the electrode portions on the surface of the wiring board by using the wire bonding apparatus.

【0035】また、複数の半導体素子がその面内に形成
された半導体ウェハーの上面に樹脂が形成され、前記樹
脂の面に前記複数の半導体素子と各々接続した外部電極
が設けられた封止体に対して、各半導体素子単位に前記
半導体ウェハーを切断して個別封止体を得る工程と、前
記個別封止体の外部電極側を上にして複数個配列する工
程と、前記配列された複数の個別封止体の外部電極上に
各々同時にボール電極を搭載する工程とよりなる。
In addition, a resin is formed on an upper surface of a semiconductor wafer having a plurality of semiconductor elements formed in the surface thereof, and a sealing body provided with external electrodes respectively connected to the plurality of semiconductor elements on the surface of the resin. A step of cutting the semiconductor wafer for each semiconductor element unit to obtain an individual sealing body, a step of arranging a plurality of the individual sealing bodies with the external electrode side facing up, And mounting the ball electrodes simultaneously on the external electrodes of the individual sealing bodies.

【0036】これにより、半導体ウェハーを切断して個
別封止体を得た後に、複数の個別封止体の外部電極上に
各々同時にボール電極を搭載することで、ボール電極の
搭載精度が向上する。
[0036] Thereby, after the semiconductor wafer is cut to obtain the individual sealing bodies, the ball electrodes are simultaneously mounted on the external electrodes of the plurality of individual sealing bodies, respectively, so that the mounting accuracy of the ball electrodes is improved. .

【0037】また、複数の半導体素子がその面内に形成
された半導体ウェハーの上面に樹脂が形成され、前記樹
脂の面に前記複数の半導体素子と各々接続した外部電極
が設けられた封止体に対して、各半導体素子単位に前記
半導体ウェハーを切断して個別封止体を得る工程におい
て、前記封止体は上方または下方に反っている封止体で
あり、個別封止体に切断することによりその反りを減少
させる。
In addition, a resin is formed on an upper surface of a semiconductor wafer having a plurality of semiconductor elements formed in the surface thereof, and an external electrode provided on the surface of the resin is provided with external electrodes respectively connected to the plurality of semiconductor elements. On the other hand, in the step of cutting the semiconductor wafer for each semiconductor element unit to obtain an individual sealing body, the sealing body is a sealing body that is warped upward or downward, and cut into individual sealing bodies. This reduces that warpage.

【0038】これにより、半導体ウェハーの大口径化に
伴って、半導体ウェハーの反り量が増大しても、半導体
ウェハーの電極または半導体ウェハーの電極に接続した
外部電極に対して、高精度にボール電極を搭載すること
が可能となる。
Thus, even if the amount of warpage of the semiconductor wafer increases with the increase in the diameter of the semiconductor wafer, the ball electrode can be precisely formed with respect to the electrode of the semiconductor wafer or the external electrode connected to the electrode of the semiconductor wafer. Can be mounted.

【0039】また、複数のボール電極を吸着穴で吸着し
て搬送するボール電極搭載ヘッドと、少なくとも上面に
配線電極と底面に前記配線電極と電気的に接続した外部
電極を有した配線基板の上面に半導体素子が搭載され、
その上面が封止樹脂で封止された各半導体素子単位の個
別封止体の複数個を配列するための搬送治具とからなる
半導体装置の製造装置であって、前記複数のボール電極
と前記配線基板の外部電極とを位置合わせし、前記配列
された複数の個別封止体の裏面の外部電極上に各々同時
にボール電極を搭載する。
A ball electrode mounting head for sucking and transferring a plurality of ball electrodes by suction holes, and an upper surface of a wiring board having at least a wiring electrode on an upper surface and an external electrode electrically connected to the wiring electrode on a lower surface. The semiconductor element is mounted on
An apparatus for manufacturing a semiconductor device, comprising: a transport jig for arranging a plurality of individual sealing bodies of each semiconductor element unit whose upper surface is sealed with a sealing resin, wherein the plurality of ball electrodes and The external electrodes of the wiring board are aligned with each other, and the ball electrodes are simultaneously mounted on the external electrodes on the back surfaces of the plurality of individual sealing bodies arranged.

【0040】これにより、配線基板の反りの影響を受け
ることなく平坦性の高い状態で配線基板の外部電極にボ
ール電極を搭載することができるので、外部電極にボー
ル電極を高精度に搭載することが可能である。
Thus, the ball electrode can be mounted on the external electrode of the wiring board in a state of high flatness without being affected by the warpage of the wiring board. Therefore, the ball electrode can be mounted on the external electrode with high precision. Is possible.

【0041】また、搬送治具の上面に耐熱性粘着テープ
を設置し、前記耐熱性粘着テープ上に個別封止体を搭載
する。
Further, a heat-resistant adhesive tape is provided on the upper surface of the transport jig, and an individual sealing body is mounted on the heat-resistant adhesive tape.

【0042】これにより、個別封止体を耐熱性粘着テー
プ上で容易に固定することができ、ボール電極の搭載精
度が向上する。
Thus, the individual sealing body can be easily fixed on the heat-resistant adhesive tape, and the mounting accuracy of the ball electrode is improved.

【0043】[0043]

【発明の実施の形態】以下、本発明の半導体装置の製造
方法および製造装置の一実施形態について、図面を参照
しながら説明する。
DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of a method and an apparatus for manufacturing a semiconductor device according to the present invention will be described below with reference to the drawings.

【0044】まず、本実施形態の半導体装置の製造方法
について説明する。
First, a method for manufacturing the semiconductor device of the present embodiment will be described.

【0045】図1は、本実施形態の半導体装置の製造方
法の各製造工程を示すフロー図である。
FIG. 1 is a flowchart showing each manufacturing process of the method of manufacturing a semiconductor device according to the present embodiment.

【0046】図1に示すように、まず、複数の半導体素
子が形成された半導体ウェハーの電極にバンプを形成す
る(バンプ形成工程)。本実施形態ではワイヤボンディ
ング法によってAuバンプを形成しているが、めっき法
によってバンプを形成してもよい。
As shown in FIG. 1, first, a bump is formed on an electrode of a semiconductor wafer on which a plurality of semiconductor elements have been formed (bump forming step). In the present embodiment, the Au bump is formed by a wire bonding method, but the bump may be formed by a plating method.

【0047】次に、半導体素子の電極に形成されたバン
プと、その底面に外部電極が形成された配線基板の上面
に形成された配線電極とを直接電気的に接続する(フリ
ップチップ実装工程)。バンプには、あらかじめ銀パラ
ジウム等の導電粒子を含む導電性接着剤を付着させてお
き、実装後に導電性接着剤を硬化させることによって接
合信頼性を向上させることも可能である。
Next, the bumps formed on the electrodes of the semiconductor element are directly electrically connected to the wiring electrodes formed on the upper surface of the wiring substrate having the external electrodes formed on the bottom surfaces thereof (flip chip mounting step). . A bonding adhesive containing conductive particles such as silver palladium is attached to the bumps in advance, and the bonding reliability can be improved by curing the conductive adhesive after mounting.

【0048】本実施形態では、半導体素子と配線基板と
をフリップチップ接続しているが、半導体素子の裏面と
配線基板の上面とを接着し、半導体素子の電極と配線基
板の上面の電極部とを金属細線で電気的に接続してもよ
い。
In this embodiment, the semiconductor element and the wiring substrate are flip-chip connected. However, the back surface of the semiconductor element and the upper surface of the wiring substrate are bonded together, and the electrodes of the semiconductor element and the electrode portions on the upper surface of the wiring substrate are connected. May be electrically connected by a thin metal wire.

【0049】そして、配線基板の上面の実質的全面を封
止樹脂によって封止する。すなわち、配線基板の上面に
搭載された複数の半導体素子をエポキシ樹脂等からなる
封止樹脂によって封止し、複数の半導体素子が封止され
た封止体を形成する(封止工程)。
Then, substantially the entire upper surface of the wiring board is sealed with a sealing resin. That is, a plurality of semiconductor elements mounted on the upper surface of the wiring board are sealed with a sealing resin made of epoxy resin or the like to form a sealed body in which the plurality of semiconductor elements are sealed (sealing step).

【0050】次に、この封止体の半導体素子ごとの境界
部をブレードによってダイシング切断して個別封止体に
分割する(封止体分割工程)。
Next, a boundary portion of each semiconductor element of the sealing body is cut by dicing with a blade and divided into individual sealing bodies (sealing body dividing step).

【0051】次に、搬送治具の上面に複数の個別封止体
を配列する。この際、個別封止体の裏面の外部電極側が
上側になるようにして個別封止体を配列する。なお、搬
送治具の表面に個別封止体を配列する前に、個別封止体
が良品であるか否かを検査し、良品の個別封止体のみを
搬送治具に搭載することにより、不良の個別封止体の裏
面の外部電極にボール電極を搭載することを防止できる
ので生産効率が向上する。
Next, a plurality of individual sealing bodies are arranged on the upper surface of the transport jig. At this time, the individual sealing bodies are arranged such that the external electrode side on the back surface of the individual sealing body faces upward. Before arranging the individual sealing bodies on the surface of the transport jig, it is checked whether the individual sealing bodies are non-defective, and by mounting only the non-defective individual sealing bodies on the transport jig, Since the mounting of the ball electrode on the external electrode on the back surface of the defective individual sealing body can be prevented, the production efficiency is improved.

【0052】そして、複数の個別封止体の外部電極に対
して、ボール電極搭載ヘッドの吸着穴に吸着された複数
のボール電極を位置合わせし、複数の個別封止体の裏面
の外部電極に対して複数のボール電極を各々同時に搭載
する。なお、搬送治具の表面に耐熱性粘着テープを設置
しておき、この耐熱性粘着テープ上に個別封止体を搭載
することによって、個別封止体を搬送治具に容易に固定
することができる(ボール電極搭載工程)。
Then, the plurality of ball electrodes sucked in the suction holes of the ball electrode mounting head are aligned with the plurality of external electrodes of the individual sealing body, and the external electrodes on the back surfaces of the plurality of individual sealing bodies are aligned. On the other hand, a plurality of ball electrodes are simultaneously mounted. In addition, by installing a heat-resistant adhesive tape on the surface of the transport jig and mounting the individual sealing body on the heat-resistant adhesive tape, the individual sealed body can be easily fixed to the transport jig. Yes (ball electrode mounting process).

【0053】次に、ボール電極が搭載された複数の個別
封止体を搬送治具とともに、一定温度以上の雰囲気中を
通過させることによってボール電極を溶融させる。その
後、搬送治具に搭載された複数の個別封止体を室温中で
冷却することにより、個別封止体の裏面の外部電極のハ
ンダを固化させる(リフロ工程)。
Next, the ball electrodes are melted by passing the plurality of individual sealing bodies on which the ball electrodes are mounted together with the transport jig in an atmosphere at a certain temperature or higher. Thereafter, by cooling the plurality of individual sealing bodies mounted on the transport jig at room temperature, the solder of the external electrodes on the back surface of the individual sealing bodies is solidified (reflow step).

【0054】そして、所定のトレイに複数の個別封止体
を配置して収納する(トレイ収納工程)。
Then, a plurality of individual sealing bodies are arranged and stored in a predetermined tray (tray storing step).

【0055】以上、本実施形態の半導体装置の製造方法
は、複数の半導体素子が配線基板に搭載された封止体を
半導体素子ごとに分割した後に、複数のボール電極を各
々同時に複数の個別封止体の外部電極に搭載するので、
封止工程で加熱されることによって発生する封止体の反
り量が、分割後の複数の個別封止体に分散され、外部電
極がほぼ平坦な状態でボール電極を搭載することができ
る。したがって、ボール電極を外部電極に対して高精度
に搭載することが可能になるので、外部電極からはみ出
してボール電極が搭載されるといった不具合もなくな
り、半導体装置の生産性向上を達成できるものである。
As described above, in the method of manufacturing a semiconductor device according to the present embodiment, after a plurality of semiconductor elements mounted on a wiring board are divided into individual semiconductor elements, a plurality of ball electrodes are simultaneously respectively sealed with a plurality of individual sealing elements. Since it is mounted on the external electrode of the stop,
The amount of warpage of the sealing body generated by heating in the sealing step is dispersed among the plurality of individual sealing bodies after division, and the ball electrode can be mounted with the external electrode being substantially flat. Therefore, the ball electrode can be mounted on the external electrode with high accuracy, so that the problem that the ball electrode is mounted outside the external electrode is eliminated, and the productivity of the semiconductor device can be improved. .

【0056】次に、図1を用いて説明した本実施形態の
半導体装置の製造方法について、さらに図面を用いて詳
細に説明する。
Next, the method of manufacturing the semiconductor device of the present embodiment described with reference to FIG. 1 will be described in detail with reference to the drawings.

【0057】なお、前記と共通の内容については省略す
る。
The contents common to the above are omitted.

【0058】図2は、本実施形態の半導体装置の製造方
法の工程の一部を示す断面図である。
FIG. 2 is a cross-sectional view showing a part of the steps of the method for manufacturing a semiconductor device according to the present embodiment.

【0059】図2(a)に示すように、複数の電極9が
形成された半導体ウェハー10を用意する。
As shown in FIG. 2A, a semiconductor wafer 10 on which a plurality of electrodes 9 are formed is prepared.

【0060】次に図2(b)に示すように、それぞれの
電極9にバンプ11を形成する。本実施形態では、バン
プ11はワイヤボンディング法によってAuバンプを形
成したが、メッキ法を用いて形成してもよい。
Next, as shown in FIG. 2B, bumps 11 are formed on each of the electrodes 9. In the present embodiment, the bump 11 is formed by an Au bump by a wire bonding method, but may be formed by a plating method.

【0061】次に図2(c)および図2(d)に示すよ
うに、バンプ11が形成された半導体ウェハー10を反
転させて、ガラスエポキシ樹脂からなる配線基板12の
上面にフリップチップ実装する。ここで、封止樹脂13
を半導体ウェハー10と配線基板12との間に注入して
加熱、硬化させるとともにバンプ11を配線基板12の
上面に形成された配線電極14に電気的に接続し、複数
の半導体素子15が搭載された封止体16を形成する。
そして、半導体ウェハー10を半導体素子15ごとの境
界部17を通る直線上において、配線基板12、封止樹
脂13とともにブレードを用いてダイシング切断し、複
数の個別封止体18を形成する。
Next, as shown in FIGS. 2 (c) and 2 (d), the semiconductor wafer 10 on which the bumps 11 are formed is inverted and flip-chip mounted on the upper surface of a wiring board 12 made of glass epoxy resin. . Here, the sealing resin 13
Is injected between the semiconductor wafer 10 and the wiring substrate 12, heated and cured, and the bumps 11 are electrically connected to the wiring electrodes 14 formed on the upper surface of the wiring substrate 12, so that a plurality of semiconductor elements 15 are mounted. A sealed body 16 is formed.
Then, the semiconductor wafer 10 is diced and cut using a blade together with the wiring substrate 12 and the sealing resin 13 on a straight line passing through the boundary portion 17 for each semiconductor element 15 to form a plurality of individual sealing bodies 18.

【0062】なお、配線基板12の底面にはボール電極
が搭載されるための外部電極19が形成されている。
An external electrode 19 for mounting a ball electrode is formed on the bottom surface of the wiring board 12.

【0063】以上の封止工程では、封止樹脂の硬化時に
封止体が加熱されるために、封止体が全面にわたって反
ってしまうが、複数の個別封止体に分割することによっ
て反り量が分散されるので反りを減少させることがで
き、高精度なボール電極の搭載を実現できる。
In the above-mentioned sealing step, the sealing body is heated when the sealing resin is cured, so that the sealing body warps over the entire surface. Are dispersed, so that warpage can be reduced, and mounting of the ball electrode with high accuracy can be realized.

【0064】ところで、通常は、複数の半導体素子が搭
載されて封止された封止体がブレードによってダイシン
グされた後、個別の封止体は、配線基板側を下側にして
トレイに収納される。しかしながら、配線基板に形成さ
れた外部電極にボール電極を搭載する必要があるため、
トレイに収納された個別封止体を表裏反転させてから、
搬送治具に封止体を配列しなければならない。
Usually, after a sealed body on which a plurality of semiconductor elements are mounted and sealed is diced with a blade, the individual sealed bodies are stored in a tray with the wiring substrate side down. You. However, since it is necessary to mount the ball electrode on the external electrode formed on the wiring board,
After turning over the individual sealing bodies stored in the tray,
Seals must be arranged on the transport jig.

【0065】そこで、個別封止体を表裏反転させる搬送
装置が必要となる。
Therefore, a transport device for turning the individual sealing body upside down is required.

【0066】以下、個別封止体の表裏を反転させる搬送
キャリア搭載機について、図面を用いて説明する。
Hereinafter, a transport carrier mounting machine for reversing the front and back of the individual sealing body will be described with reference to the drawings.

【0067】図3は、個別封止体の表裏を反転させるた
めの搬送キャリア搭載機の斜視図である。
FIG. 3 is a perspective view of a carrier mounting machine for turning over the individual sealing body.

【0068】図3に示すように、まず、トレイ20の上
面に形成された複数の凹部に個別封止体18の外部電極
を下側にして搭載する。複数の個別封止体18を順次、
チップ反転ヘッド21によって吸着して反転させた後、
チップ移載ヘッド22によって吸着する。この段階で、
個別封止体は外部電極を上側にしてチップ移載ヘッド2
2に吸着された状態となっている。また、認識カメラ2
3によってトレイ20の認識マークを認識することによ
ってチップ移載ヘッド22の搬送精度を向上させてい
る。
As shown in FIG. 3, first, the external electrodes of the individual sealing body 18 are mounted in a plurality of recesses formed on the upper surface of the tray 20 with the external electrodes facing down. A plurality of individual sealing bodies 18 are sequentially
After being attracted and inverted by the chip inversion head 21,
The suction is performed by the chip transfer head 22. At this stage,
The chip transfer head 2 with the external electrodes facing upward
2 is in a state of being adsorbed. In addition, recognition camera 2
3, the recognition accuracy of the chip transfer head 22 is improved by recognizing the recognition mark on the tray 20.

【0069】次に、チップ移載ヘッド22によって個別
封止体18を搬送治具24の上面に搬送して収納する。
搬送治具24に一定個数の個別封止体18が配列される
と搬送治具24がコムマガジン25に移動して収納され
る。
Next, the individual sealing body 18 is transported and stored on the upper surface of the transport jig 24 by the chip transfer head 22.
When a certain number of the individual sealing bodies 18 are arranged on the transport jig 24, the transport jig 24 is moved to and stored in the comb magazine 25.

【0070】次に、搬送治具に配列された複数の個別封
止体の外部電極にボール電極を搭載し、リフロする工程
について説明する。本実施形態では、ボール電極として
ハンダを材料としたハンダボールを用いている。
Next, a process of mounting ball electrodes on the external electrodes of the plurality of individual sealing bodies arranged on the transport jig and performing reflow will be described. In the present embodiment, a solder ball made of solder is used as the ball electrode.

【0071】図4は、図2に示した本実施形態の半導体
装置の製造方法に続く工程の一部を示す断面図である。
FIG. 4 is a cross-sectional view showing a part of a step following the method of manufacturing the semiconductor device of the present embodiment shown in FIG.

【0072】図4(a)に示すように、配線基板12が
半導体ウェハー10の上側になるように個別封止体18
を搬送治具24の凹部26に収納する。
As shown in FIG. 4A, the individual sealing members 18 are arranged so that the wiring substrate 12 is located above the semiconductor wafer 10.
Is stored in the concave portion 26 of the transport jig 24.

【0073】次に図4(b)および図4(c)に示すよ
うに、複数の個別封止体18の外部電極19上に各々同
時に複数のボール電極27を同時に搭載する。本実施形
態では、ボール電極としてハンダを材料とするハンダボ
ールを用いたが、その他の金属粒子および球状の樹脂に
金属膜をコートしたものを用いてもよい。
Next, as shown in FIGS. 4B and 4C, a plurality of ball electrodes 27 are simultaneously mounted on the external electrodes 19 of the plurality of individual sealing bodies 18, respectively. In the present embodiment, a solder ball made of solder is used as the ball electrode, but other metal particles and a spherical resin coated with a metal film may be used.

【0074】そして、複数の個別封止体18とともに搬
送治具24を一定温度以上の雰囲気中に通過させてボー
ル電極27を溶融させ、その後、室温でハンダ28を硬
化させる。なお、搬送治具24の凹部26の底面に耐熱
性粘着テープを設置し、この耐熱性粘着テープ上に個別
封止体18を搭載することによって個別封止体18を容
易に固定することができ、ボール電極27の外部電極1
9に対する搭載精度が向上する。
Then, the carrier jig 24 is passed through an atmosphere having a temperature equal to or higher than a predetermined temperature together with the plurality of individual sealing bodies 18 to melt the ball electrodes 27, and thereafter, the solder 28 is cured at room temperature. In addition, the individual sealing body 18 can be easily fixed by installing a heat-resistant adhesive tape on the bottom surface of the concave portion 26 of the transport jig 24 and mounting the individual sealing body 18 on the heat-resistant adhesive tape. , External electrode 1 of ball electrode 27
9 is improved in mounting accuracy.

【0075】次に、本発明の半導体装置の製造方法の別
の実施形態について説明する。
Next, another embodiment of the method of manufacturing a semiconductor device according to the present invention will be described.

【0076】複数の半導体素子が形成された半導体ウェ
ハーの上面に樹脂が形成され、その樹脂の面に複数の半
導体素子と各々接続した外部電極が設けられた封止体に
対して、各半導体素子単位に半導体ウェハーを切断して
個別封止体を得る工程と、個別封止体の外部電極側を上
にして複数個配列する工程と、配列された複数の個別封
止体の外部電極上に各々同時にボール電極を搭載する工
程とよりなる。
Resin is formed on the upper surface of a semiconductor wafer on which a plurality of semiconductor elements are formed, and each semiconductor element is sealed with respect to a sealing body provided with external electrodes respectively connected to the plurality of semiconductor elements on the surface of the resin. A step of obtaining individual sealed bodies by cutting the semiconductor wafer into units, a step of arranging a plurality of individual sealed bodies with the external electrode side facing up, and a step of arranging a plurality of arranged individual sealed bodies on external electrodes. And a step of mounting ball electrodes at the same time.

【0077】このように、半導体素子の電極と接続され
た外部電極が樹脂の面に形成されることによって外部電
極が可動性を有することになって、信頼性の高い電気的
接続を確保できるとともに、外部電極にボール電極を高
精度に搭載することが可能となる。
As described above, since the external electrode connected to the electrode of the semiconductor element is formed on the surface of the resin, the external electrode has mobility, and a highly reliable electrical connection can be ensured. In addition, a ball electrode can be mounted on the external electrode with high accuracy.

【0078】また、以上の実施形態では搬送治具の凹部
に封止体を収納したが、凹部が形成されない平坦な表面
の搬送治具を用いて、搬送治具の表面に封止体または半
導体素子を配列して搭載してもよい。
In the above embodiment, the sealing body is housed in the concave portion of the transport jig. However, a flat surface of the transport jig where no concave portion is formed is used, and the sealing member or the semiconductor is placed on the surface of the transport jig. The elements may be arranged and mounted.

【0079】以上、本実施形態の半導体装置の製造方法
により、封止体の封止工程において加熱されることによ
って発生する封止体の反りを、封止体を個別封止体に分
割することにより反りを減少させ、配列された個別封止
体の裏面電極を平坦な状態にすることができるので、ボ
ール電極を個別封止体の外部電極に高精度に搭載するこ
とができる。
As described above, according to the manufacturing method of the semiconductor device of the present embodiment, the warpage of the sealing body caused by heating in the sealing step of sealing the sealing body is divided into individual sealing bodies. As a result, the warpage is reduced, and the rear electrodes of the arranged individual sealing bodies can be made flat, so that the ball electrodes can be mounted on the external electrodes of the individual sealing bodies with high accuracy.

【0080】また、半導体ウェハーの上面に樹脂が設け
られ、その樹脂の面に半導体ウェハーの電極と各々接続
された外部電極が形成され、その外部電極にボール電極
を搭載する場合においても、半導体ウェハーを個別半導
体素子に分割することで、半導体ウェハーの反りを減少
させ、配列された個別半導体素子の電極を平坦な状態に
することができるので、ボール電極を個別半導体素子の
電極に高精度に搭載することができる。
Further, when a resin is provided on the upper surface of the semiconductor wafer, external electrodes connected to electrodes of the semiconductor wafer are formed on the surface of the resin, and a ball electrode is mounted on the external electrode. Is divided into individual semiconductor elements, so that the warpage of the semiconductor wafer can be reduced and the electrodes of the arranged individual semiconductor elements can be made flat, so the ball electrodes can be mounted on the individual semiconductor element electrodes with high precision. can do.

【0081】次に、本実施形態の半導体装置の製造装置
について図面を参照しながら説明する。
Next, an apparatus for manufacturing a semiconductor device according to this embodiment will be described with reference to the drawings.

【0082】図5は、本実施形態の半導体装置の製造装
置を示す図である。
FIG. 5 is a diagram showing an apparatus for manufacturing a semiconductor device according to the present embodiment.

【0083】前記した半導体装置の製造方法の実施形態
と同一の構成要件については同一の符号を付し、同一の
内容については省略する。また、封止体の構造について
は簡略化して示している。
The same components as those in the embodiment of the semiconductor device manufacturing method described above are denoted by the same reference numerals, and the same contents are omitted. Further, the structure of the sealing body is shown in a simplified manner.

【0084】図5に示すように、複数のボール電極27
をボール電極搭載ヘッド29の吸着穴30で吸着し、搬
送治具24の凹部26に収納された個別封止体18の外
部電極19に位置合わせする。また、リフロ時のボール
電極27の濡れ性を向上させるために、外部電極19の
表面には、あらかじめフラックス31を塗布しておく。
そして、複数のボール電極27を外部電極19に搭載す
る。
As shown in FIG. 5, a plurality of ball electrodes 27
Is sucked by the suction hole 30 of the ball electrode mounting head 29, and is aligned with the external electrode 19 of the individual sealing body 18 stored in the concave portion 26 of the transport jig 24. Further, in order to improve the wettability of the ball electrode 27 during the reflow, the flux 31 is applied to the surface of the external electrode 19 in advance.
Then, the plurality of ball electrodes 27 are mounted on the external electrodes 19.

【0085】また、凹部26の底面に耐熱性粘着テープ
を設置することで、個別封止体18を容易に固定し、ボ
ール電極27の搭載精度を向上させることができる。
Further, by providing a heat-resistant adhesive tape on the bottom surface of the concave portion 26, the individual sealing body 18 can be easily fixed, and the mounting accuracy of the ball electrode 27 can be improved.

【0086】図6は、搬送治具に粘着性テープを設置す
る方法を示した図である。
FIG. 6 is a diagram showing a method of installing an adhesive tape on a transport jig.

【0087】図6に示すように、搬送治具24の凹部2
6の底面には凹部の底面よりも小さい開口部を有し、耐
熱性粘着テープ32を搬送治具の底面側から貼付するこ
とで、凹部26に収納される個別封止体を開口部を通し
て耐熱性粘着テープ32により固定することが可能とな
る。なお、凹部が形成されない平坦な表面の搬送治具の
場合は、搬送治具の表面に耐熱性粘着テープを設置し
て、個別封止体または樹脂が形成された半導体素子を耐
熱性粘着テープ上に搭載してもよい。
As shown in FIG.
6 has an opening smaller than the bottom of the recess, and the heat-resistant adhesive tape 32 is adhered from the bottom side of the conveying jig to allow the individual sealing body accommodated in the recess 26 to pass through the opening. It becomes possible to fix with the adhesive tape 32. In the case of a transfer jig having a flat surface on which no concave portion is formed, a heat-resistant adhesive tape is provided on the surface of the transfer jig, and the semiconductor element on which the individual sealing body or the resin is formed is placed on the heat-resistant adhesive tape. It may be mounted on.

【0088】以上、本実施形態の半導体装置の製造装置
により、複数の個別封止体または樹脂が形成された個別
の半導体素子の複数個に対して複数のボール電極を各々
同時に搭載することができるので、個別に切断される前
の封止体または半導体ウェハーの反りが、各個別封止体
または各個別の半導体素子に分散され、高精度なボール
電極の搭載が可能になる。
As described above, according to the semiconductor device manufacturing apparatus of the present embodiment, a plurality of ball electrodes can be simultaneously mounted on a plurality of individual sealing elements or a plurality of individual semiconductor elements on which resin is formed. Therefore, the warpage of the sealing body or the semiconductor wafer before being individually cut is dispersed to each of the sealing bodies or each of the individual semiconductor elements, so that the ball electrodes can be mounted with high accuracy.

【0089】[0089]

【発明の効果】本発明の半導体装置の製造方法および製
造装置は、複数の半導体素子の封止体を個別封止体に分
割した後に、複数の個別封止体の外部電極に複数のボー
ル電極を各々同時に搭載するので、封止体の封止時の加
熱によって発生する反りを低減することができ、個別封
止体の外部電極に高精度にボール電極を搭載することが
可能となる。
According to the method and the apparatus for manufacturing a semiconductor device of the present invention, after dividing a plurality of semiconductor element sealing bodies into individual sealing bodies, a plurality of ball electrodes are formed on external electrodes of the plurality of individual sealing bodies. Are simultaneously mounted, so that warpage caused by heating at the time of sealing of the sealing body can be reduced, and the ball electrode can be mounted on the external electrode of the individual sealing body with high accuracy.

【0090】また、半導体ウェハーの上面に樹脂が設け
られ、その樹脂の面に半導体ウェハーの電極と各々接続
された外部電極が形成され、その外部電極にボール電極
を搭載する場合においても、半導体ウェハーを個別半導
体素子に分割することで、半導体ウェハーの反りを減少
させ、配列された個別半導体素子の電極を平坦な状態に
することができるので、ボール電極を個別半導体素子の
電極に高精度に搭載することができる。
Further, when a resin is provided on the upper surface of the semiconductor wafer, and external electrodes connected to the electrodes of the semiconductor wafer are formed on the surface of the resin, and the ball electrodes are mounted on the external electrodes, the semiconductor wafer is also used. Is divided into individual semiconductor elements, so that the warpage of the semiconductor wafer can be reduced and the electrodes of the arranged individual semiconductor elements can be made flat, so the ball electrodes can be mounted on the individual semiconductor element electrodes with high precision. can do.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の一実施形態の半導体装置の製造方法を
示すフロー図
FIG. 1 is a flowchart showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.

【図2】本発明の一実施形態の半導体装置の製造方法を
示す断面図
FIG. 2 is a sectional view showing the method for manufacturing the semiconductor device according to the embodiment of the present invention;

【図3】本発明の一実施形態の半導体装置の製造方法を
示す斜視図
FIG. 3 is a perspective view showing a method for manufacturing a semiconductor device according to one embodiment of the present invention;

【図4】本発明の一実施形態の半導体装置の製造方法を
示す断面図
FIG. 4 is a sectional view showing the method of manufacturing the semiconductor device according to one embodiment of the present invention;

【図5】本発明の一実施形態の半導体装置の製造装置を
示す断面図
FIG. 5 is a sectional view showing a semiconductor device manufacturing apparatus according to one embodiment of the present invention;

【図6】本発明の一実施形態の半導体装置の製造方法を
示す図
FIG. 6 is a diagram showing a method for manufacturing a semiconductor device according to one embodiment of the present invention;

【図7】従来の半導体装置の製造方法を示すフロー図FIG. 7 is a flowchart showing a conventional method for manufacturing a semiconductor device.

【図8】従来の半導体装置の製造方法を示す断面図FIG. 8 is a sectional view showing a conventional method for manufacturing a semiconductor device.

【図9】従来の半導体装置の製造方法を示す断面図FIG. 9 is a cross-sectional view illustrating a conventional method for manufacturing a semiconductor device.

【符号の説明】[Explanation of symbols]

1 半導体素子 2 配線基板 3 外部電極 4 ボール電極 5 金属細線 6 ボール電極搭載ヘッド 7 吸着穴 8 ズレ 9 電極 10 半導体ウェハー 11 バンプ 12 配線基板 13 封止樹脂 14 配線電極 15 半導体素子 16 封止体 17 境界部 18 個別封止体 19 外部電極 20 トレイ 21 チップ反転ヘッド 22 チップ移載ヘッド 23 認識カメラ 24 搬送治具 25 コムマガジン 26 凹部 27 ボール電極 28 ハンダ 29 ボール電極搭載ヘッド 30 吸着穴 31 フラックス 32 耐熱性粘着テープ Reference Signs List 1 semiconductor element 2 wiring board 3 external electrode 4 ball electrode 5 thin metal wire 6 ball electrode mounting head 7 suction hole 8 gap 9 electrode 10 semiconductor wafer 11 bump 12 wiring board 13 sealing resin 14 wiring electrode 15 semiconductor element 16 sealing body 17 Boundary part 18 Individual sealing body 19 External electrode 20 Tray 21 Chip reversing head 22 Chip transfer head 23 Recognition camera 24 Transport jig 25 Com magazine 26 Depression 27 Ball electrode 28 Solder 29 Ball electrode mounting head 30 Suction hole 31 Flux 32 Heat resistance Adhesive tape

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.7 識別記号 FI テーマコート゛(参考) H01L 23/12 501 H01L 23/12 501C 501P ──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. 7 Identification symbol FI Theme coat ゛ (Reference) H01L 23/12 501 H01L 23/12 501C 501P

Claims (10)

【特許請求の範囲】[Claims] 【請求項1】 少なくとも上面に配線電極と底面に前記
配線電極と電気的に接続した外部電極を有した配線基板
の上面に複数の半導体素子が搭載され、その上面に実質
的全面が封止樹脂で封止された封止体に対して、各半導
体素子単位に前記配線基板を切断して個別封止体を得る
工程と、前記個別封止体の裏面の外部電極側を上にして
複数個配列する工程と、前記配列された複数の個別封止
体の裏面の外部電極上に各々同時にボール電極を搭載す
る工程とよりなることを特徴とする半導体装置の製造方
法。
1. A plurality of semiconductor elements are mounted on an upper surface of a wiring substrate having a wiring electrode on at least an upper surface and external electrodes electrically connected to the wiring electrode on a lower surface, and a substantially entire surface of the upper surface is formed of a sealing resin. A step of cutting the wiring substrate for each semiconductor element unit to obtain an individual sealing body with respect to the sealing body sealed with A method of manufacturing a semiconductor device, comprising: arranging and simultaneously mounting ball electrodes on external electrodes on the back surfaces of the arranged plurality of individual sealing bodies, respectively.
【請求項2】 少なくとも上面に配線電極と底面に前記
配線電極と電気的に接続した外部電極を有した配線基板
の上面に複数の半導体素子が搭載され、その上面に実質
的全面が封止樹脂で封止された封止体に対して、各半導
体素子単位に前記配線基板を切断して個別封止体を得る
工程において、前記封止体は上方または下方に反ってい
る封止体であり、個別封止体に切断することによりその
反りを減少させることを特徴とする請求項1に記載の半
導体装置の製造方法。
2. A plurality of semiconductor elements are mounted on an upper surface of a wiring substrate having a wiring electrode on at least an upper surface and external electrodes electrically connected to the wiring electrode on a lower surface, and a substantially entire surface of the upper surface is formed of a sealing resin. In the step of cutting the wiring substrate for each semiconductor element unit to obtain an individual sealing body with respect to the sealing body sealed with, the sealing body is a sealing body that is warped upward or downward. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the warpage is reduced by cutting into individual sealing bodies.
【請求項3】 少なくとも上面に配線電極と底面に前記
配線電極と電気的に接続した外部電極を有した配線基板
の上面に複数の半導体素子が搭載され、その上面に実質
的全面が封止樹脂で封止された封止体に対して、各半導
体素子単位に前記配線基板を切断して個別封止体を得る
工程では、回転ブレードにより各半導体素子単位に分割
することを特徴とする請求項1に記載の半導体装置の製
造方法。
3. A plurality of semiconductor elements are mounted on an upper surface of a wiring substrate having a wiring electrode on at least an upper surface and external electrodes electrically connected to the wiring electrode on a lower surface, and a substantially entire surface of the upper surface is formed of a sealing resin. In the step of cutting the wiring substrate for each semiconductor element unit to obtain an individually sealed body with respect to the sealed body sealed by the above, dividing into each semiconductor element unit by a rotating blade. 2. The method for manufacturing a semiconductor device according to item 1.
【請求項4】 少なくとも上面に配線電極と底面に前記
配線電極と電気的に接続した外部電極を有した配線基板
の上面に複数の半導体素子が搭載され、その上面に実質
的全面が封止樹脂で封止された封止体に対して、各半導
体素子単位に前記配線基板を切断して個別封止体を得る
工程において、配線基板は1枚の基板上に複数の半導体
素子が搭載でき、個々の半導体素子ごとに切断すること
ができる配線基板であることを特徴とする請求項1に記
載の半導体装置の製造方法。
4. A plurality of semiconductor elements are mounted on an upper surface of a wiring substrate having a wiring electrode on at least an upper surface and external electrodes electrically connected to the wiring electrode on a lower surface, and a substantially entire surface is formed of a sealing resin. In the step of cutting the wiring board for each semiconductor element unit to obtain an individual sealed body for the sealed body sealed with, the wiring board can mount a plurality of semiconductor elements on one substrate, 2. The method for manufacturing a semiconductor device according to claim 1, wherein the wiring substrate can be cut for each individual semiconductor element.
【請求項5】 半導体素子の電極に形成されたバンプと
配線基板の配線電極とを電気的に接続することを特徴と
する請求項1に記載の半導体装置の製造方法。
5. The method according to claim 1, wherein the bumps formed on the electrodes of the semiconductor element are electrically connected to the wiring electrodes of the wiring board.
【請求項6】 半導体素子の裏面と配線基板の上面とを
接着し、前記半導体素子の電極と前記配線基板の配線電
極とを金属細線で電気的に接続することを特徴とする請
求項1に記載の半導体装置の製造方法。
6. The semiconductor device according to claim 1, wherein a back surface of the semiconductor element and an upper surface of the wiring board are bonded to each other, and an electrode of the semiconductor element and a wiring electrode of the wiring board are electrically connected by a thin metal wire. The manufacturing method of the semiconductor device described in the above.
【請求項7】 複数の半導体素子がその面内に形成され
た半導体ウェハーの上面に樹脂が形成され、前記樹脂の
面に前記複数の半導体素子と各々接続した外部電極が設
けられた封止体に対して、各半導体素子単位に前記半導
体ウェハーを切断して個別封止体を得る工程と、前記個
別封止体の外部電極側を上にして複数個配列する工程
と、前記配列された複数の個別封止体の外部電極上に各
々同時にボール電極を搭載する工程とよりなることを特
徴とする半導体装置の製造方法。
7. A sealing body in which a resin is formed on an upper surface of a semiconductor wafer in which a plurality of semiconductor elements are formed in its surface, and an external electrode connected to each of the plurality of semiconductor elements is provided on the surface of the resin. A step of cutting the semiconductor wafer for each semiconductor element unit to obtain an individual sealing body, a step of arranging a plurality of the individual sealing bodies with the external electrode side facing up, Mounting a ball electrode on each of the external electrodes of the individual sealing body at the same time.
【請求項8】 複数の半導体素子がその面内に形成され
た半導体ウェハーの上面に樹脂が形成され、前記樹脂の
面に前記複数の半導体素子と各々接続した外部電極が設
けられた封止体に対して、各半導体素子単位に前記半導
体ウェハーを切断して個別封止体を得る工程において、
前記封止体は上方または下方に反っている封止体であ
り、個別封止体に切断することによりその反りを減少さ
せることを特徴とする請求項7に記載の半導体装置の製
造方法。
8. A sealing body in which a resin is formed on an upper surface of a semiconductor wafer in which a plurality of semiconductor elements are formed in the plane, and external electrodes respectively connected to the plurality of semiconductor elements are provided on the surface of the resin. In contrast, in the step of cutting the semiconductor wafer for each semiconductor element unit to obtain an individual sealing body,
The method according to claim 7, wherein the sealing body is a sealing body that is warped upward or downward, and the warpage is reduced by cutting the sealing body into individual sealing bodies.
【請求項9】 複数のボール電極を吸着穴で吸着して搬
送するボール電極搭載ヘッドと、少なくとも上面に配線
電極と底面に前記配線電極と電気的に接続した外部電極
を有した配線基板の上面に半導体素子が搭載され、その
上面が封止樹脂で封止された各半導体素子単位の個別封
止体の複数個を配列するための搬送治具とからなる半導
体装置の製造装置であって、前記複数のボール電極と前
記配線基板の外部電極とを位置合わせし、前記配列され
た複数の個別封止体の裏面の外部電極上に各々同時にボ
ール電極を搭載することを特徴とする半導体装置の製造
装置。
9. A top surface of a wiring board having a ball electrode mounting head for sucking and transporting a plurality of ball electrodes by suction holes, and a wiring electrode on at least an upper surface and an external electrode electrically connected to the wiring electrode on a bottom surface. A semiconductor device is mounted on a semiconductor device, and the upper surface thereof is a semiconductor device manufacturing apparatus comprising a transport jig for arranging a plurality of individual sealing bodies for each semiconductor element unit sealed with a sealing resin, The semiconductor device according to claim 1, wherein the plurality of ball electrodes and the external electrodes of the wiring board are aligned with each other, and the ball electrodes are simultaneously mounted on the external electrodes on the back surface of the arranged plurality of individual sealing bodies. manufacturing device.
【請求項10】 搬送治具の上面に耐熱性粘着テープを
設置し、前記耐熱性粘着テープ上に個別封止体を搭載す
ることを特徴とする請求項9に記載の半導体装置の製造
装置。
10. The apparatus for manufacturing a semiconductor device according to claim 9, wherein a heat-resistant adhesive tape is provided on an upper surface of the transport jig, and an individual sealing body is mounted on the heat-resistant adhesive tape.
JP2001047866A 2001-02-23 2001-02-23 Method and apparatus for manufacturing semiconductor device Pending JP2002252237A (en)

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Application Number Priority Date Filing Date Title
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Publications (1)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004119552A (en) * 2002-09-25 2004-04-15 Matsushita Electric Works Ltd Semiconductor device and its manufacturing method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004119552A (en) * 2002-09-25 2004-04-15 Matsushita Electric Works Ltd Semiconductor device and its manufacturing method

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