JP2002251894A - Serial memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce required chip area and to decrease a peak current in operation by reducing the number of required sense amplifiers in a serial memory device in which an address is specified for each word unit. SOLUTION: A memory cell of (n) bits in which an address is specified for each plurality of (n) bits unit is sectioned for each n/k (k:2 or more), selected successively every n/k bits, output data of the selected memory cell of the n/k are discriminated by sense amplifiers of n/k pieces, and outputted in serial as read-out data.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a serial memory device having a memory cell array in which a storage unit is addressed in units of a plurality of n bits, such as a word unit.

[0002]

2. Description of the Related Art In a serial memory device such as a video memory, a data string (for example, a word unit) composed of a plurality of bits is simultaneously read out from a memory cell array, stored in a register group, and then stored in a register group. Data is read out serially while being sequentially shifted. When data is input serially, for example, one word is accumulated and then the data is written collectively in word units.

FIG. 6 shows an EEPR as a memory cell array.
FIG. 2 is a diagram illustrating a configuration of a conventional serial memory device using a nonvolatile memory made of an OM.

[0006] In FIG. 6, a memory cell array 61 includes:
For a data group in which one word is 8 bits, memory cells of 32 rows and 4 columns (1 column is 8 bits) are formed.
Each memory cell is composed of a nonvolatile memory such as an EEPROM. The decoder 62 selects one of the 32 rows by the word line WL, and the selector 63 selects one of the four columns by the column selection signal YA. A specific address is specified by the row and column selected by the decoder 62 and the selector 63. Therefore, the address is specified in word units (8-bit units).

When writing data, the data line DL
Data of one word is supplied to 0 to DL7, and the data is written to a memory cell group of a designated address. On the other hand, at the time of data reading, data lines DL0 to DL0 corresponding to the storage data of the memory cell group of the designated address.
The state of L7, that is, the electric signal is determined by the sense amplifier 64 provided for each data line, and stored in the shift register 65. Thereafter, the shift register 6
5, the output data DO is serially output sequentially in accordance with the serial clock.

As described above, in the conventional serial memory device, the read operation is performed in word units similarly to the write operation. In particular, in the case of a non-volatile memory such as an EEPROM, since the time required for writing is long (for example, about 10 ms), it is necessary to perform batch processing in word units. Processing is performed.

[0007]

However, in order to perform the read operation collectively in units of words, a sense amplifier of the number of bits is used, so that the required area of the sense amplifier and the data line for the number of bits increases. This has been a factor of increasing the chip area of the serial memory device.

Therefore, the present invention reduces the required chip area and reduces the peak current during operation by reducing the required number of sense amplifiers in a serial memory device addressed in word units. The purpose is to:

[0009]

According to a first aspect of the present invention, there is provided a serial memory device, comprising: a memory cell array addressed in units of a plurality of n bits; and n / k (where k is an integer) the memory cells of the addressed n bits. ), And n / k sense amplifiers for judging output data of the n / k memory cells selected by the selecting means. And a register which receives the outputs of these sense amplifiers in parallel and serially outputs the data as read data.

According to the serial memory device of the first aspect, an n-bit unit (eg, 1 word; 8 bits, 16 bits)
Bit), the memory state is determined for each group, and the number of sense amplifiers for determination is reduced to one for k, and the data for that is reduced. The number of lines is likewise reduced. Therefore, the area of the LSI chip constituting this serial memory device can be reduced, and the peak current during operation can be reduced.

According to a second aspect of the present invention, in the serial memory device, a memory cell array 11 addressed by a plurality of n bits in units of a row selection signal and a column selection signal, and a row selection means for supplying the row selection signal to the memory cell array 12
A first selection unit 13 for selecting, by the column selection signal, an n-bit memory cell addressed from the row selected by the row selection signal, and an n-bit memory cell selected by the first selection unit 13 The memory cell is n / k (where k is 2
And n / k bits for sequentially selecting n / k bits at a time, and n / k number of output data of the n / k memory cells selected by the second selection means. A sense amplifier 17, a register 18 which receives the outputs of these sense amplifiers 17 in parallel and serially outputs them as read data, and
N / k-bit input data supplied from the outside is sequentially latched at a position selected by the second selecting means, and n bits for writing data to a designated address of the memory cell array via the first selecting means. And a data holding unit 14.

According to the serial memory device of the second aspect, the same operation and effect as those of the serial memory device of the first aspect can be obtained. Further, with the reduction in the number of sense amplifiers and the number of data lines, data input in n / k bits can be stored in the data holding means 14 and written in n bits at a time. It doesn't take long.

According to a third aspect of the present invention, in the serial memory device, a memory cell array 31 addressed by a plurality of n bits in units of a row selection signal and a column selection signal, and row selection means for supplying the row selection signal to the memory cell array. 32
And an n-bit memory cell addressed from the row selected by the row selection signal is selected by the column selection signal, and the selected n-bit memory cell is set to n / k (where k is 2 or more). ), And selecting means 33 for sequentially selecting n / k bits at a time, and n / k for judging output data of the n / k memory cells selected by the selecting means.
The sense amplifiers 36, a register 37 which receives the outputs of the sense amplifiers 36 in parallel and serially outputs the read data, and n / k-bit input data supplied from the outside via the selection means. J × n-bit page buffer means 34 for sequentially storing data at the positions selected by the selection means and writing data collectively to j (where j is 1 or more) designated addresses of the memory cell array. It is characterized by having.

According to the serial memory device of the third aspect, the same operation and effect as those of the serial memory device of the first aspect can be obtained. Further, with the reduction in the number of sense amplifiers and the number of data lines, data input in n / k bits can be sequentially accumulated in the page buffer means 34 of j × n bits, and j × n bits can be collectively written. Therefore, the write operation to the memory cell array can be shortened.

According to a fourth aspect of the present invention, in the serial memory device according to the first to third aspects, while the read data is serially output from the register,
Next, n / k output data to be output is selected by the selection means or the second selection means, and is determined by the n / k sense amplifiers.

According to the serial memory device of the present invention, while the read data is serially output from the register, the n / k output data to be output next is changed to the n / k output data. Since the determination is made by the sense amplifier, n output data can be serially output continuously without delay.

According to a fifth aspect of the present invention, in the serial memory device of the first to fourth aspects, each memory cell of the memory cell array is an electrically writable / erasable nonvolatile memory (EEPROM). An array source ground line (ASG line) commonly arranged for the n-bit memory cells;
The memory cells of / k bits are characterized by being distributed among the n-bit memory cells with respect to the ASG line.

According to the serial memory device of the fifth aspect, the source potential of the memory cell rises due to the impedance of the wiring (diffusion layer, etc.) and the operating current at the time of data reading between each memory cell and the ASG line. Is reduced.
As a result, the current capability of the memory cell can be made uniform, so that the data read operation can be speeded up and the operational reliability of the sense amplifier can be improved.

[0019]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of a serial memory device according to the present invention.

In the present invention, the memory cell array is addressed in units of a plurality of n bits, and the addressed n-bit memory cells are divided into n / k (where k is 2 or more) and n / k bits Are sequentially selected, and the selected n /
Output data of k memory cells are determined by n / k sense amplifiers. The plurality of n-bit units are usually word units, and 8 bits, 16 bits, 32 bits, etc. are used, and 2, 4, 8, or the like is used as the number of divisions k. Of course, these numerical values are merely examples, and other values may be used.

FIG. 1 shows an EEPR as a memory cell array.
FIG. 2 is a diagram showing a configuration of a serial memory device according to a first embodiment of the present invention using a non-volatile memory composed of an OM, and FIG. 2 is a diagram showing a timing chart at the time of reading. In these figures, the case where n = 8 and k = 2 will be described as an example.

In FIG. 1, a memory cell array 11
A nonvolatile memory such as an EEPROM is used as a memory cell.
It is formed of memory cells in rows and four columns (one column is eight bits). The decoder 12 as a row selecting means selects one of the 32 rows by the word line WL (0; 31), and the first selector 13 outputs a column selection signal YA such as a count signal.
Selects one of the four columns. Decoder 12 and first
A specific address is specified by the row and column selected by the selector 13. Therefore, the address of the memory cell array 11 is specified in word units (8-bit units) regardless of the write operation and the read operation.

The first selector 13 selects a bit line corresponding to the selected word from the bit line BL (0; 31) of the memory cell array 11 and connects it to the intermediate data line DL '(0; 7). . Data latch 14
Is a data holding means for temporarily storing one word of 8-bit data when writing data.

The second selector 15 divides the intermediate data line DL '(0; 7) from the first selector 13 into two groups, and one of the two groups according to a first select signal Y1B and a second select signal Y2B. The group is connected to four data lines DL0 to DL3.

The drivers 16-0 to 16-3 receive 4-bit data which is half of one word (8 bits) at the time of data writing, and supply the data to the data lines DL0 to DL3. The sense amplifiers 17-0 to 17-3 compare the electric signals generated on the data lines DL0 to DL3 with predetermined reference voltages, respectively, and determine whether the data read from the memory cell array 11 is "0" or "1". It is determined whether there is.

The shift register 18 includes a sense amplifier 17
Data from −0 to 17-3 are collectively held, and sequentially output as serial data in response to a serial clock.

The operation at the time of reading data will be described. First, any one of the word lines WL (0; 31) is selected from the decoder 12 in the memory cell array 11, and four columns of the selected one row are connected to the bit line BL (0; 31). Connected to the first selector 13. In the first selector 13, one of the four columns (8 bits) is selected by a column selection signal YA which is sequentially updated by a counter or the like, and the intermediate data line D is selected.
L '. That is, one word of the memory cell array 11 is addressed by the selection of the decoder 12 and the first selector 13.

Next, of the intermediate data lines DL ', four of the first set and four of the second set are connected to the second selector 1.
At 5, the first select signal Y1B and the second select signal Y2B selectively connect to the data lines DL0 to DL3.

As a result, the sense amplifiers 17-0 to 17-
3 is connected to four memory cells of the addressed word in the memory cell array 11 via the second selector 15, the intermediate data line DL ', and the first selector 13.

In this state, as shown in FIG. 2, the sense amplifier EN signal SAEN is set by the read signal (time t1), thereby setting the data lines DL0 to DL0.
3 indicates the level of the electric signal generated by the sense amplifier 1
It is determined in 7-0 to 17-3. The determination result, that is, the read data (D7 to D4) of the first set of four memory cells in the designated word is stored in the shift register 18 by the shift register latch signal SRL at time t2.
To memorize.

The first set of read data (D7 to D4) stored in the shift register 18 is a serial clock S
The data is sequentially read out serially in accordance with CK and output as output data DO.

Here, the first set of read data (D7 to
While D4) is sequentially read out serially, the selection state of the second selector 15 is changed by the second select signal Y2B to the second set of four of the intermediate data lines DL ', and the data lines DL0 to DL0. Connect to DL3. As a result, the sense amplifiers 17-0 to 17-3 are connected to the second selector 1
5, via the intermediate data line DL 'and the first selector 13 to be connected to the second set of four memory cells of the addressed word in the memory cell array 11.

In this state, at time t3, by setting the sense amplifier EN signal SAEN, the level states of the electric signals generated on the data lines DL0 to DL3 are determined by the sense amplifiers 17-0 to 17-3. . The result of the determination, that is, read data (D3 to D0) of the second set of four memory cells in the designated word
Is stored in the shift register 18 by the shift register latch signal SRL at time t4. Therefore, at the same time when the first set of read data (D7 to D4) is completely read from the shift register 18, the read data (D3 to D0) of the second set of four memory cells are newly stored in the shift register 18. It is memorized.

As described above, while the read data (D7 to D4) is serially output from the shift register 18, four (n / k) output data (D / K) to be output next are output.
3 to D0) are determined by four (n / k) sense amplifiers, so that one word (n) of output data can be serially output without delay. Further, the data of the next word can be successively output in the same manner.

Next, the operation at the time of writing data will be described. First, of the one-word data (D7 to D0) to be written, the first set of data (D7 to D
4) is latched by the data latch 14 via the drivers 16-0 to 16-3, the second selector 15 selected to the first state by the first select signal Y1B, and the intermediate data line DL '. Subsequently, a second set of data (D
3 to D0) are latched by the data latch 14 via the drivers 16-0 to 16-3, the second selector 15 selected to the second state by the second select signal Y2B, and the intermediate data line DL '. . As a result, one word of data (D7 to D0) is latched by the data latch 14.

Next, for the memory cell array 11, any one of the word lines WL (0; 31) is selected from the decoder 12 by the decoder 12, while the first selector 13 is turned on by the column selection signal YA. One of the columns is selected, and the write address is selected.
In this state, one word of data (D7 to D0) latched by the data latch 14 is stored in the memory cell array 1
1 is written to the write address 1 via the first selector 13.

As described above, the memory cells selected in word units (8 bits) are divided into two groups, and storage data is determined for each group. Therefore, the number of sense amplifiers for determination is also four. And the number of data lines is similarly reduced. Therefore, L constituting the serial memory device
The chip area of the SI can be reduced, and the peak current during the sensing operation is reduced.

Also, as for the write data, one word (8 bits) is input in two steps, and one word is latched in the data latch. be able to.

FIG. 3 is a diagram showing a configuration of a serial memory device according to a second embodiment of the present invention.

In FIG. 3, the memory cell array 31, decoder 32, drivers 35-0 to 35-3, sense amplifiers 36-0 to 36-3, and shift register 37 are the same as those in FIG. Is omitted.

The selector 33 is the first selector 13 shown in FIG.
And the second selector 15 and the connection between the bit line BL (0; 31) and the data line DL (0; 3) by the column select signal YA, the first select signal Y1B, and the second select signal Y2B. Selectively switch states. That is, the column selection signal YA addresses one of the word units (8 bits) of the memory cell array 31 together with the word line WL (0; 31) from the decoder, and
And the second select signals Y1B and Y2B divide the addressed word into two sets and select one of the sets.

FIG. 4 shows a specific circuit example of the selector 33. FIG. 4 exemplifies a portion corresponding to one of the four columns, and the bit line BL (7: 0) of the column selected by the column selection signal YA further includes the first column.
Alternatively, either the first set of bit lines BL (4 to 7) or the second set of bit lines BL (0 to 3) is changed to the data line DL by the second select signals Y1B and Y2B.
(3; 0). Therefore, as shown in the figure, 8
It is composed of a plurality of MOS transistors, a NOT circuit NOT, and NOR circuits NOR1 and NOR2.

The page buffer 34 has a capacity of one row and four columns of the memory cell array 31 (that is, four words), and has a transfer gate provided therein for input / output control. When writing data to this page buffer 34,
Data supplied from the outside is sequentially stored via the selector 33, and after storing a predetermined number of words (at least better than 4 words), the data is collectively written to a predetermined row of the memory cell array 31.

The operation at the time of reading data shown in FIG. 3 will be described. First, the decoder 3 is added to the memory cell array 31.
2, one of the word lines WL (0; 31) is selected, and the four columns of the selected one row are connected to the bit line BL (0; 31) and connected to the selector 33. Is done. In the selector 33, one of the four columns (8 bits) is selected by a column selection signal YA which is sequentially updated by a counter or the like, whereby one word of the memory cell array 31 is addressed. Then, of the 8 bit line BL of the selected word, four of the first set and four of the second set are:
The data lines DL0 to DL3 are selectively connected by the select signal Y1B and the second select signal Y2B.

As a result, the sense amplifiers 36-0 to 36-
3 is connected to four memory cells in the addressed words of the memory cell array 31 via the selector 33.

In this state, by setting the read signal and the sense amplifier EN signal, the level states of the electric signals generated on the data lines DL0 to DL3 are determined by the sense amplifiers 36-0 to 36-3. You. The determination result, that is, read data (D7 to D4) of the first set of four memory cells in the designated word is
By the shift register latch signal, the shift register 37
To memorize.

The first set of read data (D7 to D4) stored in the shift register 37 is sequentially and serially read according to a serial clock, and output data DO is output.
Is output as

Here, the first set of read data (D7 to
While D4) is sequentially read out serially, the selection state of the selector 33 is connected to the data lines DL0 to DL3 by using the second select signal Y2B. As a result, the sense amplifiers 36-0 to 36-3 are connected to the second set of four memory cells in the addressed words of the memory cell array 31 via the selector 33.

In this state, while the read data (D7 to D4) is serially output from the shift register 37 in the same manner as in the timing chart of FIG. Output data (D3 to D0)
Is determined by four (n / k) sense amplifiers 36-0 to 36-3. As a result, output data of one word (n) can be serially output without delay, and further, data of the next word can be continuously output.

Next, the operation at the time of writing data will be described. First, of the one-word data (D7 to D0) to be written, the first set of data (D7 to D7) is written.
4) are the drivers 35-0 to 35-3 and the column selection signal YA
Is stored in the page buffer 34 via the selector 33 selected to the first state by the first select signal Y1B. Subsequently, the second set of data (D3 to D0) is stored in the page buffer 34 via the selector 33 selected to the second state by the second select signal Y2B. Thus, the first word is stored in the page buffer 34. Subsequently, the second word to the fourth word
Word data is sequentially stored in the page buffer 34 in the same manner as needed.

Next, for the memory cell array 31, one of the word lines WL (0; 31) is selected from the decoder 32, and in this state,
The four words of data stored in the page buffer 34 are written to the write address of the memory cell array 31, that is, the memory cell group corresponding to one selected word line.

Therefore, similarly to the first embodiment,
The chip area of the LSI constituting the serial memory device can be reduced, and the peak current at the time of the sensing operation is reduced.

Since one word (8 bits) is divided into two times and four words are input and stored in the page buffer, a plurality of words are written in the memory cell array 31 addressed in word units. Data can be written collectively.

FIG. 5 is a diagram showing a structure of a memory cell array according to a third embodiment of the present invention. In the memory cell array according to the first and second embodiments described with reference to FIGS. This shows a division method in a case where memory cells for one word (n bits) are divided into k (k is 2 or more) and n / k bits are selected. In this figure, one word is composed of 16 bits (n = 16), and the number of sections is 4 (k
= 4).

In FIG. 5, memory cells MC0 to MC1
Reference numeral 5 includes a select transistor ST and a memory transistor MT connected in series. This memory transistor MT is a known EEPROM (electrically erasable and nonvolatile memory) and has a floating gate and a control gate.

A word line WL is connected to the gate of each select transistor ST of each of the memory cells MC0 to MC15, and a control gate of each memory transistor MT is connected to a sense line via a gate transistor GT driven by the word line WL. SL is connected.

Bit lines BL0 to BL15 are arranged at positions on the line where memory cells MC0 to MC15 are arranged, and are respectively connected to the other ends of select transistors ST. Further, the memory cell MC2 and the bit line BL2
, An array source ground line (ASG line) is arranged between the memory cell MC3 and the bit line BL3,
Another AS is provided between the memory cell MC12 and the bit line BL12 and the memory cell MC13 and the bit line BL13.
G line is arranged.

Then, the other end of the memory transistor MT of each memory cell and the ASG line are electrically connected. Since these interconnections are formed by a diffusion layer due to the structure of the EEPROM, as shown in FIG.
Some resistance will be generated.

The memory cells MC0 to MC0 thus configured
When reading the stored data from the MC 15,
The word line WL is set to H level to turn on the select transistor ST, and a predetermined gate potential is applied from the sense line SL to the control gate of the memory transistor MT. Then, the stored data is read by setting the ASG line to the ground potential and detecting the magnitude of the current I flowing through the bit lines BL0 to BL15 by the sense amplifier.

According to the present invention, in the example of this figure, 1
A word (16 bits) is divided into four sections, data is determined collectively for each section, and the data is read out serially. However, a voltage drop is determined by the resistance R and the read current I between each other. For this reason, when one word is k-divided, for example, simply dividing the word into a predetermined number from the end thereof increases the voltage drop for a specific memory cell and raises the source potential. Ability is reduced,
A sufficient read operation cannot be performed.

In the embodiment shown in FIG. 5, the k cells are arranged so that the memory cells which read the k segments simultaneously with respect to the ASG line are dispersed, and the voltage drop during the reading operation is kept at a predetermined small value. I have. Looking at the division in FIG. 5, the first division is “MC0, MC4, MC8, MC1”.
2 ”and the second category is“ MC1, MC5, MC9, MC1
3 ”and the third category is“ MC2, MC6, MC10, MC1
4 "and the fourth category is" MC3, MC7, MC11, MC1
5 ".

Here, for example, the first division “MC0, MC
4, MC8, MC12 ", a read current I flows as indicated by an arrow in the drawing. In this example, it is shown that the current I flows through all the selected memory cells equally. As is apparent from this example, the current I is dispersed and flows with respect to the ASG line, and the current I is less likely to be superimposed on each resistor R. As a result, the voltage drop at the time of reading data is reduced, and Source voltage rise is reduced.

As described above, by arranging the memory cells and the bit lines of each section so as to be dispersed with respect to the ASG line, the read current I is dispersed and the superposition on each resistor R is reduced. Therefore, the rise of the source potential of the memory cell at the time of data reading can be reduced. This improves the speed of the data read operation and improves the reliability of the sense amplifier operation.

In this figure, two ASG lines are used, but three or more ASG lines may be used, or one ASG line may be used. Of course, the number of bits in one word is not limited to 16 bits, and may be another number of bits.

[0065]

According to the serial memory device of the first aspect, memory cells selected in units of n bits (eg, 1 word; 8 bits, 16 bits, etc.) are divided into k groups,
Since the storage state is determined for each set, the number of sense amplifiers for the determination is reduced to 1 for k, and the number of data lines for that is also reduced. Therefore,
The LSI chip area constituting this serial memory device can be reduced, and the peak current during operation can be reduced.

According to the serial memory device of the second aspect, the same operation and effect as those of the serial memory device of the first aspect can be obtained. In addition, with the reduction in the number of sense amplifiers and the number of data lines, data input in n / k bits can be stored in the data holding means, and n bits can be written at a time. It doesn't take long.

According to the serial memory device of the third aspect, the same operation and effect as the serial memory device of the first aspect can be obtained. Further, with the reduction in the number of sense amplifiers and the number of data lines, data input in n / k bits can be sequentially accumulated in a page buffer means of j × n bits, and j × n bits can be collectively written. In addition, the write operation to the memory cell array can be shortened.

According to the serial memory device of the present invention, while the read data is serially output from the register, the n / k output data to be output next is supplied to the n / k sense data. Since the determination is made by the amplifier, n output data can be serially output continuously without delay.

According to the serial memory device of the fifth aspect, an increase in the source potential of the memory cell between each memory cell and the ASG line due to the impedance of the wiring (diffusion layer or the like) and the operating current at the time of data reading. Reduced. Therefore, the speed of the data read operation can be increased, and the operational reliability of the sense amplifier can be improved.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a serial memory device according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a timing chart at the time of reading.

FIG. 3 is a configuration diagram of a serial memory device according to a second embodiment of the present invention.

FIG. 4 is a diagram showing a specific circuit example of a selector.

FIG. 5 is a diagram showing a configuration of a memory cell array according to a third embodiment of the present invention.

FIG. 6 is a configuration diagram of a conventional serial memory device.

[Explanation of symbols]

 11,31 memory cell array 12,32 decoder 13,15,33 selector 14 data latch 34 page buffer 16,35 driver 17,36 sense amplifier 18,37 shift register WL word line BL bit line DL data line ASG array source ground DO output Data YA column select signal Y1B, Y2B select signal

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Noriaki Katsuhara 21 Ryozaki-cho, Saiin, Ukyo-ku, Kyoto F-term in ROHM Co., Ltd. (Reference) 5B025 AA02 AC01 AD04 AD05 AE00 AE05 AE08

Claims (5)

[Claims] A memory cell array addressed in units of a plurality of n bits;
(Where k is equal to or greater than 2) and selecting means for sequentially selecting n / k bits at a time, and n / k number of output data of the n / k memory cells selected by the selecting means And a register that receives outputs of the sense amplifiers in parallel and serially outputs the data as read data. 2. A memory cell array addressed by a plurality of n bits in units of a row selection signal and a column selection signal; row selection means for supplying the row selection signal to the memory cell array; A first selection unit for selecting an n-bit memory cell addressed from a row selected by a row selection signal; and n / k (where k is an integer) the n-bit memory cell selected by the first selection unit. (2 or more), and n / k bits are sequentially selected and n / k bits are sequentially selected. N / k number of output data of the n / k memory cells selected by the second selection means are determined. A sense amplifier, a register that receives outputs of these sense amplifiers in parallel and serially outputs the data as read data, and n / k externally supplied through the second selection means.
And n-bit data holding means for sequentially latching bit input data at a position selected by the second selection means and writing data to a designated address of the memory cell array via the first selection means. A serial memory device, characterized in that: 3. A memory cell array addressed by a plurality of n-bit units by a row selection signal and a column selection signal; a row selection unit for supplying the row selection signal to the memory cell array; An n-bit memory cell addressed from the row selected by the row selection signal is selected, and the selected n-bit memory cell is set to n / k (however,
(k is 2 or more), and selecting means for sequentially selecting n / k bits at a time, and n / k sense amplifiers for determining output data of the n / k memory cells selected by the selecting means And a register that receives the outputs of these sense amplifiers in parallel and serially outputs them as read data; and that the selection means sequentially selects n / k-bit input data supplied from outside via the selection means. In the memory cell array (where j is 1
And a page buffer means of j × n bits for writing data collectively to the specified address. 4. The serial memory device according to claim 1, wherein n / k pieces of output data to be output next are selected by said selection means or said first output means while serially outputting read data from said register. A serial memory device, wherein the serial memory device is selected by two selecting means and is determined by the n / k sense amplifiers. 5. The serial memory device according to claim 1, wherein each memory cell of said memory cell array is electrically writable / erasable nonvolatile memory (EEPRO).
M) and an array source ground line (ASG) commonly arranged for the n-bit memory cells.
A serial memory device, wherein the n / k-bit memory cells are distributed among the n-bit memory cells with respect to the ASG line.