JP2002246331A - Manufacturing method of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve Co silicide reaction in a region where a Co silicide film is hard to be formed, since As and F have been injected. SOLUTION: By injecting P ions into a region, where the Co silicide film is hard to be formed since various ions, such as at least an N+ diffusion layer formed on a silicon substrate in a transistor, are injected, the Co silicide is formed easily. When P ions are to be injected, a region other than a region, such as the surface of the N+ diffusion layer where the Co silicide film is hard to be formed is selectively masked by a resist, and P ions are merely injected into the region, where the Co silicide film is hard to be formed. For example, an oxide film 2 of the transistor, and the surface of a gate electrode 5 are masked by resist 7, and P ions are injected into drain and source layers 3 and 4.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming a Co silicide film uniformly on a MOSFET (hereinafter referred to as a transistor).

[0002]

2. Description of the Related Art An N-type or P-type doped polycrystalline silicon film is used for a gate electrode of a transistor.
Recently, a silicide structure in which a Ti silicide film (TiSi ₂ ) or a Co silicide (CoSi ₂ ) film is laminated on the surface of polycrystalline silicon is used to reduce the resistance of the gate electrode.

[0003] A Ti silicide film (TiSi ₂ ) or Co silicide (CoSi ₂ ) is simultaneously formed on a source / drain region. Co silicide is T
Compared with i-silicide, they are excellent in heat resistance and in that there is no increase in resistance due to the thin wire effect, and utilizing such characteristics, Co silicide films are widely used in logic-based semiconductor devices.

[0004]

However, the Co silicide film has various problems regarding its formation. One of the problems is that it is difficult to form a uniform Co silicide film. This is because the Co silicide film is affected by the ion species and the amount of ions implanted into the silicon substrate, and as a result, the silicide reaction may be inhibited.

[0005] For example, the method of implanting As as an ion species to be implanted into the N ⁺ diffusion layer is a method which is currently widely used for forming a shallow junction.
Is known to inhibit the silicide reaction of F is an ion species implanted as a countermeasure for slow trapping, and it has been found that a similar phenomenon occurs with F.

Therefore, the problem of how the Co silicide reaction can be easily formed is a problem of C.
oThis is a major issue in the silicide process.

By the way, there is a problem that a silicon reaction inhibition layer for Co is formed on the surfaces of the gate, source and drain by various ion implantations. If such a silicon reaction inhibition layer for Co is formed, it becomes difficult to perform silicidation itself. Therefore, such a reaction inhibition layer must be removed in advance. At present, a technique for removing such a reaction inhibition layer using wet etching or dry etching has been established (see Japanese Patent No. 3104689 (Prior art 1)).

An object of the present invention is to provide a method for improving a Co silicidation reaction in a region where a Co silicide film is hardly formed because As or F is implanted.

[0009]

In order to achieve the above object, P ions are implanted into at least a region where a Co silicide film is difficult to form, such as an N ⁺ diffusion layer, formed on a silicon substrate in a transistor. Is formed easily.

The implantation of P ions reduces the suppression of the Co silicide reaction due to As implanted in the region where the silicide reaction occurs.

Further, P ions are implanted into the entire surface of the silicon substrate.

Also, a region other than the region where the Co silicide film is difficult to form, such as on the N ⁺ diffusion layer, is selectively masked with a resist, and the P region is formed only in the region where the Co silicide film is difficult to form.
This is for implanting ions.

Further, the oxide film of the transistor and the surface of the gate electrode are masked with a resist, and P ions are implanted into the drain layer and the source layer.

The appropriate amount of P ions to be implanted is determined by the amount of As or F implanted.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to the drawings. Figure 1 shows a transistor (MOSFET)
The basic structure of is shown. As shown in FIG. 1, the transistor has a source layer 4 and a drain layer 3 near the surface of the silicon substrate 1, and further has a gate insulating film on the surface of the silicon substrate 1 between the source layer 4 and the drain layer 3. 9, a gate electrode 5 made of polycrystalline silicon is formed thereon.

Transistors include Nch and Pch, and various ions are implanted to form a channel layer.
In the transistor, it is necessary to reduce the layer resistance of the diffusion layer such as the source layer 4 and the drain layer 3 and the resistance of the gate electrode 5 in order to increase the operation speed.

For this purpose, a silicide film 10, which is a low-resistance film, is formed on the source layer 4, the diffusion layer of the drain layer 3, and the gate electrode 5, as shown in FIG. For the silicide film 10, Ti silicide and Co silicide are mainly used, and Co silicide is superior to Ti silicide in terms of its heat resistance and no increase in resistance due to the thin wire effect. It is as follows. FIG. 2 shows an example in which a Co silicide film 10 is formed as a silicide film.

As shown in FIG. 1, the Co silicide film 10 is formed by performing Co sputtering on the entire surface of the silicon substrate 1 and annealing the formed Co film 8 as a silicide reaction process. That is, by performing Co sputtering, Co and Si react on the silicon substrate 1 and silicidation occurs.

However, since the Co of the Co silicide film 10 and the oxide film do not react on the oxide film 2 separating the elements of the transistor, even if the Co film 8 is formed on the entire surface of the silicon substrate 1, A source layer 4, a drain layer 3,
Only on the gate electrode 5, Co reacts with Si to be selectively converted into Co silicide (CoSi ₂ ).

After the annealing process, a wet process is performed.
By the wet process, the Co film 8 in the non-silicided region is removed by etching, and the Co silicide remains in the silicided region without being etched. Therefore, only in a predetermined region, in this case,
The Co silicide film 10 is selectively formed only on the source layer 4, the drain layer 3, and the gate electrode 5.

By the way, a considerable amount of various ion species is implanted in a region where a silicidation reaction of a transistor occurs, such as on an N ⁺ diffusion layer or a scribe line.
For this reason, in each region, a region where it is difficult to form a Co silicide is formed, and in a region where a Co silicide film is not easily formed, the generation of the Co silicide film becomes non-uniform.

In particular, in recent years, the miniaturization of transistors has progressed, and the miniaturization of gate length, width, and diffusion layer has progressed. Therefore, the necessity of forming a channel layer in a shallow region even in a junction region has increased. ^{+ In the} diffusion layer, heavy atoms As
Are mainly used.

In fact, this heavy As inhibits the Co silicide reaction. Conversely, using As, N ⁺
In order to form a diffusion layer, a method of uniformly reacting the Co silicide reaction is required. Therefore, in the present invention, as a method of uniformly reacting the Co silicide reaction, P ions are implanted into a region where the Co silicide film is difficult to be formed, the suppression of the Co silicide reaction is reduced by As, and the uniform silicide film is easily formed. Is formed.

In the present invention, it has been experimentally found that the effect of implanting a P ion at a dose of 3E14 atoms / cm ² or more at an implantation energy of about 10 keV is recognized.

Of course, if the amount of P ions implanted is too large, the transistor characteristics will change, so it is natural that the P ion implantation region and the amount of implantation must be confirmed for the actual device. If As is 6E15at
oms / cm ² or less, P is 3E14a
Even when not implanting more than toms / cm ² ,
It is considered that the formation failure of Si does not occur. That is,
This means that an appropriate amount of P to be implanted must be determined based on the amount of As or F to be implanted.

FIG. 3 shows that a diffusion layer, a field, a gate electrode and the like are formed on a silicon substrate, and a gate electrode 5, a drain layer 4, a source layer 3 and an oxide film 2 are included in the process of forming a transistor. 1 shows an example of a method of implanting P ions at a level that does not cause a problem in the characteristics of the transistor. According to this method, the gate electrode 5, the drain layer 4, the source layer 3, and the oxide film 2
The P injection layer 8 is formed.

Further, FIG. 4, as on the ^{N +} diffusion layer Co
Except for the region where Si ₂ is not easily formed, that is, the oxide film 2,
An example of a method of implanting P ions into the drain layer 3 and the source layer 4 by masking the surface of the gate electrode 5 with a PR (resist) 7 is shown. According to this method, the P injection layer 8 is formed only on the drain layer 3 and the source layer 4.

As described above, by selectively implanting P ions only in the entire surface of the silicon substrate 1 or in a region where a Co silicide film (CoSi ₂ ) is not easily formed,
In a silicidation process performed in a later step, a silicide reaction is promoted, and as shown in FIG. 2, formation of a region of the drain layer 3, the source layer 4, and the gate electrode 5, excluding the oxide film 2, particularly a Co silicide film is not performed. A uniform Co silicide film 10 is formed on the diffusion layer of the drain layer 3 and the source layer 4 which is likely to be uniform
Is formed.

A method of implanting P ions into the entire surface of the silicon substrate 1 shown in FIG. 3 and a method of selectively implanting P ions only in regions where CoSi ₂ is difficult to form by masking with PR7 as shown in FIG. In comparison with the method, the latter method does not include P ions even in a region where CoSi ₂ is easily formed, and thus can be said to be superior in performance to the former method. However, the latter method requires an extra masking step by PR, and is disadvantageous in terms of TAT and manufacturing cost as compared with the former method. The choice between the former method and the latter method is a matter to be determined in consideration of the degree of performance degradation due to P ion implantation and the manufacturing cost.

[0030]

Examples of the present invention will be described below. FIG.
Is deposited on a silicon substrate implanted with 6E15 atoms / cm ² , and the formation of silicide is observed by dark field observation with an optical microscope. At the level where P is not injected, FIG.
Many bright spots are observed as in (a). C in the bright spot
Since no o-silicide is formed, a step is generated, which is observed as a bright spot.

FIG. 5B shows an implantation energy of 10 ke.
V, when P was implanted at a dose of 1E14 atoms / cm ² , as can be seen at a glance, many bright spots are still observed. FIG. 5C shows an implantation energy 1
This is the case where P is implanted at 0 keV and at a dose of 3E14 atoms / cm ² . The occurrence of bright spots is considerably reduced as compared with FIG. 5 (b), and it can be seen that the formation defect of Co silicide hardly causes a problem in practical use. In an actual device, it is probably desirable to have no bright spot. The presence or absence of a CoSi formation defect is confirmed by confirming with an actual device.

FIG. 5D shows an implantation energy of 10 ke.
FIG. 5E shows the case where P is implanted at a V and dose of 5E14 atoms / cm ² , and FIG. 5E shows the case where P is implanted at an implant energy of 10 keV and a dose of 7E14 atoms / cm ² . In each case, almost no bright spots are generated on the film
unacceptable. From the above results, the P ion was 10 keV
Dose of 3E14 atoms /
It can be seen that uniform Co silicide is easily formed by injecting cm ² or more into the Co film.

As described above, in the embodiment, As is set to 6E15
An example in which atoms / cm ^{2 are} injected is shown. The above injection amount is based on the actual device, but the injection amount of As varies depending on the device. In other words, it is necessary to determine an appropriate P injection amount based on the injection amount of As, F, or the like. In this case, it should be noted that it is necessary to determine the characteristics such as Vt and the region where there is no problem of defective CoSi formation.

In a real device, for example, As is 4E
P is 1E1 when implanted at 15 atoms / cm ^2.
5 atoms / cm ^{2 is} implanted. In this way, in practice, devices are mass-produced without any problem with device characteristics and CoSi formation defects.

[0035]

As described above, according to the present invention, N
By implanting P ions into at least a region where a Co silicide film is unlikely to be formed, such as on the ⁺ diffusion layer, to such an extent that the characteristics of the transistor are not affected, a silicide reaction caused by the use of heavy atoms As or the like is inhibited. This has the effect of solving the problem described above and easily forming a Co silicide film.

[Brief description of the drawings]

FIG. 1 is a diagram showing a state in which a Co film is formed on the entire surface of a silicon substrate.

FIG. 2 is a diagram showing a state in which Si reacts with Co to form a Co silicide film on a drain layer, a source layer, and a gate electrode.

FIG. 3 is a diagram showing a situation where P ions are implanted into the entire surface of a silicon substrate.

FIG. 4 is a diagram showing a situation in which the surface of an oxide film and a gate electrode is masked with a resist, and P ions are implanted into a drain layer and a source layer.

FIG. 5 (a) shows Co at a level where P ions are not implanted.
Micrographs showing the formation of silicide, (b)-
(E) is a photomicrograph showing the formation state of Co silicide when the implantation energy of P ions is gradually increased.

[Explanation of symbols]

 Reference Signs List 1 silicon substrate 2 oxide film 3 drain layer 4 source layer 5 gate electrode 6 Co film 7 PR (resist) 8 P ion implantation layer 9 gate insulating film 10 Co silicide film

Continued on the front page F-term (reference) 4M104 AA01 BB01 BB20 CC01 DD02 DD26 DD78 DD84 FF14 GG09 GG14 5F140 AA10 BA01 BF04 BF11 BF18 BF38 BG08 BG34 BG43 BG45 BH21 BJ01 BJ08 BK13 BK24 CF39 BK34 CF39

Claims (6)

[Claims] 1. A method of forming a Co silicide by implanting P ions into a region where formation of a Co silicide film is difficult, such as at least an N ⁺ diffusion layer, formed on a silicon substrate in a transistor. A method for manufacturing a semiconductor device. 2. The method according to claim 1, wherein the implantation of the P ions reduces the suppression of the Co silicide reaction due to As implanted in the region where the silicide reaction is performed.
13. The method for manufacturing a semiconductor device according to item 5. 3. The method according to claim 1, wherein P ions are implanted into the entire surface of the silicon substrate. 4. A method of selectively masking a region other than a region where a Co silicide film is difficult to form as with an N ⁺ diffusion layer with a resist, and implanting P ions only into a region where a Co silicide film is difficult to form. The method of manufacturing a semiconductor device according to claim 1. 5. The method of manufacturing a semiconductor device according to claim 3, wherein the oxide film of the transistor and the surface of the gate electrode are masked with a resist, and P ions are implanted into the drain layer and the source layer. 6. The method of manufacturing a semiconductor device according to claim 1, wherein an appropriate amount of P ions is determined by an amount of As or F to be implanted.