JP2002237784A - Optical power level equalizing circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To stably maintain an optical output level with wide input dynamic range by enabling not only attenuation but an amplifying of an optical signal in an optical power level equalizing circuit. SOLUTION: The optical power level equalizing circuit is provided with a power controlled semiconductor optical amplification element 6 to amplify/ attenuate the optical signal according to a driving current, a branching circuit 7 to be connected with a rear stage or a front stage of the semiconductor optical amplification element and to branch the optical signal, a photoelectric converting circuit 8 to convert the branched optical signal into an electric signal, a signal level detecting circuit 9 to detect a voltage level of the electric signal, to compare the detected voltage level with the reference level voltage and to output a voltage signal to act so that the driving current is reduced when the voltage level is higher than the reference level voltage and that the driving current is increased when the voltage level is lower than the reference level voltage and a voltage/current converting circuit 10 to convert the outputted voltage signal into the driving current and to feed the driving current back to the semiconductor optical amplification element 6.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an optical power level equalizing circuit used for controlling the power level of an optical signal in an optical communication network or the like.

[0002]

2. Description of the Related Art In an optical communication network, power level control of an optical signal is a very important technique for adjusting and optimizing a level diagram of the optical network. In particular, in the large-capacity optical communication network system using the wavelength division multiplexing technology (WDM) of the optical signal, the power level control is used to unify the levels of a plurality of wavelength signals or to control an optical circuit having a small input dynamic range. This is an indispensable technology for level adjustment, etc., for taking an interface.

As a method for realizing such optical power level equalization, a configuration using a variable optical attenuation element has been proposed.

FIG. 1 shows a configuration of a conventional optical level control circuit using an optical signal variable attenuator (a device having this configuration has already been commercialized. Product name: Variable)
Optical Attenuators, Model: TVA08INMSS, Manufacturer: N
TT Electronics Co., Ltd.). Here, 1 is an optical fiber for transmitting an optical signal, 2 is a variable attenuation element, and 3 is a heating / cooling element for controlling the variable attenuation element of the variable attenuation element 2. Reference numeral 4 denotes a temperature control circuit for controlling the heating / cooling element 3, which is constituted by an electronic circuit. Reference numeral 5 denotes a control terminal for electrically controlling the temperature of the variable attenuation element 2 via the temperature control circuit 4 and the heating / cooling element 3.

The operation of this circuit will be described. The temperature of the variable attenuation element 2 is controlled by the control voltage applied to the control terminal 5, and the amount of attenuation between the input and output of the variable attenuation element 2 is controlled. As the variable attenuating element 2, an element having a thermo-optical effect is generally used. The refractive index and the absorption coefficient of light change with a change in temperature, and the amount of attenuation between the input and output terminals of an optical signal can be changed.

FIG. 2 shows a general attenuation characteristic between the temperature of the variable attenuation element 2 and an input / output terminal of an optical signal. By controlling the temperature of the variable attenuation element 2 (power injected into the control terminal 5), it is possible to generally provide an attenuation variable width of about 20 dB. Therefore, this optical level control circuit can be applied to level equalization of an optical signal by adjusting the voltage of the control terminal 5.

However, in the configuration using the variable attenuation element 2, as shown in FIG. 2, the equalization operation by amplification cannot be performed only by the attenuation operation. Therefore, it is necessary to add another light amplifying circuit to secure the light output level. In addition, since the thermal control is performed as described above, the response speed is slow, and stabilization of the optical output level requires a time on the order of milliseconds or more. Further, there is a point that power consumption by heat control is large.

[0008]

As described above,
A conventional optical power level equalizing circuit using a variable attenuation element can only attenuate an optical signal for level equalization, has a slow response time, and consumes large power. There is a problem that optimization of the level diagram of the network system, simplification of the device, reduction of power consumption, and the like are restricted.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and an object of the present invention is to enable not only attenuation of an optical signal but also equalization by amplification.
Provide an optical power level equalization circuit that enables control by electricity instead of heat control, reduces power consumption during attenuation operation, ensures a wide input dynamic range, and can automatically control output level stabilization. Is to do.

[0010]

According to a first aspect of the present invention, there is provided an optical power level equalizing circuit comprising: a current control type semiconductor optical amplifying element for amplifying and attenuating an optical signal according to a driving current; A branch circuit that is connected to a subsequent stage or a previous stage of the semiconductor optical amplifying element to branch an optical signal, and when the optical signal level branched by the branch circuit is low, the optical signal level is increased so that high gain operation is performed. A control circuit for controlling the drive current of the semiconductor optical amplifying element so as to perform a low gain or an attenuating operation when it is large.

Here, the control circuit includes an optical / electrical conversion circuit for converting the optical signal branched by the branching circuit into an electric signal, and detects a voltage level of the electric signal converted by the optical / electrical conversion circuit. Then, comparing the detected voltage level with the reference level voltage, if the voltage level is lower than the reference level voltage so that the drive current decreases when the voltage level is higher than the reference level voltage Is a signal level detection circuit that outputs a voltage signal acting to increase the drive current, converts the voltage signal output from the signal level detection circuit into a current signal, and uses the current signal as the drive current as the semiconductor A voltage / current conversion circuit that feeds back to the optical amplifying element.

The optical / electrical conversion circuit includes a photodiode for converting an optical signal into a current signal, and a current / voltage conversion circuit comprising a resistor and an amplifier for converting an output current signal of the photodiode into a voltage signal. By having an amplifier circuit and a capacitance for integrating the voltage signal and detecting an average value, a DC voltage signal is output as a detection result of the average value of the signal level. A differential-input amplifier circuit that compares the DC voltage signal of the conversion circuit with a reference level voltage and outputs the comparison result as an output voltage, wherein the voltage / current conversion circuit includes a driving current setting resistor; A differential input amplifier circuit in which one input port is connected to the resistor and the other input port is connected to the output voltage of the signal level detection circuit; and the base potential is controlled by the output voltage of the amplifier. The combination circuit of a current drive transistor, can be characterized by converting the output voltage of the signal level detection circuit to the driving current.

Further, the control circuit includes an optical / electrical conversion circuit for converting the optical signal branched by the branching circuit into an electric signal, and a peak value of a signal waveform of the electric signal converted by the optical / electrical conversion circuit. And a peak value detection circuit that outputs the detected peak voltage level, and compares the peak voltage level output from the peak value detection circuit with a reference level voltage, so that the current peak pressure level is equal to the reference level voltage. A signal level detection circuit that outputs a voltage signal acting to increase the drive current when the peak voltage level is smaller than the reference level voltage, so that the drive current decreases when the level is larger than the reference level voltage; A voltage / current conversion circuit that converts a voltage signal output from the signal level detection circuit into a current signal and feeds back the current signal as the drive current to the semiconductor optical amplifier. It can be characterized Rukoto.

The optical / electrical conversion circuit includes a photodiode for converting an optical signal into a current signal, a resistor and an amplifier for converting an output current signal of the photodiode into a voltage signal, and an amplifier. An amplification circuit;
The peak value detection circuit includes a differential input amplifier for detecting a signal level of an electric signal converted by the optical / electrical conversion circuit, a diode connected to a stage subsequent to the amplifier, and a capacitor connected to a stage subsequent to the diode. And a resistor for setting a holding time of a peak value voltage. When the signal level is High, the diode is turned on, charge is accumulated in the capacitor, and when the signal level is Low, the diode is turned off. Is turned off, the peak value voltage is held by the electric charge stored in the capacitor, the signal level detection circuit compares the peak value voltage signal of the peak value detection circuit with a reference level voltage, A differential input amplifier circuit for outputting a comparison result as an output voltage, wherein the voltage / current conversion circuit includes a driving current setting resistor, and one of the input ports connected to the resistor for setting the signal. The signal level detection circuit is formed by a combination circuit of a differential input amplifier circuit connected to the other input port to the output voltage of the level detection circuit, and a current driving transistor whose base potential is controlled by the output voltage of the amplifier. Is converted into the drive current.

In addition, a programmable control circuit is connected to the signal level detection circuit in place of the signal level detection circuit. The programmable control circuit includes a drive current, a gain-attenuation characteristic relationship, a wavelength, By setting necessary conditions such as dependence and polarization dependence in advance,
It is possible to execute a highly stable optical power level equalizing operation.

The programmable control circuit stores a drive current of the semiconductor optical amplifying element and a gain / attenuation characteristic relationship in advance, and converts an analog level signal from the optical / electrical conversion circuit into a digital signal. An analog / digital conversion circuit, a digital operation control circuit for comparing the level of a digital signal output from the analog / digital conversion circuit with information stored in the memory, calculating and outputting an optimum control voltage signal, and A digital / analog conversion circuit for converting a digital signal output from the digital operation control circuit into an analog voltage signal and outputting the converted analog voltage signal to the voltage / current conversion circuit.

Also, a high gain amplifier circuit is inserted between the signal level detection circuit and the voltage / current conversion circuit.

(Operation) As described above, according to the present invention, there is provided a control circuit which uses a semiconductor optical amplifying element as an optical signal amplifying / attenuating element and automatically adjusts an electric bias of the semiconductor optical amplifying element. (A) equalization operation by amplification as well as attenuation of optical signal is possible;
(B) Amplification / attenuation characteristics can be controlled by electrical control instead of thermal control; (c) wide dynamic range operation is possible; (d) power consumption can be reduced during attenuation operation; and (e) output. A level automatic stabilization control circuit; (f) a circuit suitable for small module / hybrid integration / monolithic integration; (g) multi-channel capability , Are significantly different from the prior art.

[0019]

Embodiments of the present invention will be described below in detail with reference to the drawings.

(First Embodiment) FIG. 3 shows a first embodiment of the present invention.
1 shows a configuration of an optical power level equalization circuit according to the embodiment. Here, 1 is an optical fiber, 6 is a semiconductor optical amplifying / attenuating element for amplifying and attenuating an optical signal, 7 is a branch circuit for an optical signal, and 8 is an optical / electrical converting circuit (O / O) for converting an optical signal into an electric signal. /
E) and 9 are signal level detection circuits (Det.) And 10 is a voltage / current conversion circuit (V /
I) and 11 are reference level voltage terminals. The semiconductor optical amplifying / attenuating element 6 is a current control type semiconductor optical control function element, and is a semiconductor optical amplifying element (SOA).
It is assumed that the device is currently being actively researched and developed as a tical Amplifier).
(Reference 1) T. Ito, N. Yoshimoto, O. Mitomi, K. Magari,
I.Ogawa, F.Ebisawa, Y.Yamada, and Y.Hasumi, "Polari
zation Independent Semiconductor Optical Amplifier
Gate and Its Application in WDM Systems ", IEICE Tr
ans.Electron., Vol.E81-C, No.8 August 1998. (Reference 2) T.Ducellier, M.Goix, J.Phebert, O.Legouezigou,
"Compact high sensitivity 10Gbit / s SOA-filter-pin
receiver module ", Electronics letters, 13th, March
1997, Vol.33, No.6 (Reference 3) K. Morito, M. Ekawa, T.
Watanabe, T. Fujii and Y. Kotaki, "High Saturation o
utput power (+ 17dBm) 1550nm polarization insensitiv
e semiconductor optical amplifier ", ECOC 2000, Vo
l.1, Mon., September 4, Session 1.3.2.).

FIG. 4 shows the SOA (semiconductor optical amplifier).
Is an example of the characteristics of the semiconductor optical amplifying / attenuating element 6, wherein the horizontal axis indicates the driving current of the element and the vertical axis indicates the gain between input and output of the optical signal of the element. By controlling the drive current of the semiconductor optical amplification / attenuation element 6 in a feedback manner, it is possible to attenuate or amplify the optical signal passing through the optical fiber 1.

In the example of FIG. 4, when the drive current of the semiconductor optical amplifying / attenuating element 6 is varied from 15 mA to 70 mA, the gain between the input and output of the optical signal of this element is changed from -20 to +20.
It can be varied widely up to 15 dB. Therefore, the dynamic range is 35 dB. Note that SO
A is a semiconductor chip element, and its size is generally as small as 1 mm square or less.

The operation of the optical power level equalizing circuit of the present invention shown in FIG. 3 is as follows. First, an optical signal from the semiconductor optical amplifying / attenuating element 6 is branched by a branch circuit 7, and the branched optical signal is converted into an electric signal by an optical / electrical conversion circuit 8. A signal level detection circuit 9 compares the level of the electric signal with a reference level voltage (Vref) at a reference level voltage terminal 11, and
The comparison result is converted into a current signal by the voltage / current conversion circuit 10, and this current signal is fed back to the semiconductor optical amplification / attenuation element 6.

When the output level of the optical / electrical conversion circuit 8 is higher than the reference voltage of the reference level voltage terminal 11, the drive current to the semiconductor optical amplifying / attenuating element 6 is reduced, and is lower than the reference voltage. When it is smaller, the output power level of the branch circuit 7 can be stabilized by configuring the signal level detection circuit 9 so that the drive current becomes larger.

FIG. 5 schematically shows the operation of stabilizing the output level of the optical power level equalizing circuit having the configuration shown in FIG. As shown in FIG. 5, when the output signal level of the light is low, the semiconductor optical amplification / attenuation element 6 is operated so as to operate at a high gain, and when the output signal level of the light is high, the operation is performed at a low gain or attenuation. By controlling the drive current of
The output light level can be stabilized. This stability is determined by the loop gain. For example, a high-gain amplifier (amplifier) may be provided between the signal level detection circuit 9 and the voltage / current conversion circuit 10 as necessary so as to increase the loop gain.
, The stability of the optical output level of 1 dB or less can be easily ensured even for a wide input dynamic range of 30 to 40 dB.

Further, when a large light signal is input, the semiconductor optical amplifying / attenuating element 6 performs an attenuating operation.
It requires only a small amount, and the semiconductor optical amplifying / attenuating element 6 is 1 m.
m Smaller modules because each chip element is less than
Suitable for hybrid integration / monolithic integration.

Since the control of the drive current of the semiconductor optical amplifying / attenuating element 6 is feedback control as described above, it is possible to compensate for fluctuations in the wavelength and polarization of the light level.

In the present invention, an SOA is assumed as a gain / attenuation control element, but an optical amplifier such as an optical fiber amplifier (optical fiber amplifier) can be applied.

FIG. 6 shows a detailed circuit configuration and operation of the first embodiment of the present invention. FIG. 6A shows an optical / electrical conversion circuit (O / E) 8 in FIG. Circuit (D
et. 9) shows a detailed circuit configuration of a voltage / current conversion circuit (V / I) 10 portion.

Here, 12 is a photodiode (PD) for converting an optical signal into a current signal, 13 is a resistor for converting a current signal into a voltage signal, 14-1 is an amplifier circuit, and 15 is a capacitor. An optical / electrical conversion circuit (O / E) 8 is constituted by the elements 12 to 15. 25 is a terminal for supplying a PD bias voltage applied to the photodiode 12, and 0 is a ground terminal. Optical / electrical conversion circuit 8
Converts an optical signal into an electric signal by the photodiode 13 and simultaneously integrates the electric signal by the capacitor 15 to detect an average value.

14-3 is a differential input amplifier circuit,
The signal level detection circuit 9 is configured. The signal level detection circuit 9 compares the output voltage (Vo1) 20 of the optical / electrical conversion circuit 8 with the reference voltage (Vref) 16 of the reference level voltage terminal 11, and outputs the comparison result as an output voltage (Vo2) 21. .

14-4 is a differential input amplifier circuit for inputting the output voltage (Vo2) 21, 17 is a drive current setting resistor,
Reference numeral 18 denotes a current driving transistor.
Voltage / current conversion circuit (V / I) 10 according to 4-4 to 18
Is configured. Reference numeral 26 denotes a power supply terminal for a drive current (Id) circuit, and 0 denotes a ground terminal. In the voltage / current conversion circuit 10, a combination circuit of the amplifier circuit 14-4, the driving current setting resistor 17, and the current driving transistor 18 provides
The output voltage (Vo2) 21 of the signal level detection circuit 9 is converted into a drive current Id, and this drive current Id is converted into a semiconductor optical amplifier / drive.
This is supplied to the attenuation element 6.

The operation of this circuit will be described. First, the optical signal is converted into a current signal Iin by the PD 12, and the current signal Iin is converted into a voltage signal (Vo1) 20 by a current / voltage conversion amplifier circuit including the resistor 13 and the amplifier 14-1.
Convert to At the same time, the detection operation of the average value is realized by the integration capacitor 15, and as the Vo1 output, a DC voltage signal is output as the detection result of the average value of the signal level.

The Vo1 output level is compared with a reference level voltage (Vref) by a differential input amplifier circuit 14-3, and an output voltage (Vo2) 21 as a result of the comparison is driven via a voltage / current conversion circuit 10. The drive current Id is converted into a current Id, and the drive current Id is converted into a semiconductor optical amplification / attenuation element 6 (corresponding to SOA)
The feedback to the branch circuit 7 in FIG.
Light output level can be stabilized.

FIG. 6B schematically shows the operation of the circuit shown in FIG. As shown in FIG. 6B, when the voltage signal Vo1 is larger than the reference level voltage Vref, the drive current Id acts to decrease.
When the voltage signal Vo1 is smaller than the reference level voltage Vref, the drive current Id acts to increase. Voltage/
In the current conversion circuit 10, the differential amplifier circuit 14-4 and the resistor 1
7, the combinational circuit of the transistor 18 controls the base potential of the transistor 18 by the output voltage of the differential amplifier circuit 14-4, so that the collector current of the transistor 18 can be linearly and stably controlled.

The feature of this circuit configuration is that the band is limited by 15 capacitors C at the PD output of the first stage, so that the circuit can be operated at a low speed and is easy to realize. Further, since the noise band is necessarily narrowed, the value of Rf can be increased, and high-sensitivity operation can be performed. For this reason, in the optical branch circuit 7 of FIG. 3, there is an advantage that a stable control operation can be realized even if the amount of optical branch to the optical / electrical conversion circuit 8 is set small (for example, 1/10 or less). Also,
Since this circuit can be operated at a low speed, inexpensive components can be used and the circuit can be realized at low cost.

FIG. 7 shows another example of the configuration and operation of the detailed circuit according to the first embodiment of the present invention. FIG. 7A shows the optical / electrical conversion circuit 8 and signal level detection circuit in FIG. 9, a detailed circuit configuration of the voltage / current conversion circuit 10 is shown.

Here, 12 is a photodiode (PD) for converting an optical signal to a current signal, 25 is a PD bias supply terminal of the PD 12, 13 is a resistor for converting a current signal to a voltage signal, and 14-1 is a resistor. The amplifying circuit 22 is a capacitor.
Is composed. 20-1 is the output voltage (Vo1) of the optical / electrical conversion circuit 8.

The reference numeral 14-2 denotes an output voltage (Vo1) 20
A differential input amplifier circuit for inputting -1; 19, a diode; 23, a capacitor; 24, a resistor; and 0, a ground terminal. A combination of these elements constitutes a peak value detection circuit described later. 20-2 is an output voltage (Vo1 ') of the peak value detection circuit.

14-3 is an output voltage (Vo1 ') 2
Reference numeral 16 denotes a reference level voltage (Vref) of a reference level voltage terminal 11 of the amplifier circuit 20-2, and reference numeral 21 denotes an output voltage (Vo2) of the signal level detection circuit 9. It is.

14-4 is an output voltage (Vo2) 21
, An amplifier circuit having a differential input, and a driving current (I
d) a circuit power supply terminal, 17 is a resistor for setting the drive current (Id), 18 is a current drive transistor, and a voltage / current conversion circuit 10 is constituted by a combination of these elements. The drive current (Id) of 10 is supplied to the semiconductor optical amplifying / attenuating element 6 (corresponding to the SOA).
0 is a ground terminal.

FIG. 7B schematically shows the operation of the circuit shown in FIG. The circuit configuration of FIG. 7 of the present invention is different from the circuit configuration of FIG. 6 of the present invention in that the capacitance 15 is eliminated, the output voltage (Vo1) 20-1, the differential input amplifier circuit 14-2, and the diode The difference is that a peak value detection circuit composed of 19, a capacitor 23, and a resistor 24 is added.

The operation of the optical power level equalizing circuit shown in FIG. 7 will be described. First, the optical signal branched by the branch circuit 7 in FIG. 3 is converted into a current signal by the photodiode 12 constituting the optical / electrical conversion circuit 8, and this current signal is constituted by the resistor 13 and the amplifier circuit 14-1. The current / voltage conversion amplifier circuit converts the signal into a voltage signal (Vo1). This voltage signal (Vo1) is input to a peak value detection circuit including a differential amplifier circuit 14-2, a diode 19, a capacitor 23, and a resistor 24 via a capacitor (C1) of 22.

The peak value detection circuit detects the peak value of the signal waveform using the rectification characteristic of the diode 19, and detects the detected peak voltage level (Vo of the output voltage 20-2).
1 ') is output. The peak value detection operation will be described. When the signal level is high (high level), the diode 19 is turned on, electric charge is accumulated in the capacitor 23 (C2), and when the signal level is low (low level), The diode 19 is turned off, and the peak value voltage is held by the electric charge accumulated in the capacitor 23. Resistance 24
Is to set the response time when the input signal level changes. If the resistance value Rh is set to a high resistance, the holding time of the peak value voltage can be set long, and if the resistance value Rh is set low, the holding value of the peak value voltage can be set. Time can be set shorter.

This peak value voltage Vo1 '(20-2) is compared with a reference level voltage (Vref) by a differential input amplifier circuit 14-3 at the next stage, and a voltage signal V which is the result of the comparison is obtained.
o2 (21) is connected to the differential input amplifier circuit 14-4 and the resistor 1
Semiconductor amplifying / attenuating element 6 by a current through a voltage / current conversion circuit 10 comprising a transistor 7 and a transistor 18.
(Corresponding to SOA)
The light output level in the branch circuit 7 of FIG. 3 can be stabilized.

As shown in FIG. 7B, when the peak value voltage Vo1 'is higher than the reference level voltage Vref, the drive current Id acts to decrease, and the peak value voltage Vo1' is lower than the reference level voltage Vref. When Vo1 'is small, it acts to increase the drive current Id. The voltage / current conversion circuit 10 is configured such that the base potential of the transistor 18 is controlled by voltage and the collector current thereof can be linearly and stably controlled, as in the configuration example of FIG.

The feature of the circuit configuration of FIG. 7 is that, compared to the circuit configuration of FIG. 6, capacitive coupling is performed by the capacitor (C1) 22 and peak value detection is performed. This has an advantage that DC noise (for example, a spontaneous emission light component of the SOA 6) of an optical signal can be removed. Therefore, as compared with the average value detection circuit of FIG. 6, it is possible to realize a more accurate optical output stabilization control for the signal light.

(Second Embodiment) FIG. 8 shows a configuration of an optical power level equalizing circuit according to a second embodiment of the present invention. The circuit configuration of the present embodiment is different from the circuit configuration of the first embodiment in FIG. 3 in that an optical signal branch circuit 7 is disposed in front of the semiconductor optical amplifying / attenuating element 6, and the branch circuit 7 in the preceding stage is used. Using the branched optical signal, feedforward control is performed on the semiconductor optical amplifying / attenuating element 6 through a circuit including an optical / electrical conversion circuit 8, a signal level detection circuit 9, and a voltage / current conversion circuit 10. Are different.

In this embodiment, since the feedforward control is performed, it is difficult to stabilize the output level with high precision. However, the optical signal is branched before the semiconductor optical amplifying / attenuating element 6, and the output is adjusted according to the level of the optical signal. Since the control is performed, there is an advantage that the semiconductor light amplification / attenuation element 6 is not affected by noise (such as spontaneous emission light).

FIG. 9 is a modification of the configuration of FIG. 8, and shows a configuration in which a programmable control circuit 9-2 is introduced instead of the signal level detection circuit 9 of FIG. In this configuration, conditions are set at the control terminal 27 of the programmable control circuit 9-2 according to the amplification / attenuation characteristics of the semiconductor optical amplification / attenuation element 6 (drive current and gain / attenuation characteristics relationship, wavelength dependence, polarization dependence). ), A highly stable optical power level equalizing operation can be realized.

FIG. 10 shows a detailed configuration example of the programmable control circuit 9-2 in FIG. Here, 28 is an analog / digital conversion circuit (A / D), 29 is a digital operation control circuit, and 30 is a digital / analog conversion circuit (D / D).
/ A), 31 is a memory, and 27-2 is a memory information setting terminal.

The relationship between the drive current of the semiconductor optical amplifying / attenuating element 6 and the gain / attenuation characteristic is previously input (stored) to the memory 31 via the memory information setting terminal 27-2. A / D signal of analog level
The signal is converted into a digital signal at 28, the digital operation control circuit 29 compares the digital signal level with the contents of the memory information in the memory 31, calculates and outputs an optimal control voltage signal, and outputs the D / A 30 Converts the digital signal output into an analog voltage signal and outputs it to the voltage / current conversion circuit 10.

By adopting such a configuration, a stable and highly accurate output power level equalizing operation can be realized even in Feedford.

(Third Embodiment) FIG. 11 shows an applied embodiment of the present invention as a third embodiment of the present invention. Here, reference numeral 40 denotes an optical power level equalizing circuit (any one of the circuits shown in FIGS. 3, 8, and 9) of the present invention, and 41 denotes an optical processing circuit which receives an optical signal from an optical receiving circuit or the like and operates. Circuit. For example, assuming that 41 is an optical receiving circuit, the optical power level equalizing circuit 40 of the present invention is inserted in front of the optical receiving circuit 41, so that the optical power level equalizing circuit 40 amplifies and attenuates the optical input. The dynamic range for the signal can be greatly extended.

As a circuit corresponding to 41, in addition to the above-described optical receiving circuit, for example, the input dynamic range is small,
An optical wavelength conversion circuit having a small allowable input level fluctuation range can be cited, and the optical power level equalization circuit 40 of the present invention is used as an equalization circuit for the input of such an optical wavelength conversion circuit.
Can be applied effectively.

(Fourth Embodiment) FIG. 12 shows, as a fourth embodiment of the present invention, the development of application of the optical power level equalizing circuit 40 of the present invention to multi-channel operation. As shown in FIG. 13A, only the conventional attenuation characteristic can equalize to the lowest output level in the channel, but as shown in FIG. By using the operation, an arbitrary output level can be set.

[0057]

As described above, according to the present invention,
A semiconductor optical amplifier is used as an optical signal amplifying / attenuating element, and a control circuit is provided to automatically adjust the electrical bias of the semiconductor optical amplifying element. A more accurate optical power level equalization operation can be realized.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration example of a conventional variable attenuation circuit.

FIG. 2 is a graph schematically showing a variable attenuation characteristic of a conventional variable attenuation circuit.

FIG. 3 is a block diagram illustrating a basic configuration of an optical power level equalization circuit according to the first embodiment of the present invention.

FIG. 4 is a graph schematically showing a characteristic example of a semiconductor optical amplification / attenuation element used in the present invention.

FIG. 5 is a graph illustrating an optical power level equalizing operation of the optical power level equalizing circuit according to the first embodiment of the present invention.

FIG. 6 is a circuit diagram (A) showing a detailed configuration of an average value detection type optical signal level detection circuit according to the first embodiment of the present invention;
And a graph (B) showing the operation of the circuit.

FIGS. 7A and 7B are a circuit diagram (A) showing a detailed configuration of a peak value detection type optical signal level detection circuit according to the first embodiment of the present invention, and a graph (B) showing an operation of the circuit.

FIG. 8 is a block diagram illustrating a configuration of an optical power level equalization circuit according to a second embodiment of the present invention.

FIG. 9 is a block diagram showing a modification of the optical power level equalization circuit according to the second embodiment of the present invention.

FIG. 10 is a block diagram showing a detailed configuration of the programmable control circuit of FIG. 9;

FIG. 11 is a block diagram (A) showing an application example of the embodiment of the present invention as a third embodiment of the present invention, and a conceptual diagram (B) for explaining the operation thereof.

FIG. 12 is a block diagram showing, as a fourth embodiment of the present invention, the development of application of the optical power level equalizing circuit of the present invention to multi-channel.

FIG. 13 is a graph (A) showing an operation when only the conventional attenuation is used, and a graph (B) showing an operation when the present invention is applied, in a case where the optical power level equalization circuit has multiple channels. It is.

[Description of Signs] 1 Optical fiber 2 Variable attenuation element 3 Heating / cooling element for controlling variable attenuation element 2 4 Temperature control circuit for controlling heating / cooling element 3 5 Electric control terminal 6 Semiconductor optical amplification / attenuation Element 7 Branch circuit for optical signal 8 Optical / electrical conversion circuit for converting optical signal to electric signal 9 Signal level detection circuit 9-2 Programmable control circuit 10 Voltage / current conversion circuit for converting voltage signal to current signal 11 Reference level voltage Terminal 12 Photodiode (PD) for converting an optical signal to a current signal 13 Resistor for converting a current signal to a voltage signal 14, 14-1 Amplifying circuit 14-2, 4-3, 4-4 Amplification of differential input Circuit 15 Capacitance 16 Reference level voltage (Vref) 17 Driving current setting resistor 18 Current driving transistor 19 Diode 20, 20-1 Light / electric conversion Circuit of the output voltage (Vo
1) 20-2 Output voltage of the peak value detection circuit (Vo1 ') 21 Output voltage of the signal level detection circuit (Vo2) 22, 23 Capacitance 24 Resistance 25 PD bias supply terminal 26 Drive current circuit power supply terminal 27 Control terminal 27 -2 memory information setting terminal 28 analog / digital conversion circuit (A / D) 29 digital operation control circuit 30 digital / analog conversion circuit (D / A) 31 memory FIG. 3, FIG. 8 40 Optical power level equalization circuit of the present invention (FIGS. 3, 8,
(Fig. 9) 41 Optical processing circuit that operates upon receiving an optical signal such as an optical receiving circuit 0 Ground terminal

Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat II (Reference) H04J 14/02 H04B 10/17 10/16 (72) Inventor Toshio Ito 2-3-1 Otemachi, Chiyoda-ku, Tokyo Nippon Telegraph and Telephone Corporation (72) Inventor Akira Oki 2-3-1 Otemachi, Chiyoda-ku, Tokyo Nippon Telegraph and Telephone Corporation (72) Inventor Yasuhiro Suzuki 2-3-1 Otemachi, Chiyoda-ku, Tokyo No. 1 Inside Nippon Telegraph and Telephone Corporation (72) Noboru Ishihara Inventor 2-3-1 Otemachi, Chiyoda-ku, Tokyo Nippon Telegraph and Telephone Corporation (72) Shunichi Higashino 2-chome Otemachi, Chiyoda-ku, Tokyo No.3-1 Nippon Telegraph and Telephone Corporation F-term (reference) 5K002 CA03 CA10 CA13 DA02 5K046 AA01 BA07 DD01 DD16 DD17

Claims (8)

[Claims] A current control type semiconductor optical amplifying element for amplifying and attenuating an optical signal according to a drive current; a branch circuit connected to a succeeding or preceding stage of the semiconductor optical amplifying element for branching an optical signal; When the level of the optical signal branched by the branch circuit is small, the driving current of the semiconductor optical amplifying element is changed so that high gain operation is performed, and when the optical signal level is large, low gain or attenuating operation is performed. An optical power level equalizing circuit, comprising: a control circuit for controlling. 2. The optical power level equalizer according to claim 1, wherein the control circuit is configured to convert an optical signal branched by the branch circuit into an electric signal, and the optical / electrical circuit. The voltage level of the electric signal converted by the conversion circuit is detected, and the detected voltage level is compared with a reference level voltage. When the voltage level is higher than the reference level voltage, the drive current is reduced. A signal level detection circuit that outputs a voltage signal that acts to increase the drive current when the voltage level is smaller than the reference level voltage; and converts the voltage signal output from the signal level detection circuit into a current signal. A voltage / current conversion circuit for converting the current signal and feeding back the current signal as the drive current to the semiconductor optical amplification element. 3. The optical power level equalizing circuit according to claim 2, wherein the optical / electrical conversion circuit converts a light signal into a current signal, and converts an output current signal of the photodiode into a voltage signal. By having a current / voltage conversion amplifier circuit composed of a resistor for conversion and an amplifier, and a capacitor for integrating the voltage signal and detecting an average value, a DC voltage signal is obtained as a detection result of the average value of the signal level. The signal level detection circuit has a differential input amplifier circuit that compares the DC voltage signal of the optical / electrical conversion circuit with a reference level voltage and outputs the comparison result as an output voltage. The voltage / current conversion circuit includes a driving current setting resistor, a differential input amplifier circuit having one input port connected to the resistor, and the other input port connected to the output voltage of the signal level detection circuit. An optical power level equalizing circuit, wherein an output voltage of the signal level detecting circuit is converted into the driving current by a combination circuit with a current driving transistor whose base potential is controlled by an output voltage of the amplifier. . 4. The optical power level equalizing circuit according to claim 1, wherein the control circuit converts an optical signal branched by the branch circuit into an electric signal, and the optical / electrical circuit. A peak value detection circuit that detects a peak value of the signal waveform of the electric signal converted by the conversion circuit and outputs the detected peak voltage level; anda peak voltage level and a reference level voltage output from the peak value detection circuit. By comparison, the drive current decreases when the voltage peak voltage level is higher than the reference level voltage, and increases when the peak voltage level is lower than the reference level voltage. A signal level detection circuit that outputs a voltage signal that acts on the semiconductor device; converting the voltage signal output from the signal level detection circuit into a current signal; Optical power level equalizing circuit, characterized in that it comprises a voltage / current converter circuit for feeding back to the optical amplifier. 5. The optical power level equalizing circuit according to claim 4, wherein the optical / electrical conversion circuit converts a light signal into a current signal and converts the output current signal of the photodiode into a voltage signal. A current / voltage conversion / amplification circuit including a resistor to be converted and an amplifier, wherein the peak value detection circuit detects a signal level of an electric signal converted by the optical / electric conversion circuit; An amplifier, a diode connected to a stage subsequent to the amplifier, and a capacitor connected to a stage subsequent to the diode and a resistor for setting a holding time of a peak value voltage, and when the signal level is High, the diode is turned on. When the charge is stored in the capacitor and the signal level is Low, the diode is turned off, and the peak value voltage is held by the charge stored in the capacitor, The signal level detection circuit includes a differential input amplifier circuit that compares the peak value voltage signal of the peak value detection circuit with a reference level voltage, and outputs a result of the comparison as an output voltage. The conversion circuit includes a drive current setting resistor, a differential input amplifier circuit having one input port connected to the resistor and the other input port connected to the output voltage of the signal level detection circuit, and an output voltage of the amplifier. An optical power level equalizing circuit, wherein an output voltage of the signal level detecting circuit is converted into the driving current by a combination circuit with a current driving transistor whose base potential is controlled more. 6. The optical power level equalizing circuit according to claim 2, wherein a programmable control circuit is connected to said signal level detecting circuit, said programmable control circuit being connected to said semiconductor optical amplifier. Highly stable optical power level equalization operation can be performed by setting in advance the necessary conditions such as the relationship between the drive current and gain / attenuation characteristics, wavelength dependence, and polarization dependence according to the amplification / attenuation characteristics of the An optical power level equalizing circuit characterized by: 7. The optical power level equalizing circuit according to claim 6, wherein the programmable control circuit is configured to store in advance a driving current of the semiconductor optical amplifying element and a gain / attenuation characteristic relationship; An analog / digital conversion circuit for converting an analog level signal from the conversion circuit into a digital signal; and comparing the level of the digital signal output from the analog / digital conversion circuit with the information stored in the memory to determine an optimum control voltage. A digital operation control circuit for calculating and processing a signal, and a digital / analog conversion for converting the digital signal output from the digital operation control circuit into an analog voltage signal and converting the converted analog voltage signal to the voltage / current conversion circuit And an optical power level equalization circuit. 8. The optical power level equalizing circuit according to claim 2, wherein a high gain amplifier circuit is inserted between the signal level detection circuit and the voltage / current conversion circuit. Characteristic optical power level equalization circuit.