JP2002237722A - Voltage controlled oscillation circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a voltage controlled oscillation circuit capable of shorten ing an oscillation start time. SOLUTION: When a power is supplied, an 'L' level signal ST is outputted from an oscillation start recognizing circuit 17, and a PMOS transistor 18 and a transmission gate 19 are turned on and off, and a power voltage Vdd is applied to varicaps 14-1 and 14-2 so that the oscillation start time can be shortened. After oscillation is started, an 'H' level signal ST is outputted from the oscillation start recognizing circuit 17, and the PMOS transistor 18 and the transmission gate 19 are turned on and off, and a control voltage Vc is applied to the varicaps 14-1 and 14-2 so that a normal oscillation frequency signal can be outputted.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a voltage controlled oscillation circuit incorporating a voltage variable capacitor.

[0002]

2. Description of the Related Art Conventionally, a voltage controlled oscillator (VC) having a crystal oscillator and a variable capacitance diode (referred to as a varicap) whose capacity varies according to the magnitude of an applied voltage.
XO; Voltage Controlled X't
al Oscillator) are known.

FIG. 2 is a diagram showing a configuration of a conventional voltage controlled oscillation circuit.

The voltage controlled oscillator circuit 100 shown in FIG.
Two terminals 11_1 and 11_2 and the two terminals 1
1_1, 11_2, the crystal oscillator 12, the capacitor 13_1 and the varicap 14_1 connected in series between the terminal 11_1 and the ground GND, and the capacitor 13_2 connected in series between the terminal 11_2 and the ground GND. A varicap 14_2 is provided. In addition, the voltage controlled oscillation circuit 100 includes:
The connection point between the capacitor 13_1 and the varicap 14_1, the capacitor 13_2 and the varicap 14_2
Resistance element 15_1 connected in series between the
15_2 are provided. Further, the voltage controlled oscillation circuit 100 includes a control terminal 11_3 connected to a connection point between the resistance elements 15_1 and 15_2. A predetermined control voltage Vc is applied to the control terminal 11_3.

The voltage controlled oscillation circuit 100 has a resistance element 15_ connected in series between the terminals 11_1 and 11_2.
3, 15_4, an inverter 16_1 having an input side connected to the terminal 11_1 and an output side connected to a connection point between the resistance elements 15_3, 15_4, and the inverter 16_1.
_1, an inverter 16_2, 1 connected in series to the output side
6_3 and an output terminal 11_4 connected to the output side of the inverter 16_3.

[0006] The voltage controlled oscillation circuit 1 thus configured
When the power is turned on at 00, a predetermined control voltage Vc is applied to the control terminal 11_3. The control voltage Vc is supplied to the varicap 14_ via the resistance elements 15_1 and 15_2.
1, 14_2, whereby the capacitance value of the varicaps 14_1, 14_2 changes according to the magnitude of the control voltage Vc, and the oscillation frequency due to the resonance inherent to the crystal oscillator 12 is in a range of, for example, ± 100 ppm to ± 150 ppm. Change within. In this way, a signal having an oscillation frequency corresponding to the magnitude of the predetermined control voltage Vc is output from the inverter 16_1, the waveform is shaped via the inverters 16_2 and 16_3, amplified, and output from the output terminal 11_4 to the outside. .

[0007]

In the above-described voltage controlled oscillation circuit 100, when the predetermined control voltage Vc applied to the control terminal 11_3 is relatively small, the varicap 14_
There is a problem that the capacitance value of 1,14_2 becomes relatively large, so that a long time is required for the oscillation start.

The present invention has been made in view of the above circumstances, and has as its object to provide a voltage controlled oscillation circuit in which the oscillation start time is reduced.

[0009]

In order to achieve the above object, a voltage controlled oscillator according to the present invention is a voltage controlled oscillator incorporating a voltage variable capacitor. A starting voltage providing means for providing a starting voltage whose oscillation margin is higher than a voltage; and a control voltage providing means for providing the control voltage in place of the starting voltage to the variable voltage capacitor after the oscillation is started. And

In a voltage controlled oscillation circuit incorporating a voltage variable capacitor, when a relatively large control voltage is applied to a voltage variable capacitor (for example, a varicap), the value of the voltage variable capacitor becomes relatively small. Therefore, the oscillation start time is relatively short, and the oscillation margin is increased. On the other hand, when a relatively small control voltage is applied to the voltage variable capacitance, the value of the voltage variable capacitance becomes relatively large. For this reason, the oscillation start time is relatively long and the oscillation margin is low. As described above, the oscillation margin in the voltage controlled oscillation circuit depends on the magnitude of the control voltage applied to the voltage variable capacitor. The present invention has been made by focusing on such a viewpoint.

In the voltage-controlled oscillation circuit according to the present invention, when the power is turned on, a start voltage at which the oscillation margin becomes higher than the control voltage during normal oscillation is given to the voltage variable capacitor. As a result, oscillation start is performed, and the oscillation start time is short. After the oscillation is started, the control voltage is applied to the voltage variable capacitor, so that a signal having a normal oscillation frequency corresponding to the magnitude of the control voltage is output.

[0012]

Embodiments of the present invention will be described below.

FIG. 1 is a circuit diagram of a voltage controlled oscillation circuit according to one embodiment of the present invention.

The same components as those of the voltage controlled oscillation circuit 100 shown in FIG. 2 are denoted by the same reference numerals, and the description thereof will not be repeated.

The voltage controlled oscillation circuit 10 shown in FIG. 1 includes, in addition to the components of the voltage controlled oscillation circuit 100 shown in FIG. 2, an oscillation start recognition circuit 17 whose input side is connected to a connection point between the inverters 16_2 and 16_3. A PMOS transistor 18 having a gate connected to the output side of the oscillation start recognizing circuit 17, a source connected to the power supply for supplying the power supply voltage Vdd, and a drain connected to a connection point between the resistance elements 15_1 and 15_2; , 15_2 and a control terminal 11_3, and a transmission gate 19, and an inverter 16_4.

The transmission gate 19 has an NMOS transistor 1 whose gate is connected to the output side of the oscillation start recognition circuit 17 and the input side of the inverter 16_4.
9_1 and a PMOS transistor 19_2 whose gate is connected to the output side of the inverter 16_4. The oscillation start recognizing circuit 17, the PMOS transistor 18, the transmission gate 19, and the inverter 16_4 play the role of both the start voltage applying means and the control voltage applying means according to the present invention. Hereinafter, the operation of the voltage controlled oscillation circuit 10 shown in FIG. 1 will be described.

When power is supplied to the voltage controlled oscillation circuit 10, the power supply voltage Vd is applied to the entire voltage controlled oscillation circuit 10.
d and a predetermined control voltage Vc (for example, Vdd / 2) is applied to the control terminal 11_3. When the power is turned on, the oscillation start recognition circuit 17 outputs “L”.
A level signal ST is output. This “L” level signal ST is input to the gate of the PMOS transistor 18, whereby the PMOS transistor 18 is turned on. Further, the signal ST at the “L” level is applied to the NMOS transistor 1 constituting the transmission gate 19.
Input to the gate of 9_1. Therefore, the NMOS
The transistor 19_1 is turned off. Further, the signal ST at the “L” level is changed to “H” by the inverter 16_4.
It is converted to a level and input to the gate of the PMOS transistor 19_2. Therefore, the PMOS transistor 19_2 is also turned off. Therefore, the transmission gate 19 is turned off. Thus, the power supply voltage Vdd, which is a start voltage higher than the control voltage Vc, is applied to the connection point between the resistance elements 15_1 and 15_2 via the PMOS transistor 18. This power supply voltage V
dd is applied to the varicaps 14_1 and 14_2 via the resistance elements 15_1 and 15_2. Since such a sufficiently large power supply voltage Vdd is applied to the varicaps 14_1 and 14_2, the varicaps 14_1 and 14_2
The capacitance value of 14_2 becomes small, so that the oscillation starting time from the time when the power is turned on until the oscillation starts is short, and the oscillation margin is increased.

After the oscillation is started in the voltage controlled oscillation circuit 10, the oscillation start recognition circuit 17 has an inverter 16_
2 is input. The oscillation start recognition circuit 17 counts the oscillation frequency of this signal, and outputs an “H” level signal ST when the oscillation frequency reaches a predetermined value. The "H" level signal ST is input to the gate of the PMOS transistor 18, and the PMOS transistor 18 is turned off. Further, the signal ST at the “H” level is input to the gate of the NMOS transistor 19_1, so that the NMOS transistor 19_1 is turned on. Further, the "H" level signal ST
Is converted to 'L' level by the inverter 16_4 and PM
Since the signal is input to the gate of the OS transistor 19_2,
The PMOS transistor 19_2 is also turned on.
Therefore, the transmission gate 19 is turned on. Then, the control voltage Vc applied to the control terminal 11_3 is applied to the connection point between the resistance elements 15_1 and 15_2 via the transmission gate 19, and further, the varicap 1 is connected via the resistance elements 15_1 and 15_2.
4_1 and 14_2. Varicap 14_
1, 14_2 have a capacitance value commensurate with the magnitude of the control voltage Vc, whereby a signal having an oscillation frequency based on the capacitance value is output from the inverter 16_1, and further subjected to waveform shaping and amplification by the inverters 16_2, 16_3. Output from the output terminal 11_4.

In the voltage-controlled oscillation circuit 10 of the present embodiment, when the power is turned on, the oscillation start recognition circuit 17 outputs an "L" level signal ST, whereby the varicap 14_
Since the power supply voltage Vdd is applied to the power supply voltages 1 and 14_2, the oscillation start is performed based on the relatively small capacitance values of the varicaps 14_1 and 14_2. Therefore, the oscillation start time is short and the oscillation margin is increased. After the oscillation is started, the oscillation start recognition circuit 17 outputs the “H” level signal ST.
_2, the control voltage Vc is applied instead of the power supply voltage Vdd, and oscillation is performed based on the relatively large capacitance values of the varicaps 14_1 and 14_2. Therefore, the control voltage Vc
Will be output at the normal oscillation frequency corresponding to the magnitude of.

The oscillation start-up time in the voltage-controlled oscillation circuit 10 of this embodiment is about 1 ms when the voltage at the connection point between the resistance elements 15_1 and 15_2 is 0 V, and about 0.5 ms when the voltage at the power supply voltage Vdd. is there. Therefore,
Oscillation start-up time can be reduced by about 0.5 ms at the maximum. In addition, since the oscillation state is locked and stabilized when the oscillation starts, the allowance during the normal oscillation also increases with the increase in the allowance at the start of the oscillation.

In this embodiment, the oscillation start recognition circuit 1
Although the counter 7 has been described as an example of a counter, the present invention is not limited to this, and a so-called power-on reset circuit configuration that outputs a signal for recognizing the oscillation start after a predetermined time has elapsed since the power was turned on may be used.

[0022]

As described above, according to the present invention,
The oscillation start time can be shortened.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a voltage controlled oscillation circuit according to an embodiment of the present invention.

FIG. 2 is a diagram showing a configuration of a conventional voltage controlled oscillation circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Voltage controlled oscillation circuit 11_1, 11_2, 11_3, 11_4 Terminal 12 Crystal oscillator 13_1, 13_2 Capacitor 14_1, 14_2 Varcap 15_1, 15_2, 15_3, 15_4 Resistance element 16_1, 16_2, 16_3, 16_4 Inverter 17 Oscillation start recognition circuit 18, 19_2 PMOS transistor 19 Transmission gate 19_1 NMOS transistor

Claims (1)

[Claims] 1. A voltage-controlled oscillation circuit incorporating a voltage-variable capacitor, wherein when power is turned on, a start-voltage providing means for applying a start voltage at which an oscillation margin becomes higher than a control voltage during normal oscillation to the voltage-variable capacitor; A voltage-controlled oscillation circuit, comprising: a control voltage applying means for applying the control voltage instead of the start voltage to the voltage variable capacitor after the start of oscillation.