JP2002237189A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve readout speed among different memory cell arrays in a memory system of an overlaid system. SOLUTION: In a memory system of an overlaid system, respective memory cell array is activated independently of the other memory cell array, further, the memory cell array is activated and delay of readout speed by reset pre- charge is not caused by keeping an activation state of respective memory cell arrays at the time of readout between different memory cell arrays.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a semiconductor device having an overlay bus structure and a control circuit therefor.

[0002]

2. Description of the Related Art In recent years, a so-called logic-mixed memory in which memories having various capacities and configurations are combined with a logic system for performing various data processing to form one IC chip has been reduced. It has been demanded because of the need for higher power consumption, higher speed for increasing data transfer efficiency, and expansion of bit width.

At this time, the bus width for exchanging data between the memory unit and the logic unit is often constant, for example, 64 bits or 128 bits. In order to meet various demands from a system in which the logic unit and the like are mixed, it is preferable that the configuration of the memory unit has a data bus width that is invariable with respect to a change in an address configuration or a memory capacity.

In response to such demands, a memory system having an overlay bus structure has been proposed.

FIG. 16 shows a circuit configuration of a memory cell array and its peripheral portion of a memory system having an overlay bus structure. FIG. 16 focuses on three memory cell arrays out of a plurality of memory cell arrays, and a memory system includes a plurality of such memory cell arrays.
The memory system shown in FIG. 16 employs a shared sense amplifier system in which a sense amplifier is shared by memory cells on both sides of a memory cell array.

[0006] The memory system includes a memory cell array MC.
Ai-1, MCAi, and MCAi + 1, and data lines DATA0 to DATA2 common to each memory cell array.
55, sense amplifiers S / A, S / A1 to S / A4
, Column switches CSW, CSW1, and CSW2, and a decoder circuit DEC. The memory cell array has 256 rows × 1024 columns, and 1024
Of bit lines and 256 word lines. FIG.
Only the bit line pair BL and BL1 to BL4 are shown therein. The sense amplifiers S / A and S / A1 to S / A4 are shared by adjacent memory cell arrays. For example, MCA
i and MCAi-1 share the sense amplifier S / A1, and MCAi and MCAi + 1 share the sense amplifier S / A1.
/ A2 is shared.

In the case of the memory cell array MCAi, BL
1 to BL4 are sense amplifiers S / A1 to S, respectively.
/ A4. Also, the sense amplifier S / A1,
S / A3 is connected to the column switch CSW1, the sense amplifier S / A2, and S / A4 are connected to the data line pair DATA0 via the column switch CSW2. Therefore,
The four sense amplifiers S / of the memory cell array MCAi
A1 to S / A4 can be connected to a pair of data lines DATA0. That is, each memory cell array has a common data line for every 4-bit line pair. Although not shown, since the memory cell array has 1024 bit line pairs, the data line DATA is 1024/4 = 25.
6 pairs. Hereinafter, the operation of this memory system will be described by referring to the data on the memory cell array MCAi as the data line DATA0
A case where the data is read out to DATA255 will be described as an example.

The decoder circuit DEC selects one word line of a desired memory cell array MCAi according to the row address. Data specified by the selected word line on bit line pair BL1-BL4 is applied to sense amplifier S /
A1 to S / A4 are sent, and MCAi is activated. Further, when the sensing operation of the sense amplifiers S / A1 to S / A4 is completed, the decoder circuit DEC determines the O of the column switches CSW1,2 according to the column address.
N, OFF, and sense amplifiers S / A1 to S / A
4 sends out one of the data sensed and held to the data line pair DATA0. Therefore, the data of the memory cell selected by the column address of the word line selected by the row address is transmitted to the data line pair DATA0. Similarly, data is transmitted to the other data line pairs DATA1 to 255, so that data is transmitted to a total of 256 pairs of data lines.

FIG. 17 shows a data bus memory system having a width of 128 I / O as an example of a configuration of a memory system using the above-mentioned overlay structure.

The memory system comprises two blocks 170
1 and 1702, each block having 16 memory cell arrays MCA0 to MCA15 and MCA16.
To MCA31. Each memory cell array has 256 rows × 1024 columns, and the total capacity of the memory system is 8 megabits.

Upper and lower blocks 1701, 170
2, each of 16 memory cell arrays MCA0
To MCA15 and MCA16 to MCA31, each of which has 256 data lines 1704 and 1705 in the bit line direction of the memory cell array. These data lines 1704 and 1705 are connected to column decoders 1706 and 1707, respectively.
Connected to. A decoder circuit 1703 exists between the respective blocks 1701 and 1702, is shared by both blocks, and simultaneously controls selection of a word line and a column switch of each block.

A decoder circuit 1703 selects an arbitrary word line of, for example, MCA5 and MCA21 in accordance with the input row address. The data of the selected word line is sent to the sense amplifier and sensed (MCA5, MCA5).
CA21 is activated). Next, the decoder circuit 170
Reference numeral 3 selects a sense amplifier according to the input column address, and sends data to the data lines 1704 and 1705. The data lines 1704 and 1705 are connected to the column decoder circuit 1
706 and 1707 are input. Column decoder circuit 170
6 and 1707 respectively select 64 data lines from 256 data lines and connect them to the data buses 1708 and 1709.

As described above, the upper and lower data bus widths are 64 I / Os, respectively, for a total of 128 I / Os.

The capacity of the memory system having such a structure can be increased or decreased by increasing or decreasing the number of memory cell arrays MCA. In this case, the number of data lines does not increase or decrease. Therefore, a constant data bus width can always be maintained.

Next, the memory cell arrays MCA5, MCA
After reading the data of A21, MCA13, MCA2
The case where 9 data is read will be described.

First, data in the memory cell arrays MCA5 and MCA21 is read in accordance with the above procedure. Next, the decoder circuit resets / precharges the activated memory cell arrays MCA5 and MCA21. Next, the decoder circuit 1703 selects an arbitrary word line of the MCA 13 and the MCA 29 according to the input row address. The data on the selected word line is sent to the sense amplifier and sensed (MCA13, MCA2).
9 is activated). Next, the decoder circuit 1703 selects a sense amplifier according to the input column address, and sends data to the data lines 1704 and 1705.
The data lines 1704 and 1705 are connected to the column decoder circuit 170
6, 1707. A column decoder circuit 1706,
Reference numeral 1707 selects 64 data lines from 256 data lines and connects them to the data buses 1708 and 1709.

As described above, since the memory cell array is activated and precharged by the row address decoded by the decoder circuit 1703, the data read operation between different memory cell arrays is performed by MCA5,
MCA21 activation → data reading → MCA5, MC
A21 reset / precharge → MCA13, MCA2
9 activation → data reading. Therefore, activation and reset / precharge operations of the memory cell are required every time.

In the above example, one memory cell array is simultaneously activated in each of the upper and lower blocks 1701 and 1702. However, although not shown, the input addresses of the word line selection unit and the column switch control unit in the decode circuit 1703 are not shown. By adjusting the number of bits, a plurality of memory cell arrays can be activated at the same time. For example, when one bit of the input row address is not used for word line selection but is used for column switch control as a column address, the upper and lower blocks 1701, 17
At 02, two memory cell arrays are simultaneously activated. At this time, MCA0, MCA8, M
CA16 and MCA24 are simultaneously activated, and similarly, MCA5, MCA13, MCA21, MCA29
Are activated simultaneously.

As described above, each block 1701, 170
In the case where two memory cell arrays are activated at the same time in 2, the operation of reading the data of MCA5 and MCA21 as described above and then reading the data of MCA13 and MCA29 is performed by MCA5, MCA13, MCA21,
MCA 29 is activated → data is read from MCA 5 and MCA 21 → data is read from MCA 13 and MCA 29, and reset / precharge of the memory cell can be omitted.

However, even in such a case, the combinations of memory cells that can be activated simultaneously are predetermined, and the memory cell arrays that are not activated simultaneously (for example, MCA5, MCA21 and MCA3, MCA19).
The data read operation in the above requires an activation and a reset / precharge operation.

[0021]

As described above,
In a conventional overlay type memory system, when reading data, it is necessary to activate a memory cell array, reset and precharge, and thus there is a limit to speeding up the data reading operation.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and in a memory system of an overlay type, each memory cell array is activated independently of other memory cell arrays. An object of the present invention is to provide a memory system which does not cause a delay in read speed in activation, reset, and precharge of a memory cell array when data is read between different memory cell arrays by maintaining a read state.

[0023]

In order to solve the above problems, a first semiconductor device according to the present invention is provided with at least three data holding devices having mutually different bank addresses and corresponding to the data holding devices. A plurality of data amplification transfer buffers divided into a plurality of groups, a plurality of data lines provided so as to be commonly coupled to corresponding data amplification transfer buffers in each of the groups, and the data holding Provided in correspondence with each of the devices, sends out data from a predetermined output terminal of the data holding device to a corresponding data amplification / transfer buffer based on a control signal, and thereafter transmits the data in the corresponding data amplification / transfer buffer. To a corresponding data line, and thereafter, a control unit for presetting the data amplification transfer buffer.

A second semiconductor device according to the present invention is a semiconductor device comprising at least two blocks, wherein each block has at least three data holding devices having mutually different bank addresses, and A plurality of data amplification transfer buffers provided correspondingly and divided into a plurality of groups, and a plurality of data lines provided so as to be respectively commonly coupled to the corresponding data amplification transfer buffers in the respective groups And provided for each of the data holding devices, controlling the data holding device based on a control signal, and transferring data of an associated data holding device to a corresponding one of the corresponding data lines based on a control signal. And a control unit for transmitting the data to the data line.

A third semiconductor device according to the present invention is a semiconductor device comprising at least two blocks, wherein each block has at least three data holding devices having mutually different bank addresses, and A plurality of data amplification transfer buffers provided correspondingly and divided into a plurality of groups, and a plurality of data lines provided so as to be respectively commonly coupled to the corresponding data amplification transfer buffers in the respective groups And a plurality of control units, each control unit being provided between the blocks and controlling a data holding device of each block based on a control signal, and further corresponding to the data holding device of each block. Sending the data of the holding device to a corresponding one of the corresponding data lines based on the control signal;
A plurality of control units.

A fourth semiconductor device according to the present invention is a semiconductor device comprising at least two blocks, each block having at least three data holding devices having mutually different bank addresses, and corresponding to the data holding devices. A plurality of data amplification transfer buffers divided into a plurality of groups, and a plurality of data lines provided so as to be respectively coupled to the corresponding data amplification transfer buffers in each of the groups. A plurality of control units provided between the blocks for controlling the data holding device of each block based on a control signal and transmitting data of the data holding device of each block to the corresponding data line based on a control signal And

The array control units of the first to fourth semiconductor devices can control the corresponding memory cell arrays independently of each other, and can keep the activated state of the memory cells. In addition, activation and precharge of a memory cell array can be performed irrespective of the operation state of another memory cell array. That is, when data is read between different memory cell arrays, it is not necessary to consider the time required for resetting and precharging the memory cells.

[0028]

FIG. 1 shows a circuit configuration of a memory cell array of a memory system of a semiconductor memory device according to the present invention and peripheral portions thereof. FIG. 1 focuses on three memory cell arrays out of a plurality of memory cell arrays, and a memory system includes a plurality of such memory cell arrays. The memory system shown in FIG. 1 employs a shared sense amplifier system in which a sense amplifier is shared by memory cells on both sides of a memory cell array.

The memory system has separate addresses, and has a plurality of bit line pairs BL, BL1 to BL4.
Cell arrays MCAi-1 and MCAi having
, MCAi + 1, and array control units CTRLi-1 and CTRLi provided in each memory cell array.
, CTRLi + 1, data lines DATA0 to DATA255 common to each memory cell array, array selection switches ASW, ASW1 to ASW4, sense amplifiers S / A, S / A1 to S / A4, and column switches CSW, CSW1, CSW2. It is composed of Memory cell arrays MCAi, MCAi-1, MCAi
+1 is 256 rows × 1024 columns, and 1
It has 024 bit line pairs and 256 word lines.
FIG. 1 shows only the bit line pairs BL and BL1 to BL4. S / A, S / A1 to S / A
4 is shared by adjacent memory cell arrays. For example, MCAi and MCAi-1 are sense amplifiers S / A1
, And MCAi and MCAi + 1 share the sense amplifier S / A2.

In the case of the memory cell array MCAi, BL
1 to BL4 are array switches ASW1 to ASW4
Are connected to the sense amplifiers S / A1 to S / A4. Further, the sense amplifiers S / A1 and S / A3 are connected to the column switch CSW1, the sense amplifiers S / A2 and S / A3, respectively.
/ A4 is connected to the data line pair DATA0 via the column switch CSW2. Therefore, the four sense amplifiers S / A1 to S / A of the memory cell array MCAi
4 can be connected to a pair of data lines DATA0.
That is, each memory cell array has a common data line for every 4-bit line pair. Although not shown, since the memory cell array has 1024 bit line pairs,
Data lines DATA are 1024/4 = 256 pairs. Here, the difference from the conventional memory system shown in FIG. 16 lies in that an array control unit is provided for each memory cell array, and that a bit line is connected to a sense amplifier via an array selection switch. Hereinafter, the operation of the memory system will be described by taking as an example a case where data on the memory cell array MCAi is read out to the data lines DATA0 to DATA255.

The array control unit CTRLi activates the bank address included in the array control signal and the corresponding memory cell array transmitted from the array control units CTRLi-1 and CTRLi + 1 of the adjacent memory cell array arrays MCAi-1 and MCAi + 1. It is determined from the signals BZi-1 and BZi + 1 indicating whether the memory cell array can be activated. Specifically, the bank address included in the array control signal is MCA
i, and MCAi-1 and MCAi + 1 are not activated, MC
Ai can be activated. Memory cell array MCAi
Is determined to be activating, the array control unit CTRL
i selects an arbitrary word line of the memory cell array MCAi. When the word line is sufficiently boosted, the array control unit CTRLi sets the array selection switch ASW1
A signal for turning ON ASW4 is sent. Array selection switch AS receiving signal SENi
W1 to ASW4 are bit line pairs BL1 to BL4 of the memory cell array MCAi and the sense amplifiers S / A1 to
It is controlled to be connected to S / A4. Bit line pair B
The data specified by the selected word line on L1, BL2, BL3, BL4 is the sense amplifier S /
A1 is sent to A / S / A4, and MCAi is activated. Further, when the sensing operation of the sense amplifiers S / A1 to S / A4 is completed, the array control unit CTRLi sends out the signals CSSi1 and CSSi2 to send the column switch C
SW1 and CSW2 are turned on and off, and one of the data held in the sense amplifiers S / A1 to S / A4 is transmitted to the data line DATA0. Therefore, the data of the selected bit line on the selected word line of the memory cell array MCAi is transferred to the data line DATA0.
At the specified timing.
Similarly, data is transmitted to the data lines DATA1 to DATA255, so that data is transmitted to a total of 256 data lines. Also, when a plurality of memory cell arrays are activated at the same time, the ON / OFF of the column switch can be prevented.
The data held in only one sense amplifier S / A is transmitted to the data line by the F control.

Next, FIG. 2 shows a circuit configuration of the array control unit CTRLi.

The array control unit CTRLi includes an array selection decoder 201, a word line control unit 202, a sense control unit 203, a word line decoder 204, and a column switch selection control unit 205. The array control signal is a signal commonly applied to all array control units, and is a signal including a bank address, a row address, a column address, and various timing signals. Receiving the bank address or a part thereof in the array control signal, the array selection decoder 201 determines whether the corresponding memory cell array is selectable. If the memory cell array is selectable, the signal BNKi is activated at the timing of activating the memory cell array. To the word line controller 2
02 and to the sense control unit 203. Word line control unit 202 receives signal BNKi, and sends signal BZi indicating that the corresponding memory cell array has been activated to array control units of two adjacent memory cell arrays,
A signal / RDPRC and RDACT for controlling the word line decoder are sent to the word line decoder 204. On the other hand, the sense control unit 203 receives the signal BNKi, and after a period in which the rise of the word line selected by the word line decoder 204 is completed, a signal indicating that data can be transferred to the outside of the cell array. CENBi is sent to the column switch selection control unit 205, and the signal SEN or BEQ for controlling the equalization of the sense amplifier and the bit line is transmitted.
To the sense amplifier. Signals are exchanged between the word line control unit 202 and the sense control unit 203 to control the operation sequence. Word line decoder 20
4 receives the signals / RDPRC and RDACT, decodes the row address, and sends out a signal for selecting an arbitrary word line. The column switch selection control unit 205 receives the bank address and the signal CE sent from the sense control unit 203.
Bi, the corresponding memory cell array is selected, and furthermore, if data is held in the sense amplifier, that is, in a so-called activated state, the column address is decoded at the timing of switching the column switch,
A signal for turning on / off the column switch is transmitted.

FIG. 3A shows the details of the array selection decoder. B0 to B3 are 4-bit bank addresses, each of which is paired with its inverted signal, and one of them is input to the NAND gate 301a. Accordingly, there are 16 inputs to the NAND gate 301a,
16 bank addresses can be decoded. That is, all the input signals of the NAND gate 301a of the array control unit in which the bank address given from the outside matches the bank address of the corresponding memory cell array of the array control unit become "H", and the NAND gate 301a
Sends "L". Signals BZi + 1, BZi-1
Are both "L", the NOR gate 302a becomes "H", and Matchi rises. Signal BZ
i + 1 and BZi-1 are signals which become "H" when the memory cell arrays transmitted from both adjacent memory cell arrays are activated. In this embodiment, since the shared sense system is used in which the sense amplifier is shared by the memory cell arrays on both sides, the array control unit CTRLi is used.
Cannot activate the memory cell array even if a bank address is input if any of the adjacent cell arrays is activated. As described above, Matchi
Becomes "H" when the bank address of the corresponding memory cell array is input and the memory cell arrays on both sides are not activated.

Signal ACT is a signal indicating the timing for activating the memory cell array included in the array control signal. The signal PRC is a signal indicating the timing at which the memory cell array included in the array control signal is set to the precharge state. These signals are pulse signals that become “H” only during a certain period. NAND 303a ~
A flip-flop circuit 306a sends out a signal BNKi for directly controlling the word line control unit 202 and the sense control unit 203. When the Matchi signal is “H”, at the timing when ACT rises,
BNKi becomes “H”. At this time, the memory cell array starts a series of sensing operations. In addition, the Match
When the i signal is “H”, BNKi becomes L at the timing when the PRC rises. At this time, the memory cell array starts a series of precharge operations. Other than the above two timings, the NANDs 303a to 306a
Since the flip-flop circuit composed of BNKi holds that state, BNKi also holds that state.

FIG. 3A shows a circuit configuration of an array selection decoder when one memory cell array is simultaneously activated in a block composed of 16 memory cell arrays, and FIG. 4 shows a circuit configuration of an array selection decoder when activating one memory cell array.

When two memory cell arrays are activated at the same time in the block, two of the 16 array control units activate the memory cell arrays, so that the NAND gate 301b has eight inputs. That is, the NAND gates 301 of the two array control units whose bank address given externally and the bank address of the corresponding memory cell array of the array control unit partially match.
All the input signals of “a” become “H”. Thus, according to the array selection decoder of FIG. 3B, the two array control units simultaneously activate or precharge the corresponding memory cell arrays.

FIG. 4 shows the details of the word line decoder 204. 4A is a word line drive signal predecode circuit, FIG. 4B is a row address signal conversion circuit, and FIG.
Is a conversion signal decoding circuit, and FIG. 4D is a word line drive signal generation circuit. These four circuits decode a row address. Hereinafter, detailed operations of these circuits will be described.

The word line drive signal predecoding circuit shown in FIG. 4A is composed of a Pch transistor 401 and an Nc transistor connected in series between a word line drive voltage Vboot and a ground potential.
h transistors 402, 403, and 404, and a latch circuit 405 composed of inverters. The word line drive signal WLDR (0; 3) and its inverted signal / WLDR (0;
Send out 3).

First, when the signal / RDPRC is "L",
The Pch transistor 401 is turned on, and the connection point between the Pch transistor 401 and the Nch transistor 402 is precharged. Next, when this signal becomes H and the Pch transistor 401 is turned off, the Nch transistor 404 is turned on at the timing when the pulse-changing signal RDACT becomes H, and the row addresses RA0 and RA1 are decoded. When the row addresses RA0 and RA1 are decoded, they are converted into a word line drive signal WLDR (0; 3) and its inverted signal / WLDR (0; 3) and transmitted. RA0 and RA1 are 2 bits of the row address, each of which is paired with its inverted signal, and one of them is one of the Nch transistors 402 and 4 respectively.
03 is input. RDACT is a signal that becomes “H” during a period in which the corresponding memory cell array is activated. Therefore, the word line decoding unit 204 decodes the row address only when the corresponding memory cell array is activated.

The row address signal conversion circuit shown in FIG.
NAND having two bits of row address as input
It is composed of a gate 406 and an inverter. For example, RA
2, RA3 is paired with the inverted signal, and the NAND gate 406 having one of them as an input sends PXA (0; 3) via the inverter. Similarly, PXB (0; 3) is obtained from RA4 and RA5.
4. PXB (0; 3) is generated from RA5.

The converted signal decoding circuit shown in FIG. 4C converts the signals PXA (0; 3), PXB (0; 3) and PXC (0;) converted by the row address signal converting circuit shown in FIG. 4B.
This is a circuit for further decoding 3). Pch connected in series between the word line drive voltage Vboot and the ground potential
Transistor 407 and Nch transistors 408 and 40
9, 410, 411 and a latch circuit 4 by an inverter
12 and an inverted signal of the word line decode signal /
Send RDC (0; 63). Nch transistor 4
08, 409 and 410 are signals PXA (0;
3), PXB (0; 3), and PXC (0; 3) as gate inputs.
This is the same as the word line drive signal predecode circuit of FIG.

The word line drive signal generation circuit shown in FIG. 4D includes a Pch transistor 413 and an Nch transistor 4.
14, 415, the output of which is connected to the word line of the memory cell array. The output signal WLDR (0;) of the word line drive signal predecode circuit in FIG.
3), / WLDR (0; 3) and FIG. 4 (c) show the output signal / RDC (0; 63) of the conversion signal decoding circuit.
Pch transistor 413 and Nch transistor 41
By controlling ON / OFF of 4, 415, "H" is sent to the selected word line, and the ground potential is sent to the other word lines.

The above is the circuit for driving the word line and the sense amplifier. The cell array selected by the bank address is driven by a closed circuit in the array. Therefore, the memory cell array constituting the block can be controlled regardless of the state of other memory cell arrays. Further, the activated state of the memory cell array is maintained until the memory cell array enters the precharged state.

FIG. 5 shows the details of the column switch selection control unit 205. The column switch selection control unit controls a switch system that connects the data line and the sense amplifier to exchange data with the activated cell array. FIG.
5A shows a switch control signal generation circuit, FIG. 5B shows a column address predecode circuit, and FIG. 5C shows a column address decode circuit.

In the switch control signal generating circuit shown in FIG. 5A, B0 to B3 are 4-bit bank addresses, each paired with an inverted signal thereof, and one of them is input to the NAND gate 501. You. That is, all the input signals to the NAND gate 501 of the array control unit in which the bank address given from the outside matches the bank address of the memory cell array corresponding to the array control unit become “H”, and the NAND gate 501 sends “L”. I do. The signal CENBi is sent to the sense control unit 2
03, which is a signal which becomes "H" in a state where the corresponding memory cell array has completed the sensing operation and the data is held in the sense amplifier. The signal ACC is a signal for determining the timing for controlling the column switch. The switch control signal generation circuit receives an activation signal ACC when a bank address of a corresponding memory cell array is input and the memory cell array is activated.
Becomes "H" at the timing when the signal SWONi becomes "H". At this time, the column switch of the corresponding memory cell array becomes operable. When the bank address of the corresponding memory cell array is not input, the signal SWONi becomes "L" and the column switch of this memory cell array does not operate. Also,
If the corresponding memory cell array is in a precharged state, CENBi goes to “L”.
ONi becomes "L", and the column switch of this memory cell array does not operate.

The column address predecoding circuit shown in FIG. 5B includes a NAND gate 506 having two bits of the column address as inputs and an inverter. CA
2, CA3 is paired with the inverted signal, and the NAND gate 502 having one of them as an input sends YA (0; 3) through the inverter.

In the column address decode circuit of FIG. 5C, the signal SWONi sent from the switch control signal generation circuit of FIG. 5A and the switch control signal generation circuit of the adjacent array control unit are supplied to the OR gate 503. The transmitted signal SWONi-1 is input. The output of this OR gate 503 and the NAND gate 504 shown in FIG.
The output signal Y of the column address predecode circuit of FIG.
A (0; 1) is input, and the signal CSS (0; 1) is transmitted via the inverter. Similarly, CSS
(2; 3) is generated. This signal CSS (0; 3) is a signal for controlling ON / OFF of four sets of column switches.

Each memory cell array has four column switch control signal lines. Further, since the present invention uses a shared sense system in which a sense amplifier is shared by both adjacent memory cell arrays, two control signal lines of the column switch are connected to the memory cell array and the memory cell array immediately before the memory cell array. Share the signal C
The two remaining memory cells are controlled by the signal CSS (2; 3), and are shared by the memory cell array and the memory cell array immediately after the memory cell array. The signal CSS (0; 1) is a signal SWONi that becomes “H” when the column switch of the corresponding memory cell array is controlled and “H” when the column switch of this memory cell array and one adjacent memory cell array are controlled. When one of the memory cell arrays controls the column switch, the signal YA (0; 1) is decoded and the control signal CSS (0; 1) for the column switch is sent out. Similarly, the column switch control signal CSS (2; 3)
Decodes YA (2; 3) and sends a column switch control signal CSS (2; 3) when one of the corresponding memory cell arrays and the other adjacent memory cell array controls a column switch. I do.

By inputting all the bits of the bank address to the input of the switch control signal generation circuit of FIG.
Even if a plurality of memory cell arrays are activated, only one memory cell array controls the column switch. This is because the memory cell arrays constituting the blocks have different addresses.

The operation of array control shown in FIG. 2 has been described above. The sense amplifier and column switch are controlled by signals transmitted from the array control unit, and the operation of reading data from the memory cell array is described. This will be described in detail with reference to FIG. FIG. 6 shows FIG. 1 in more detail.

The memory cell array MCAi is BL1,
/ BL1 has 1024 bit line pairs. Although not shown, 128 memory cells are actually connected to each bit line, and 256 memory cells are connected to one bit line pair, that is, one sense amplifier. Sense amplifier S / A1 to S
/ A4 is shared by the memory cell arrays on both sides thereof, and which of the memory cell arrays is connected is determined by the array selection gates Q1, Q2, Q3, Q4, Q5.
, Q6, Q7, Q8 are determined by ON / OFF. For example, if the memory cell array MCAi is selected, the array selection switch control signal SENi
Becomes H, and the array selection gates Q1, Q2, Q3
, Q4, Q5, Q6, Q7, Q8 are ON
And bit lines BL1, / BL1, BL2, / BL
2, BL3, / BL3, BL4, / BL4 are sense amplifiers S / A1, S / A2, S / A3, S
/ A4. At this time, the memory cell array MC
Since Ai-1 and MCAi-1 are not selected, the array selection switch control signals SENi-1 and SEN-1
i + 1 becomes L, and the array selection gates Q9, Q1
0, Q11, Q12, Q13, Q14, Q15, Q16
Is OFF. Thus, the bit line pair of the selected memory cell array is connected to the sense amplifier, and the sense amplifier is driven.

The restore / equalize unit R / E ensures that the H level of the bit line is properly rewritten with sufficient charge in the read cell, and that the bit line pair is equalized at the time of precharge to provide a reference for the sense operation. It generates a potential and is controlled by a signal BEQ output from a sense control circuit.

The sense amplifiers S / A1, S / A2, S
/ A3 and data determined to S / A4 are column switches Q17, Q18, Q19, Q20, Q21, Q22,
A pair of data buses D selected by Q23 and Q24
Connected to ATA and transferred.

Now, in the memory cell array MCAi, the bit lines BL1, / BL1, BL2, / BL2,
A case where a pair of data on BL3, / BL3, BL4, / BL4 is transferred to the data bus line DATA will be described. A memory cell array is selected, and although not shown, an arbitrary word line in memory cell array MCAi is selected. Since the memory cell array MCAi is selected, the array selection switch control signal SENi becomes "H", and the array selection gates Q1, Q2, Q3
, Q4, Q5, Q6, Q7, Q8 are ON
The bit lines BL1 and / BL1 are connected to the sense amplifier S / A
Connected to 1. Similarly, BL2, / BL2
Are connected to the sense amplifier S / A2, and BL3, / BL3 are connected to the sense amplifier S / A3, BL4, / BL4 are connected to the sense amplifier S / A4. At this time, MCAi
Since -1 and MCAi + 1 are not selected, the array selection switch control signals SENi-1 and SENi +
1 becomes "L", and the array selection gates Q9, Q1
0, Q11, Q12, Q13, Q14, Q15, Q16
Is OFF. When the sense amplifier S / A completes the sensing, the column switch control signals CSS (0; 1), C
SS (2; 3) is transmitted. Now, when the data of the bit lines BL1 and / BL1 is selected by the column address, CSS0 becomes "H" and CSS1 and CSS2
, CSS3 become L. Column switch control signal C
When SS0 becomes “H”, the transistors Q17 and Q19 constituting the column switch are turned on, and the sense amplifier S
The data held in / A1 is selected and transferred to the data bus pair DATA. At this time, the column switch control signals CSS1, CSS2, CSS3 become "L", so that the transistors Q18, Q19, Q20, Q2
1, Q22, Q23 and Q24 are turned off. As described above, by controlling the switches, any data in the memory cell array can be taken out to the data bus.

Next, a control method of the memory system of the present invention will be described with reference to the drawings, taking an actual configuration as an example.

As a first embodiment of the present invention, a width 128I
FIG. 7 shows a memory system configuration having a / O data bus. This memory system is composed of two blocks 701 and 702 similarly to the conventional memory system shown in FIG. 16, and each block has 16 memory cell arrays MCA0 to MCA15 each having a different bank address.
It is composed of MCA16 to MCA31. Each memory cell array has 256 rows × 1024 columns, and the total capacity of the memory system is 8 megabits.

In each of the upper and lower blocks 701 and 702, 16 memory cell arrays MCA0 to MCA1 are provided.
5, 256 data lines 704 and 705 connectable to the MCA 16 to MCA 31, respectively, in the bit line direction of the memory cell array. These data lines 70
4 and 705 are connected to column decoders 706 and 707, respectively.
An array control unit 703 is provided for each memory cell array, and a common array control signal is supplied to each array control unit (not shown). The memory cell arrays facing the upper and lower blocks have the same bank address.

When the bank address included in the array control signal matches the bank address of the corresponding memory cell array, array controller 703 activates the corresponding memory cell array according to the bank address and the row address. For example, when the bank addresses of MCA5 and MCA21 are input, the array control unit of MCA5 and MCA21 selects an arbitrary word line of MCA5 and MCA21 and controls the array selection switch to control the MCA5 and MCA21.
5. Connect the bit line of the MCA 21 to the sense amplifier. The data on the selected word line is sent to the sense amplifier and sensed (MCA5 and MCA21 are activated). Next, when the bank address included in the array control signal matches the bank address of the corresponding memory cell array, the array control unit 703 reads the data of the corresponding memory cell array according to the bank address and the column address. For example, for example, MCA5
When the bank address of MCA21 is input, MC
The array control unit of A5 and MCA21 is MCA5 and MCA21.
An arbitrary column switch of CA21 is turned ON / OFF, and the data sensed by the sense amplifier is transferred to the data line 70.
4, 705. The data lines 704 and 705 are input to column decoder circuits 706 and 707. Column decoder 7
Reference numerals 06 and 707 select 64 data lines from 256 data lines, respectively, and connect them to the data buses 708 and 709. (The data of MCA5 and MCA21 are read).

As described above, the data bus width is 64 I / O for each of the upper and lower sides, for a total of 128 I / O.

Next, the memory cell arrays MCA5, MCA
After reading the data of A21, MCA13, MCA2
The case where 9 data is read will be described.

First, data in the memory cell arrays MCA5 and MCA21 is read according to the above-described procedure. Thereafter, the activated state of the memory cell arrays MCA5 and MCA21 is held until the memory cell arrays are precharged. Next, the memory cell arrays MCA5, MCA
Regardless of the activation state of CA21, control unit 703 activates the corresponding memory cell array according to the array control signal. Since the bank addresses of the MCA 13 and the MCA 29 are input, the array control unit of the MCA 13 and the MCA 29 activates the MCA 13 and the MCA 29. At this time, the memory system has four activated memory cells M
CA5, MCA13, MCA21, and MCA29. Next, the array control unit 703 reads data from the corresponding memory cell array according to the array control signal. Since the bank addresses of MCA13 and MCA29 are input, the array control units of MCA13 and MCA29 read the data of MCA13 and MCA29.
At this time, since the bank addresses of the memory cell arrays MCA5 and MCA21 are not input, MCA5 and MCA5 are not input.
No data is sent out at 21.

As described above, each array control unit provided for each memory cell array controls the corresponding memory cell array irrespective of the state of the other memory cell arrays. MCA5, MCA21 activation → data reading → MCA13, MCA31 activation → data reading, and the precharge operation of the memory cell arrays MCA5, MCA21 becomes unnecessary.

The memory cell arrays MCA5, MCA
After reading the data of A21, MCA13, MCA2
9 is read, and thereafter, when the data of the memory cell arrays MCA5 and MCA21 is read again,
Memory cell arrays MCA5 and MCA21 are already activated.

As described above, each array control unit provided for each memory cell array can hold the activation state of the memory cell array until the memory cell array is precharged, so that when the memory cell array is read again, The read operation is MCA5, MCA21 activation → data read → MCA13, MCA31 activation → data read → data read, and the memory cell array MC
A5, the second activation operation of the MCA 21 becomes unnecessary.

As described above, in the memory system according to the first embodiment of the present invention, it is possible to freely activate memory cell arrays that are not adjacent to each other. The number of charges can be reduced.

Further, by setting the input of the array selection decoder circuit of the array control unit to some bits of the bank address, a plurality of memory cell arrays can be simultaneously activated in the same block. At this time, the array selection decoder circuit of the array control unit has the configuration shown in FIG.

For example, it is assumed that two memory cell arrays are simultaneously activated in each of the upper and lower blocks.
That is, MCA0, MCA8, MCA16, MCA
24 are simultaneously activated, and the same applies to other combinations of memory cell arrays.

When a part of the bank address included in the array control signal coincides with a part of the bank address of the corresponding memory cell array, the array control unit 703 determines the corresponding memory in accordance with the part of the bank address and the row address. Activate the cell array. For example, when some bank addresses of the memory cell arrays MCA5, MCA13, MCA21, MCA29 are input, the memory cell arrays MCA5, MCA13, MCA21, MCA29
Of the memory cell arrays MCA5, MCA
13, MCA21 and MCA29, select an arbitrary word line, and control an array selection switch to select MCA5, MCA5,
The bit lines of MCA13, MCA21 and MCA29 are connected to the sense amplifier. The data on the selected word line is sent to the sense amplifier and sensed (MCA5,
MCA13, MCA21, and MCA29 are activated). Next, when the bank address included in the array control signal matches the bank address of the corresponding memory cell array, the array control unit 703 reads the data of the corresponding memory cell array according to the bank address and the column address. For example, when the bank addresses of MCA5 and MCA21 are input, MCA5 and MCA21
The array control unit 21 turns on / off any column switch of MCA5 and MCA21, and sends out the data sensed by the sense amplifier to the data lines 704 and 705. The data lines 704 and 705 are connected to the column decoder circuit 70.
6, 707. The column decoders 706 and 707 select 64 data lines from 256 data lines, respectively, and connect them to the data buses 708 and 709. (MCA5
, MCA 21). At this time,
Since the bank addresses of the MCA 13 and the MCA 29 are not input, no data is transmitted to the MCA 13 and the MCA 29.

The memory cell arrays MCA5, MCA
While the activated states of A13, MCA21, and MCA29 are maintained, non-adjacent memory cell arrays, for example, memory cell arrays MCA0, MCA8, MCA16, M
It is also possible to activate CA24.

Memory cell arrays MCA0 to MCA15
Share the data line 704 and the memory cell array MCA1
6 to the MCA 31 share the data line 705, so that the upper and lower blocks 701 and 702 each have 256 data lines. Column decoders 706, 70
7 selects 64 data lines from 256 data lines and connects them to the data bus 708. This results in a total of 128 data buses in the upper and lower blocks. At this time, the number of data lines selected by the column decoders 706 and 707 is
It is determined by the number of I / O buffer circuits of the data lines provided in the circuit blocks of the column decoders 706 and 707. That is, when the width of the data bus output from the column decoders 706 and 707 is increased, the number of I / O buffer circuits provided for each output increases, and the occupied area increases. Conversely, column decoders 706 and 7
When the width of the data bus output from 07 is reduced, the number of I / O buffer circuits provided for each output is reduced, and the occupied area is reduced.

The number of memory cell arrays activated simultaneously is determined by the setting of the refresh cycle and the depth of the column. When two memory cell arrays are simultaneously activated in the same block, the refresh cycle and the column depth are as follows. Since two memory cell arrays are refreshed at the same time, all the memory cell arrays are activated in a time for activating eight memory cell arrays in 256 rows. That is, the refresh cycle is 256 × 8 = 2048
This is a refresh cycle.

Since two memory cell arrays are activated simultaneously in the same block, one data line is connected to eight bit line pairs. Column switch CSW
Selects one of the eight bit line pairs and connects it to the data line. Further, the column decoder selects one pair from the four pairs of data lines and connects it to the data bus. Therefore, the bit line pair connected to one I / O of the data bus is 8 × 4
= 32, and the column depth is 32. in this case,
This means a system of 2048 rows × 32 columns × 128 I / O.

As described above, by changing the number of memory cell arrays to be simultaneously activated, the configuration of rows and columns per I / O can be changed. For example, when four memory cell arrays are simultaneously activated, the refresh cycle is 256 × 4 = 1024 refresh cycles, and the column depth is 64. In this case, 1024
This means a system of rows × 64 columns × 128 I / O.

Next, as a second embodiment, a memory system configuration of a data bus having a width of 128 I / O is shown in FIG. 8, as in the first embodiment. This memory system is composed of four blocks 801 to 804, each of which has eight memory cell arrays MC having separate bank addresses.
A0 to MCA7, MCA8 to MCA15, MCA
16 to MCA23 and MCA24 to MCA31. Each memory cell array has 256 rows x 10
There are 24 rows and the total capacity of the memory system is 8 megabits.

The four blocks 801, 802, 803,
At 804, the eight memory cell arrays MCA0 to MCA0 to
MCA7, MCA8 to MCA15, MCA16 to M
There are 256 data lines 810, 812, 814, 816 connectable to CA23, MCA24 to MCA31, respectively, in the bit line direction of the memory cell array.
These data lines 810, 812, 814, 816 are connected to column decoders 806, 807, 808, 809. An array control unit 805 is provided for each memory cell array, and a common array control signal is supplied to each array control unit (not shown). The memory cell arrays facing the upper and lower blocks have the same bank address. In the left and right blocks, the memory cell arrays at the corresponding positions have the same bank address.

Since the array control unit 805 operates in the same manner as the array control unit 703 of the first embodiment described above, in the second embodiment, non-adjacent memory cell arrays can be sequentially activated in each block. It is. Further, it is possible to maintain the activated state. Therefore, as in the first embodiment, the number of activations and precharges can be reduced when reading between different memory cell arrays.

The refresh cycle of the memory system of this embodiment is 256 × 8 = 2048 refresh cycles. The column depth is 4 × 8 = 32 columns.
The system in this case is 2048 rows x 32 columns x 128 I /
The result is O, which is the same as the case of activating one memory cell array in the same block at the same time in the first embodiment.

In this embodiment, the length of the data bus line is shorter than that of the first embodiment, so that the data transfer speed is increased. In addition, since the number of memory cell arrays connected to the data bus line is reduced, charge and discharge of the charge by the stray capacitance is reduced, so that the drive current can be reduced.

In the memory system according to the present invention, 1024 rows × times as shown in the first or second embodiment are used.
64 columns x 128 I / O or 2048 rows x 32 columns x 12
Which of the 8 I / O configurations is selected depends on how data is exchanged with logic outside the memory. Generally, in a DRAM, it is known that the access time of a sense amplifier is shorter in a column than in a row. For example, if a request from a non-memory lodge can be satisfied by switching columns, the memory system may choose a configuration of 1024 rows x 64 columns x 128 I / O to reduce the number of rows selected at a time. desirable. On the other hand, when a request from logic outside the memory requires frequent row switching, the memory system selects a configuration of 2048 rows × 32 columns × 128 I / O, and the number of rows selected at a time is It is desirable to increase the number. As described above, in a memory system with embedded logic, it is necessary to select a more appropriate memory system in accordance with the requirements of the logic and the like outside the memory.

The case where the total capacity of the memory system of the first embodiment and the second embodiment of the present invention is 9 megabits will be described as a third embodiment and a fourth embodiment, respectively. Third
9 and 10 show a configuration of a memory cell system corresponding to the first embodiment of the third embodiment. In the upper and lower blocks 701 and 702 of the first embodiment, two new memory cell arrays (MCA16 and MCA17, MCA34 and M
CA35), a total of four memory cell arrays are added. First
The third embodiment differs from the third embodiment in the position of the cell array that is simultaneously activated. In the first embodiment, as shown in FIG. 7, the memory cell arrays are, for example, MCA0 and MCA8.
MCA16 and MCA24, MCA1 and MCA9 and MCA17 and MCA25, MCA2 and MCA10 and M
CA18MCA26, MCA3 and MCA11 and MCA
19 and MCA27, MCA4 and MCA12 and MCA2
0 and MCA28, MCA5 and MCA13 and MCA21
And MCA29, MCA6 and MCA14 and MCA22 and MCA30, MCA7 and MCA15 and MCA23 and M
Although activated for each bank of CA31, in the third embodiment, as shown in FIG. 9, MCA0, MCA9, and MCA
18 and MCA27, MCA1 and MCA10 and MCA1
9 and MCA28, MCA2 and MCA11 and MCA20
MCA29, MCA3 and MCA12 and MCA21 and MCA30, MCA4 and MCA13 and MCA22 and M
CA31, MCA5 and MCA14 and MCA23 and MC
A32, MCA6 and MCA15 and MCA24 and MCA
33, MCA7, MCA16, MCA25, and MCA3
4. MCA8, MCA17, MCA26 and MCA35
Will be activated.

One memory cell array has 256 rows × 10
Since there are 24 columns, a capacity of 0.5 Mbits is obtained with two memory cell arrays, so that the upper and lower blocks 901, 902
Respectively, one memory cell array MCA16, MCA34
Can be physically configured to form a memory cell array having a total capacity of 8.5 megabits. But,
Generally, such a configuration is not provided.

In this embodiment, the upper and lower blocks perform the same operation at the same time. Therefore, the operation of the upper block will be described as an example, and the description of the operation of the lower block will be omitted. The bank address of the added memory cell array is set to, for example, MCA
0, MCA8, and MCA16, three memory cell arrays are activated only when the bank address is designated, and two memory cell arrays are activated when other bank addresses are designated. . When the three memory cell arrays are activated, the column switch selects one pair from the 12 pairs of bit lines and connects to the data line. When the two memory cell arrays are activated, the column switch switches the eight pairs of bit lines. Is selected from the pair and connected to the data line, and the column depth differs for each bank address. Similarly, when the bank address of the added memory cell array MCA16 is newly set, only when the bank address is designated, 1
When one memory cell array is activated and other bank addresses are designated, two memory cell arrays are activated, and the column depth differs for each bank address. As described above, if the number of simultaneously activated memory cell arrays is inconsistent, the column depth changes, which causes non-uniformity in the address space in which the column depth varies depending on the activated memory cell array. Would. Therefore, it is necessary to increase or decrease the number of memory cell arrays in units of the number of memory cell arrays activated simultaneously in a block. This is because if the capacity is increased by the minimum unit in the memory system having the total capacity of 8 megabits shown in the first embodiment, the total capacity of the memory system becomes 9 megabits.

FIG. 10 shows the configuration of a memory cell system corresponding to the second embodiment of the fourth embodiment. Blocks 801, 802, 803, 804 of the second embodiment
The memory cell arrays MCA8, MCA17, MCA26, and MCA3 are newly added to each other for a total of four memory cell arrays.
Add 5 As described above, the number of memory cell arrays needs to be increased or decreased in units of the number of simultaneously activated cell arrays in a block. In this case, one memory cell array may be added to each block.

As can be seen from the third and fourth embodiments, even if the number of memory cell arrays is increased,
The width of / O can always be kept constant. Although not shown, even when the number of memory cell arrays is reduced, the width of the I / O can always be kept constant according to the above rules.

Hereinafter, more practical embodiments of the present invention will be described. In the embodiments described below, the array control section is not provided independently for each cell array, but is provided commonly to the upper and lower memory cell arrays, and the upper and lower cell arrays are activated in pairs. In this case, since the control circuit is shared by the two memory cell arrays, the degree of freedom in control is reduced, but a design with a margin in the chip area is possible.

As a fifth embodiment of the present invention, 128 I /
FIG. 11 shows the structure of a memory system having a memory capacity of 9 megabits. This memory system is composed of four blocks 1101 to 1104, each of which has nine memory cell arrays M having separate bank addresses.
CA0 to MCA8, MCA9 to MCA17, MC
A18 to MCA26 and MCA27 to MCA35. Each memory cell array has 256 rows x 1
024 columns, and the total capacity of the memory system is 9 megabits.

The four blocks 1101, 1102, 11
03 and 1104, nine memory cell arrays MCA
0 to MCA8, MCA9 to MCA17, MCA1
8 to MCA26 and data lines 1111, 1113, 1115, and 11 connectable to MCA27 to MCA35, respectively.
17 is 25 in the bit line direction of the memory cell array.
There are six. These data lines 1111, 1113, 1
115, 1117 are column decoders 1107, 1108, 1
109, 1110. An array control unit 1105 is provided for each of the upper and lower memory cell arrays, and a common array control signal is supplied to each array control unit (not shown). In the left and right blocks, the memory cell arrays at corresponding positions have the same bank address.

The array controller 1105 operates basically in the same manner as the array controller of the first embodiment described above. Therefore, in the fifth embodiment, the memory cell arrays which are not adjacent to each other in the left and right blocks are also provided. Can be sequentially activated in pairs. Further, it is possible to maintain the activated state.
Therefore, as in the first embodiment, the number of activations and precharges can be reduced when reading between different memory cell arrays.

As a sixth embodiment of the present invention, 64 I / Os,
Figure 1 shows the configuration of a memory system with a memory capacity of 8 megabits.
It is shown in FIG. This memory system has four blocks 12
The block is composed of eight memory cell arrays MCA each having a separate bank address.
0 to MCA7, MCA8 to MCA15, MCA1
6 to MCA23 and MCA24 to MCA31. Each memory cell array has 256 rows × 102
There are four rows and the total capacity of the memory system is 8 megabits.

Two blocks 1201, 1202 and 1
203 and 1204 share data buses BAS1 and BAS2 with a data width of 32 I / O, respectively, and a total of 64 I / Os.
Data bus. For example, when data of 32 I / O is taken out from the block 1201 and 32 I / O is taken out from the block 1203, MCA1, MCA3, MCA5, MC
A7 and MCA17, MCA19, MCA21, MCA
23 are activated, MCA9, MCA1
1, MCA13, MCA15, MCA25, MCA2
7, MCA29 and MCA31 are also activated at the same time,
The column switches in blocks 1202 and 1204 are all turned off, and no data transfer is performed. Conversely, when extracting data from blocks 1202 and 1204, all column switches in blocks 1201 and 1203 are OF switches
It becomes F. A block to which data is sent is determined according to the column address. In other words, the memory cell arrays corresponding to the upper and lower blocks respectively have upper one bits having different bank addresses. Further, all bits except the upper one bit of the bank address are input to the array selection decoder, and all bits of the bank address are input to the column switch selection control unit.

For example, the memory cell arrays MCA1, MCA3, MCA5, MCA7 and MCA17, MCA19, MCA21, MCA23, M
CA9, MCA11, MCA13, MCA15, MC
When A25, MCA27, MCA29, and MCA31 are activated simultaneously, half of all memory cell arrays are activated simultaneously.
The address configuration per row is 256 × 2 = 512 rows, and 32 × 4 × 2 = 25 since the memory cell arrays of the upper and lower blocks activated simultaneously correspond to one bit of the column address.
There are six columns. The number of bits required for each address is
The difference in the number of bits between row 9 bits and column 8 bits is 1 bit, and the difference between the row and column address configurations can be reduced.

FIG. 13 shows the configuration of a memory system in which each memory cell array operates asynchronously as a seventh embodiment of the present invention. Hereinafter, a combination of a plurality of memory cell arrays is referred to as a bank. For example, a memory cell array MCA
0 and MCA9 constitute a bank B0, and similarly, a total of 18 banks B1 to B17 are constituted. Each bank has a separate bank address. In the figure, the bank addresses are described in the array control units 1305 and 1306.

For example, asynchronously, B2, B5, B1
It is assumed that 6 is activated. This is because the memory cell array activated by the array control unit holds the activated state until it is precharged. Right 2
In one block 1303 and 1304, one bank B1
6, that is, since the MCA 25 and MCA 34 are activated, 64 I / O data is transferred from the bank B16. The configuration of this one bank is 64 I / O ×
256 rows x 32 columns. On the other hand, two blocks B2, B5,.
That is, MCA20, MCA29, MCA23, MCA
32 are activated, the two banks B2
, B5, 64 I / O data is transferred. Which bank the data is transferred from depends on which bank is specified at the time of data access. Even if a plurality of banks are activated in one block, data transfer is performed only from one bank in one access. As described above, the left 2
A total of 128 I / O data is transferred from the block and the two blocks on the right side by 64 I / O. At this time, the array control signal supplied to the array control unit 1305 shared by the two left blocks 1301 and 1302 and the array control signal supplied to the array control unit 1306 shared by the two right blocks 1303 and 1304 are signals indicating timing. Only the common signal is used, and other address signals are different signals.

When the memory capacity of the memory system is expanded, each of the blocks 1301, 1302,
13030 and 1304 include a memory cell array MCA36,
A bank B18 comprising an MCA 37 and an MCA 38,
A bank B19 composed of the MCA 39 can be added. In this embodiment, even when each bank has a bank address and a plurality of banks are activated in one block, data is transferred from one bank specified by the bank address, so that the memory capacity is Can be expanded in bank units.

FIG. 14 shows the relationship between the bank access signals of the memory system shown in the seventh embodiment. The signal ACT for activating the memory cell array, the signal PRC for precharging the array, the signal ACC for determining the timing for controlling the column switch, and the bank address,
The relation between the column address and the output data to be transmitted is shown. B0, B1, B2 on the timing chart
, B3 indicate that each signal is being sent to designate a respective bank. While the bank B0 is activated, a signal ACT1401 for activating the bank B1 is transmitted, and the bank B1 specified by the bank address 1405 is also activated. Next, a signal PRC1402 for precharging bank B0 is transmitted, and bank B0 specified by bank address 1406 enters a precharge state. Further, a signal ACT14 for activating bank B2 is provided.
03 is transmitted, the bank B2 specified by the bank address 1407 is activated, a signal ACT 1404 for activating the bank B3 is transmitted, and the bank B3 specified by the bank address 1408 is activated. An example of data access in each of these cases is shown below.

The shaded portion of the bank address indicates a period during which the address is not valid. As the output data, data of the specified column address is output from the specified bank after a predetermined time from the signal ACC. For example, bank B
When the signal ACC1409 for controlling the column switch of the bank B0 is transmitted in a state in which 0 is activated, the column switch specified by the column address of B0 specified by the bank address 1415 is controlled, Output data 1421 is sent out after a certain time.
Next, when the signal ACC1410 for controlling the column switch of the bank B1 is transmitted, first, the bank B1
Is activated, the column switch specified by the column address of B1 specified by the bank address 1416 is controlled, and the output data 1422 is output after a predetermined time.
Is sent. Next, when the signal ACC 1411 for controlling the column switch of the bank B2 is transmitted, since the bank B2 is activated first, the column switch designated by the column address of B2 designated by the bank address 1417 Is controlled, and the output data 1423 is sent out after a certain period of time. When the signal ACC1412 for controlling the column switch of the bank B1 is transmitted again, the bank B1 remains activated and is not in the precharge state.
The column switch specified by the column address of B1 specified by 8 is controlled, and the output data 1
424 is sent out. Thereafter, when the signal ACC1413 for controlling the column switch of the bank B2 is transmitted again, the output data 1425 is transmitted after a predetermined time since the bank B2 remains activated and not in the precharge state. . In this example, if there is a restriction on array activation by the shared sense method between banks, for example, if banks B1 and B2 are constituted by adjacent arrays, they will not be activated at the same time. Has no data output.

As described above, by activating several memory cell arrays at the same time, every time data of another memory cell array is accessed, each memory cell array is selected and the cell array can be activated. It is possible to omit the procedure of judging whether or not the memory cell array is selected based on the judgment result, and it is possible to access data only by controlling ON and OFF of the column switch, which leads to shortening of operation time. . Also, a signal ACC for controlling the column switch
For example, by synchronizing with the CPU clock,
In the logic embedded memory, data can be easily exchanged between the memory system and the logic circuit.

Although a bank may be composed of any number of memory cell arrays, FIG. 15 shows a case where a bank is composed of four memory cell arrays as an eighth embodiment. Total memory capacity is 8M and 256K cell array 3
It consists of two pieces. The whole has an eight-bank configuration, and a memory cell array is allocated to the banks B1 to B8 as shown in the figure. In the figure, the array control unit 1
Reference numeral 505 describes the bank address. The bank allocation of the memory cell array has a restriction that adjacent memory cell arrays cannot be allocated to the same bank because the sense amplifier is shared with both adjacent memory cell arrays. However, other than this, the allocation pattern can be freely selected. Also in this case, similarly to the seventh embodiment, the two right blocks 1501 and 1502
And the array control unit 1505 shared by the two blocks 1503 and 1504 on the left.
6, a common timing signal and a different address signal are supplied. In the two blocks on the right side, the bank B8 is activated, and 64 I / O data is transferred from one of the two pairs of memory cell arrays according to the column address. In the two blocks on the left, banks B1 and B3 are activated, and a bank is specified by a bank address from one of the four pairs of memory cell arrays, and 64 I / O data is transmitted from a memory cell array pair selected according to a column address. You. In this case, the address configuration of one bank is 64 I / O × 256 rows × 64 columns.

As described above, the time required for data access can be reduced by simultaneously activating a plurality of banks in the bank configuration. Even in the case of the present embodiment, the blocks 1501 and 1502 are synchronized with only the timing signal for exchanging data with the memory cell, so that 128 I /
O output data can be obtained.

The number of memory cell arrays to form one bank is determined by the number of columns per bank. One set of upper and lower memory cell arrays
When a bank is formed, in a memory system having a data width of 128 I / O, it is possible to increase or decrease the memory capacity in megabit units by adding a pair of memory cell arrays on both sides of the left and right blocks. Therefore, an M megabit memory system has M pairs of memory cell arrays in both blocks. As a result, the number of rows and the number of columns are determined as follows as an address configuration that can be realized by this memory system.

Number of rows L = 256 × M / m Number of columns C = 32 × m Here, m represents the number of memory cell array pairs activated simultaneously in a block, and is a divisor of M (including 1 and excluding M). Becomes

When a bank is constituted by this memory system, the feasible number of banks is as follows for each block.

Bank number B = M / m Here, when B is 4 or more, M / m can be set. When B is 3 or less, a bank cannot be formed because the adjacent cell arrays cannot be simultaneously activated. Bank number is M / m
In this case, the number of banks that can be activated simultaneously is a number up to M / 2m or the maximum integer not exceeding M / 2m. Increasing the number of activated memory cell arrays within these restrictions reduces the data access time.

[0105]

According to the present invention, the present invention is applied to a memory system having an overlaid bus structure which can keep the data bus width constant regardless of the number of memory cell arrays or the number of activated memory cell arrays. Since the plurality of memory cell arrays can be activated and precharged irrespective of the state of other memory cell arrays, and the activated memory cell array can maintain its activated state until it is precharged, High-speed reading from the memory cell array becomes possible.

[Brief description of the drawings]

FIG. 1 is a diagram showing a basic configuration around a memory cell array of a semiconductor memory device of the present invention.

FIG. 2 is a diagram showing a circuit configuration of an array control unit of the semiconductor memory device of the present invention.

FIG. 3 is a diagram showing a circuit configuration of an array selection decoder of the array control unit shown in FIG. 2;

FIG. 4 is a diagram showing a circuit configuration of a word line decoder of the array control unit shown in FIG. 2;

5 is a diagram showing a circuit configuration of a word line column switch selection control unit of the array control unit shown in FIG. 2;

FIG. 6 is a diagram showing a circuit configuration around a memory cell array of the semiconductor memory device of the present invention.

FIG. 7 is a diagram showing a configuration of a memory system according to a first example of the present invention.

FIG. 8 is a diagram showing a configuration of a memory system according to a second embodiment of the present invention.

FIG. 9 is a diagram showing a configuration of a memory system according to a third embodiment of the present invention.

FIG. 10 is a diagram illustrating a configuration of a memory system according to a fourth embodiment of the present invention.

FIG. 11 is a diagram showing a configuration of a memory system according to a fifth embodiment of the present invention.

FIG. 12 is a diagram showing a configuration of a memory system according to a sixth embodiment of the present invention.

FIG. 13 is a diagram illustrating a configuration of a memory system according to a seventh embodiment of the present invention.

FIG. 14 is a diagram showing an example of timing when the memory system of the present invention is operated asynchronously.

FIG. 15 is a diagram showing a configuration of a memory system according to an eighth embodiment of the present invention.

FIG. 16 is a diagram showing a basic configuration around a memory cell array of a conventional semiconductor memory device.

FIG. 17 is a diagram showing a configuration of a conventional memory system.

[Explanation of symbols]

MCA1, MCA2, MCA3
The memory cell arrays MCAi-1, MCAi, MCAi + 1,
Memory cell arrays BL1, BL2, BL3, BL4, BL
Bit lines CTRL1, CTRL2, CTRL3
Array control unit CTRLi-1, CTRLi, CTRLi + 1
Array controller S / A1, S / A2, S / A3, S / A4, S
/ A Sense amplifiers ASW1, ASW2, ASW3, ASW4, A
SW array selection switch CSW1, CSW2, CSW
Column switch BAS, BAS0 to BAS255
Data line S / A1 to S / A4
Sense amplifier R / E1 to R / E8
Restore / equalize circuit BL1, / BL1 to BL4, / BL4
Bit line pair DATA
Data line pair

Claims (17)

[Claims] At least three data holding devices having mutually different bank addresses, a plurality of data amplification / transfer buffers provided corresponding to the data holding devices and divided into a plurality of groups, A plurality of data lines provided so as to be commonly coupled to corresponding data amplification transfer buffers in the group; and a plurality of data lines provided corresponding to each of the data holding devices, wherein a predetermined number of data lines are provided based on a control signal. Sending the data from the output terminal to the corresponding data amplification / transfer buffer, then transmitting the data in the corresponding data amplification / transfer buffer to the corresponding data line, and then presetting the data amplification / transfer buffer Semiconductor device comprising: 2. The data amplification / transfer buffer, during a period from when data is transmitted from a predetermined output terminal of a data holding device to the data amplification / transfer buffer to when the data amplification / transfer buffer is preset, is provided. 2. The semiconductor device according to claim 1, wherein 3. The control signal includes a bank address, a row address, and a column address, and the control unit amplifies an output terminal of a data holding device associated with the data terminal based on the bank address and a part of the row address. A transfer buffer for transmitting the data of the data holding device to the data amplification transfer buffer; thereafter, connecting the data amplification transfer buffer to the data line based on the bank address and the column address, and 3. The semiconductor device according to claim 2, wherein said data in a transfer buffer is sent to said data line. 4. The data holding device has a data holding body, wherein the control signal includes a bank address, a row address, and a column address, and the bank address matches at least a part of a bank address of the data holding body. In the case, the control unit connects the output terminal of the associated data holding device to the data amplification transfer buffer based on the row address, and sends the data of the data holding device to the data amplification transfer buffer, and further thereafter, If the bank address matches the bank address of the data holding device, the data amplification transfer buffer is connected to the data line based on the column address, and the data in the data amplification transfer buffer is transmitted to the data line. The semiconductor device according to claim 2. 5. The data holding device has a data holding body, the control signal is a bank address, a row address, a column address, a signal indicating a timing for activating the data holding device, and the data holding device is preset. A signal indicating the timing of setting the state, and a signal indicating the timing of transmitting the data of the data amplification transfer buffer to the data line, and determining whether the data holding device transmitted by the adjacent control unit is activated. A signal indicating the bank address, at least a part of the bank address, the row address and the timing signal for activating a data holding device.
The control unit connects an output terminal of an associated data holding device to the data amplification transfer buffer, sends data of the data holding body to the data amplification transfer buffer, and then transmits the bank address, column address and Connecting the data amplification transfer buffer to the data line based on the timing signal for transmitting the data amplification transfer buffer data to the data line, and transmitting the data amplification transfer buffer data to the data line; 3. The semiconductor device according to claim 2, further comprising: setting the associated data holding device to a preset state based on the bank address and the timing signal for setting the data holding device to a preset state. 6. The data holding device has a data holding body, the control signal is a signal indicating a timing for activating the data holding device, a signal indicating a timing for setting the data holding device to a preset state, and the data A signal indicating a timing of transmitting data in the amplification transfer buffer to the data line, the control unit includes a signal transmitted by an adjacent control unit and indicating whether or not the data holding device is activated. An output terminal of an associated data holding device is connected to the data amplification transfer buffer based on a signal indicating a timing for activating the data holding device, and data of the data holding body is sent to the data amplification transfer buffer. ,afterwards,
The data amplification transfer buffer is connected to the data line based on the signal indicating the timing of transmitting the data amplification transfer buffer data to the data line, and the data amplification transfer buffer data is transmitted to the data line. And
3. The semiconductor device according to claim 2, further comprising setting the associated data holding device to a preset state based on a timing signal for setting the data holding device to a preset state. 7. The semiconductor device according to claim 6, wherein the signal indicating a timing at which data of the data amplification transfer buffer is transmitted to the data line is synchronized with an external clock signal. 8. A semiconductor device comprising at least two blocks, wherein each block is provided corresponding to at least three data holding devices having mutually different bank addresses and a plurality of groups. A plurality of divided data amplification transfer buffers, a plurality of data lines provided such that each is commonly coupled to a corresponding data amplification transfer buffer in each of the groups; and A control unit that controls the data holding device based on a control signal and sends data of an associated data holding device to a corresponding one of the corresponding data lines based on the control signal. Semiconductor device. 9. The control unit includes a timing signal indicating a timing at which data of the data amplification transfer buffer is transmitted to the data line, and the timing signal is synchronized with all of the control units. 13. The semiconductor device according to claim 1. 10. A data bus shared by the blocks, the number of data buses being smaller than the number of data lines in each of the blocks, and provided in each of the blocks and connected to the data bus from the data lines. 9. The semiconductor device according to claim 8, further comprising a decoder for selecting a data line to be applied. 11. The semiconductor device according to claim 8, wherein said control signal is common to all of said blocks. 12. The semiconductor device according to claim 11, wherein each of said blocks includes a column decoder for selecting said data line. 13. The semiconductor device according to claim 11, wherein said first block includes a column decoder for selecting said data line. 14. A semiconductor device comprising at least two blocks, each block being provided corresponding to at least three data holding devices having different bank addresses and a plurality of groups. A plurality of divided data amplification transfer buffers, a plurality of data lines each provided so as to be commonly coupled to a corresponding data amplification transfer buffer in each group, and a plurality of control units, Each control unit is provided between the blocks, controls the data holding device of each block based on a control signal, and further stores data of a corresponding holding device of the data holding device of each block based on a control signal. A semiconductor device comprising: a plurality of control units for transmitting data to a corresponding one of the corresponding data lines. 15. The data amplification transfer buffer, wherein the control unit connects a selected output terminal of an associated holding device to the data amplification transfer buffer, and sends data on the output terminal to the data amplification transfer buffer. 15. The semiconductor device according to claim 14, wherein the transfer buffer holds the data until preset. 16. A data bus provided for each of the blocks and having a number smaller than the number of data lines in each block, and a data bus provided for each of the blocks and connected to the data bus from the data lines. 15. A decoder for selecting a data line to be connected.
13. The semiconductor device according to claim 1. 17. A semiconductor device comprising at least two blocks, wherein each block is provided corresponding to at least three data holding devices having different bank addresses from each other and includes a plurality of groups. A plurality of divided data amplification transfer buffers, a plurality of data lines provided so as to be commonly coupled to corresponding data amplification transfer buffers in each of the groups, and a plurality of data lines provided between the blocks; A semiconductor device comprising: a plurality of control units that control the data holding device of each block based on a signal and transmit data of the data holding device of each block to the corresponding data line based on a control signal.