JP2002233158A - High-efficiency adaptive dc-to-ac converter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a system optimized for driving a load. SOLUTION: A DC-to-AC converter circuit transmits power to a load 20 while performing its control, and is provided with a power source 12, a plurality of switches A to D, a pulse generator 22, a drive circuit 50 for controlling the conducting states of the switches A to D, a transformer TX1, the load 20, and a feedback loop circuit. The drive circuit 50 controls overlapping time intervals among the plurality of switches in a first set, as well as the overlap time intervals among the plurality of switches in a second set, so as to consequently control the power supplied to the load.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a DC to AC power converter. More specifically, the present invention provides a high efficiency controller circuit that uses zero voltage switching technology to control the power delivered to the load. A general application of the present invention is in cold cathode fluorescent lamps (CCFLs).
s). However, those skilled in the art will appreciate that the present invention is applicable to any load where high efficiency and accurate power control is required.

[0002]

2. Description of the Related Art FIG.
Is a conventional CCFL power supply system (1
0). The system generally comprises a power supply (1
2), CCFL drive circuit (16), controller (14), feedback loop (18), LCD
One or more lamps with panels (20) (CCFL)
And The power supply (12) supplies a DC voltage to the circuit (16). The circuit (16) is controlled by the controller (14) via the transistor (Q3). The circuit (16) is a self-resonant circuit known as a Royer circuit. In essence, the circuit (16) is a self-resonant DC to AC converter, the resonance frequency of which is set by L1 and C1. N1 to N4
Represents the number of turns of the transformer winding. In operation,
Transistors (Q1, Q2) alternately conduct to switch the input voltage across each of the windings (N1, N2). When the transistor (Q1) is conducting,
An input voltage is applied across the winding (N1). A voltage of the corresponding polarity will be applied to the other windings. The voltage induced in the winding (N4) is such that the base of the transistor (Q2) is positive and the voltage of the transistor (Q1)
Conducts with a very small collector-emitter voltage drop. The voltage induced in the winding (N4) is
The transistor (Q2) is kept off. Transistor (Q1) conducts until the magnetic flux in the core of transformer (TX1) reaches saturation.

At saturation, the collector voltage of transistor (Q1) rises sharply (to a value determined by the base circuit) and the voltage induced in the transformer sharply decreases. Transistor (Q1) goes out of saturation, V _CE rises, and the voltage across winding (N1) further decreases. The reduced base drive turns off transistor (Q1), which causes a slight decrease in the magnetic flux in the core, inducing current in winding (N4) and turning on transistor (Q2). The voltage induced in winding (N4) keeps transistor (Q2) in saturation conduction until the core saturates in the opposite direction.
Until the switching cycle is completed, the same and opposite operations are performed.

[0004] Although the inverter circuit (16) is made up of a relatively small number of components, the proper operation of the circuit depends on the complex non-linear interaction between the transistor and the transformer. ing. In addition, C1, Q
Due to the error in 1, Q2 (typically 35% tolerance), circuit (16) cannot be applied to a parallel transformer configuration. The reason for this is that the superposition of the circuit (16) generates additional undesirable operating frequencies that resonate at some harmonic frequency. When applied to a CCFL load, the circuit will
This causes a “beat” to the FLs. This is a noticeable and undesirable phenomenon. Even though the tolerances are closely matched, beat phenomena are eliminated because the superposition of the circuit has an inherent operating frequency, because the circuit (16) operates in a self-resonant mode. Can not do.

Some other drive systems are disclosed in US Pat. No. 5,430,641, US Pat.
No. 619,402, US Pat. No. 5,615,09.
No. 3, U.S. Pat. No. 5,818,172. Each of these documents is of low efficiency, of two-stage power conversion, of frequency variation type and / or of load dependent type. In addition, if the load is one or more CCFs
If L and the assembly are provided, stray capacitance is introduced and adversely affects the CCFL's own impedance. In order to effectively construct a circuit that can operate properly, the circuit must have a CCFL
It must be configured in consideration of the stray impedance for driving the load. Such efforts are not only time consuming and expensive, but also make it difficult to obtain an optimal converter configuration when handling various loads. Therefore, a circuit means capable of overcoming the above-mentioned drawbacks, being highly efficient, capable of performing reliable ignition of CCFLs, performing load-independent power control, and performing power conversion with a single frequency. Was requested.

[0006]

SUMMARY OF THE INVENTION Accordingly, the present invention provides
An object of the present invention is to provide a system optimized for driving a load, and to obtain optimum operation of various LCD panel loads, thereby improving the reliability of the system.

Broadly speaking, the present invention is a DC / AC converter circuit for controlling and transmitting power to a load, the circuit being selectively connected to an input voltage source; A first set of a plurality of overlapping switches and a second set of a plurality of overlapping switches, wherein the first set of switches forms a first conductive path; A first set of overlapping switches and a second set of overlapping switches, wherein the two sets of switches form a second conductive path. A converter circuit is provided.
A pulse generator for generating a pulse signal is provided. The drive circuit receives the pulse signal and controls the conductive state of the first and second sets of switches. It has a primary side and a secondary side, and the primary side has a first side.
A transformer is provided, wherein the voltage source is selectively connected by alternately passing through the conductive path and the second conductive path. The load is connected to the secondary side of the transformer. The feedback loop circuit is disposed between the load and the drive circuit, and supplies a feedback signal representing power supplied to the load. The drive circuit alternately switches the conductive state of the first set and the second set of switches to control the overlap time between the plurality of switches in the first set and to control the overlap time between the plurality of switches in the first set. Controls the overlap time between the plurality of switches, thereby connecting the voltage source to the primary based at least in part on the feedback signal and the pulse signal.

The driving circuit is configured to generate a first complementary pulse signal from the pulse signal and to generate a gradient signal from the pulse signal. The pulse signal is supplied to a first switch of a plurality of switches forming a first set, and is used for controlling a conduction state of the first switch. The ramp signal is compared with at least a feedback signal. , A second pulse signal is generated, whereby the overlap state between the conduction state of the first switch and the conduction state of the second switch of the first set of switches is controlled. I have. The second pulse signal is supplied to a second switch among the plurality of switches forming the first set, and is used for controlling the conduction state of the second switch. The drive circuit further generates a second complementary pulse signal based on the second pulse signal, wherein the first and second complementary pulse signals are used by a first switch and a second switch of a second set of a plurality of switches. Are controlled in a conductive state. Similarly, the overlap state between the conduction state of the first switch and the conduction state of the second switch of the second set of the plurality of switches is controlled.

In a method aspect, the present invention provides a method for performing control using a zero voltage switching circuit in transferring power to a load.

In this case, a DC voltage source is provided; a first transistor and a second transistor for forming a first conductive path are connected to the voltage source and a primary side of the transformer, and the voltage source and the primary transistor are connected to each other. The secondary to the primary side of the transformer
A third transistor and a fourth transistor for forming a conductive path;
Connecting a transistor; generating a pulse signal having a predetermined pulse width; connecting a load to a secondary side of a transformer; generating a feedback signal from the load; controlling the feedback signal and the pulse signal By doing so, the conduction state of the first transistor, the second transistor, the third transistor, and the fourth transistor is determined.

In the first embodiment, the present invention
A converter circuit for transmitting power to an FL load, comprising: a voltage source; a transformer having a primary side and a secondary side; a first conductive path between the voltage source and the primary side. A first pair of switches, and a second pair of switches forming a second conductive path between the voltage source and the primary; a CCFL load circuit connected to the secondary; A pulse generator for generating a pulse signal; a feedback circuit coupled to the load for generating a feedback signal; receiving the pulse signal and the feedback signal, and providing power to the CCFL load. A driving circuit for connecting the first pair of switches or the second pair of switches to the voltage source and the primary side based on the pulse signal and the feedback signal so that they can be supplied. To provide a converter circuit to Bei.

In addition, the first embodiment provides a pulse generator that generates a pulse signal having a predetermined frequency. The drive circuit includes a first drive circuit, a second drive circuit, a third drive circuit, and a fourth drive circuit, wherein a first pair of switches has a first transistor and a second transistor, and Has a third transistor and a fourth transistor. A first drive circuit,
A second drive circuit, a third drive circuit, and a fourth drive circuit are connected to control lines of the first transistor, the second transistor, the third transistor, and the fourth transistor. The pulse signal is supplied to a first driving circuit, whereby the first transistor
Switching is performed according to the pulse signal. The third driving circuit generates a first complementary pulse signal and a ramp signal based on the pulse signal, and further supplies the first complementary pulse signal to the third transistor, so that the third transistor generates the first complementary pulse signal. Switching is performed according to one complementary pulse signal. The second pulse signal is generated by comparing the tilt signal and the feedback signal. The second pulse signal is supplied to the second driving circuit, and thereby the second
The transistor is switched according to the second pulse signal. The fourth driving circuit generates a second complementary pulse signal based on the second pulse signal, and further supplies the second complementary pulse signal to the fourth transistor, so that the fourth transistor generates the second complementary pulse signal. Switching is performed according to the pulse signal. In the present invention, each of the simultaneous conduction between the first transistor and the second transistor and the simultaneous conduction between the third transistor and the fourth transistor controls the power supplied to the load. It has become. The pulse signal and the second pulse signal are generated so as to overlap by a predetermined amount, whereby power is supplied to the load through the first conductive path. The first complementary pulse signal and the second complementary pulse signal are generated from the pulse signal and the second pulse signal, respectively, so that both the first complementary pulse signal and the second complementary pulse signal exceed a predetermined amount. Wrapping, so that the first conductive path alternates with the second conductive path
Power is supplied to the load through the conductive path.

The pulse signal and the first complementary pulse signal are generated with a phase difference of about 180 °, and the second pulse signal and the second complementary pulse signal are generated with a phase difference of about 180 °. This prevents the occurrence of a short circuit between the first conductive path and the second conductive path.

[0014] In addition to the converter circuit provided in the first embodiment, in the second embodiment, the second drive is connected to the second pulse signal only when the third transistor is switched to the conductive state. A flip-flop circuit for supplying a second pulse signal to the circuit is provided. In addition, the second embodiment includes a phase locked loop (PLL) circuit having a first input signal from the primary side and a second input signal using a feedback signal. The PLL circuit compares a phase difference between the first input and the second input, and transmits a control signal to the pulse generator to control a pulse width of the pulse signal based on the phase difference.

In both embodiments, the preferred circuit includes a feedback control loop having a first comparator for comparing the feedback signal and the reference signal to generate a first output signal. A second comparator is provided for comparing the first output signal and the ramp signal and generating a second output signal based on an intersection between the first output signal and the ramp signal. Further, the feedback circuit preferably includes a current detection circuit for receiving the feedback signal and generating a trigger signal, and a switch circuit between the first comparator and the second comparator. , Receiving a trigger signal and generating either a first output signal or a predetermined minimum signal based on the value of the trigger signal. The reference signal may be, for example, a signal that is manually generated to indicate the desired power to be provided to the load. The predetermined minimum voltage signal may be a programmable minimum voltage supplied to the switch, so that no overvoltage is applied to the load.

Similarly, in both embodiments, an overcurrent protection circuit that receives a feedback signal as an input and controls the pulse generator based on the value of the feedback signal can be provided. An overvoltage protection circuit is provided for receiving the voltage signal applied to the load and the first output signal, comparing the voltage signal with the first output signal, and controlling the pulse generator based on the value of the voltage signal applied to the load. it can.

[0017]

BEST MODE FOR CARRYING OUT THE INVENTION In the following detailed description, reference will be made to preferred embodiments and preferred methods of use, but it is to be understood that the invention is not limited to these preferred embodiments and preferred methods of use. ,
Those skilled in the art will understand. Rather, the invention has a broad scope and is limited by the appended claims.

Other features and advantages of the present invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawings.

Although not intended to limit the present invention by way of example, the following detailed description refers to a CCFL panel as a load on a circuit according to the present invention. However, the present invention is not limited to driving one or more CCFLs and should be viewed as a general power converter circuit and method that is not limited to a particular load in a particular application. .

In overview, the present invention provides a circuit for controlling power supply to a load by adjusting the on-time of two pairs of switches using a feedback signal and a pulse signal. Things. When the turn-on of one pair of switches is controlled such that their on-times overlap each other, power is transmitted through a conductive path formed by the one pair of switches (transformer). (Via a vessel). Similarly, when the turn-on of the other pair of switches is controlled such that their on-times overlap each other, the power is:
It is supplied to the load (via a transformer) via a conductive path formed by the other pair of switches. Thus, by selectively turning on the switches and by controlling the overlap between the switches, the present invention can accurately control the power supplied to a given load. In addition, the present invention is provided with an overcurrent protection circuit and an overvoltage protection circuit for shutting off power supply to the load when a short circuit or an open circuit occurs. Furthermore, the switching control scheme described herein allows the circuit to operate at a single operating frequency regardless of the load and regardless of the transformer configuration resonance. These features will be described below with reference to the accompanying drawings.

The circuit diagram shown in FIG. 2 shows a preferred embodiment of a phase shift type full-wave bridge type zero voltage switching type power converter according to the present invention.
In essence, the circuit shown in FIG. 2 comprises a power supply (12), a plurality of switches (80) arranged as diagonal pairs of switches forming an alternating conduction path, and a circuit for driving each switch. Circuit (50) and a frequency sweeper (22) for supplying a rectangular wave pulse to the drive circuit (50)
And a transformer (TX1) (with a resonance tank circuit formed by the primary side of the transformer (TX1) and the capacitor (C1)) and a load. Advantageously, the present invention further comprises an overlap feedback control loop (40) for controlling the on-time of at least one of the plurality of switch pairs, thereby enabling control of the power supply to the load. I have.

The power supply (12) is applied to the system. First, the bias / reference signal (30)
Is generated from the power supply for the control circuit (for the control circuit in the control loop (40)). Preferably,
The frequency sweeper (22) starts at the maximum frequency and sweeps downward at a predetermined speed and a predetermined number of stages (that is, a rectangular wave signal having a variable pulse width).
% Of the load ratio cycle pulse signal. The frequency sweeper (22) is preferably a conventionally known programmable frequency generator. (Sweeper (2
The pulse signal (90) (from 2) is supplied to the B_drive (the drive for driving switch_B, ie the drive for controlling the gate of switch_B) and then to the A_drive Supplied.
The A_drive generates a complementary pulse signal (92) and a ramp signal (26). As described below, the complementary pulse signal (92) has a phase of about 180 with the pulse signal (90).
The tilt signal (26) is shifted by about 90 ° from the pulse signal (90). The tilt signal is preferably a sawtooth signal as shown in the figure. The slope signal (26) is output to an output signal (24) from the error amplifier (32) (here,
CMP). Thereby, a signal (94) is generated. The output signal (94) from the comparator (28) is also a 50% duty cycle pulse and is provided to the C_drive. Thereby, the turn-on of the switch_C is started, and the overlap amount between the switches B and C and between the switches A and D are determined. Complementary signal of signal (94) (phase 1
(A signal shifted by 80 °) is supplied to the switch_D via the D_drive. Those skilled in the art will recognize that the A_drive to D_drive are connected to the control lines (ie, gates) of switches_A to switch_D, respectively, so that conduction of each switch can be controlled as described below. You will understand. Switch B,
By adjusting the amount of overlap between C and between switches A and D, control of the lamp current is obtained. In other words, it is the amount of overlap in the conducting state of the plurality of pairs of switches that determines the amount of power processed by the converter. Therefore, the switches B and C and the switches A and D are hereinafter referred to as overlapping switches.

By way of example and not limitation, in this embodiment, the B_drive is preferably formed from a totem-pole circuit, a common low-impedance operational amplifier circuit, or an emitter-follower circuit. Have been. The C_ drive is similarly configured. Due to the fact that A_drive and D_drive are not directly grounded (i.e., floating), they can be bootstrapped or other high side drive circuits (high level), as known to those skilled in the art. Side drive circuit). In addition, as described above, the A_drive and the D_drive each include an inverter that inverts (that is, inverts the phase of) a signal flowing from each of the B_drive and the C_drive.

High efficiency operation is obtained with zero voltage switching technology. Four MOSFETs (switch_A
-Switch_D) (80) is turned on after the respective intrinsic diodes (D1-D4) conduct.
This provides a current flow path for energy in the transformer / capacitor (TX1 / C1) configuration, thus ensuring that the voltage across the switches is zero voltage as each switch turns on. In such a control scheme, switching losses are minimized and high efficiency is maintained.

A preferred switching operation of the overlap switch (80) is shown in FIGS. 3 (a) to 3 (f). Switch_C is turned off a predetermined period after both switches_B and C have become conductive. The current flowing in the tank (see FIG. 2), at this point when switch_C is turned off, the diode (D4) in switch_D (FIG. 3 (e)), the primary side of the transformer and the capacitor (C1) And switch_B,
Flow through. This causes resonance of voltage and current in the capacitor (C1) and the transformer as a result of the energy supplied when the switches _B and C were conducting (FIG. 3 (f)). Note that this situation must occur because the instantaneous change in the current direction on the transformer primary disrupts the Faraday law. Thus, when switch_C turns off, current must flow through diode (D4). Similarly, switch_B is turned off (FIG. 3 (a)) and current flows through the diode (D1) associated with switch_A (FIG. 3 (e)) before switch_A is turned on. Similarly, switch_D is turned off (FIG. 3 (d)), and current flows from switch_A in this case via capacitor (C1), the primary side of the transformer, and diode (D3). Flowing. After the diode (D3) is turned on (FIG. 3 (e)), the switch_C is turned on. After switch_A is turned off, switch_B is turned on. In this case, the diode (D2) can be turned on before the switch_B is turned on. Note that the overlap of the turn-on times of the diagonal switches B, C and A, D is determined by the energy to be supplied to the transformer, as shown in FIG.

In this embodiment, FIG.
It shows that the ramp signal (26) is only generated when switch_A is turned on. Therefore, the A_drive that generates the ramp signal (26) preferably includes a constant current generation circuit (not shown). The constant current generation circuit includes a capacitor having an appropriate time constant so as to generate a gradient signal. For this purpose, a reference current (not shown) is used to charge this capacitor. The capacitor is grounded (e.g., via a transistor switch) such that the discharge rate is greater than the charge rate, thereby producing a sawtooth ramp signal (26). Of course, as described above, the ramp signal can be obtained by integrating the pulse signal (90). Therefore, the inclination signal (26) is
It can be formed using an integrating circuit (for example, an operational amplifier and a capacitor).

During the ignition period, the overlap between the two diagonal switches (ie, switches A and D)
Overlap between switches B and C) is a predetermined minimum overlap. This gives minimal energy from the input side to the tank circuit including the capacitor (C1), the transformer, the capacitors (C2, C3) and the CCFL load. Note that the load can be a resistive load, a capacitive load, or a combination of these loads. The drive frequency starts at a predetermined maximum frequency and approaches the resonance frequency of the tank circuit and the equivalent circuit reflected by the secondary of the transformer. Most of the energy is delivered to the load to which the CCFL is connected. Due to the high impedance characteristics before ignition, the CCFL receives a high voltage from the energy supplied to the primary. This voltage is large enough to ignite the CCFL. The impedance of the CCFL is usually the operating value (for example, about 100 KΩ to 130 K).
Ω). The energy delivered to the primary based on the minimum overlap operation is no longer sufficient to maintain steady state operation of the CCFL. The output from the error amplifier (26) initiates its function to increase the overlap. In this case, it is the output level from the error amplifier that determines the amount of overlap. For example, it is as follows.

As shown in FIGS. 3 (b) and 3 (c) and the feedback loop (40) of FIG. 2, the ramp signal (26) (generated by the A_drive) is
Note that when equalized by the value of the MP signal (24) (generated by the error amplifier (32)) by the comparator (28), the switch_C is turned on. is important. This is shown as intersection point (36) in FIG. 3 (b). To avoid short circuits, switches A and B and C and D must never be on at the same time. By controlling the CMP level, switches A,
The overlap time between D and B, C controls the energy delivered to the transformer. To regulate the energy delivered to the transformer (and thereby to regulate the energy delivered to the CCFL load), the output from the error amplifier, CMP,
By controlling (24), the switches C and D are
Switches A and B are shifted in time. As can be understood from the timing chart, the drive pulse from the output of the comparator (28) into the switches C and D is CM
When shifted to the right by increasing the P level, the overlap between switches A, C and B, D increases, thereby increasing the energy delivered to the transformer. In practice, this corresponds to a high current operation of the lamp. Conversely, by shifting the drive pulses of switches C and D to the left (by reducing the CMP signal), the energy delivered is reduced.

For this purpose, an error amplifier (32)
Is the feedback signal (FB) and the reference voltage (REF)
Compare with FB is the measurement result of the current value by the detection resistor (R _s ). In this case, the measured current value is the load (2
0). REF is a signal indicating a desired load state, for example, a desired current value flowing through the load. During normal operation, REF = FB. However, when the load condition is intentionally shifted,
For example, when the load state is intentionally shifted by the dimming switch attached to the LCD panel display,
The value of REF will increase or decrease accordingly. Therefore, a CMP is generated based on the compared values. The value of CMP is a reflection of the load condition and / or intentional bias and is determined as the difference between REF and FB (ie, REF−FB).

To protect the load and circuitry from opening at the load (eg, CCFL lamp opening conditions during normal operation), the FB signal is also preferably at the sense current comparator (42). , A reference value (this reference value is not shown and is different from the REF signal described above). The output from the detected current comparator (42) determines the state of the switch (38), as described below. The reference value in this case is
May be programmable and / or may be configurable by a user,
Preferably, it reflects the minimum or maximum current allowed for the system (eg, as estimated for an individual component, particularly a CCFL load). If the values of the feedback signal (FB) and the reference signal are within an allowable range (normal operation), the output of the current detection comparator is set to 1 (or HIGH). This allows the CMP to pass through the switch (38) and the circuit operates as described above, supplying power to the load. However, when the value of the feedback signal (FB) and the value of the reference signal are out of the allowable range (open circuit or short circuit), the output of the current detection comparator is set to 0 (or LOW). ,
The CMP signal is inhibited from passing through the switch (38) (of course, and vice versa, such as when the switch triggers a LOW state). In this case, the switch (38) supplies the minimum voltage Vmin (not shown) until the detected current comparator indicates that the current flowing through R _S is an allowable value, and the comparator (2
8). Therefore, the switch (3
8) has a suitable programmable selector to select Vmin if the detected current output is zero. Referring again to FIG. 3 (b), the effect of this operation is to reduce the CMP DC value to a nominal or minimum value (ie, CMP = Vmin). Thus, a high voltage condition does not occur in the transformer (TX1). Thus, the intersection point 36 shifts to the left, which reduces the amount of overlap between the complementary switches (recall that switch_C is turned on at intersection point (36)). Similarly, the detection current comparator (42) is also connected to the frequency generator (22), and when the detection current frequency is 0 (or some other preset value indicating an open circuit state). , Turn off the frequency generator (22). The CMP is supplied into the protection circuit (62). This is to turn off the frequency sweeper (22) when the CCFL is removed during operation (circuit open state).

To protect the circuit from overvoltage situations,
In this embodiment, preferably, the protection circuit (6
0) is provided. The operation of the protection circuit (60) will be described below (the overcurrent protection using the detection current comparator (42) is as described above). The protection circuit (60) includes a protection comparator (62) for comparing the CMP signal with a voltage signal (66) obtained from the load (20). Preferably, the voltage signal is
As shown in FIG. 5, the voltage dividers C2 and C3 (ie,
(A voltage divider connected in parallel to the load (20)). In the lamp open state, the frequency sweeper continues to sweep until the OVP signal (66) reaches the threshold. The OVP signal (66) is connected to the transformer (T
In order to detect the output voltage of X1), it is sampled from the outputs of the capacitor-type distributors C2 and C3. To simplify the analysis, these capacitors also represent ramp capacitors of equivalent load capacitance. The threshold value is a reference value, and the circuit determines that the secondary voltage of the transformer is less than the rated voltage of the transformer but the minimum critical voltage (eg,
Minimum critical voltage as required by LCD panel)
It is configured to be larger. OV
When P exceeds the threshold, the frequency sweeper stops sweeping the frequency. On the other hand, the detection current comparator (42)
Does not detect a signal across the detection resistor (R _S ). Therefore, the signal (24), which is the output of the switch block (38), is set to a minimum value and the switches A,
The amount of overlap between C, B, and D is minimized. Preferably, from the point where the OVP exceeds the threshold, a timer (64) is started, thereby initiating a pause sequence. The duration of the pause is preferably
It is determined according to the demand of the load (for example, CCFLs with LCD panel). However, the pause duration can also be set to some programmable value. After the primary stop, the drive pulse is prohibited,
Thus, the output from the converter circuit operates safely. That is, circuit (60) provides sufficient voltage for ignition of the lamp, but will shut down after a predetermined period of time when the lamp is not connected to the converter. Therefore, it is possible to prevent an inadvertent output of a high voltage. Such a pause duration is necessary for the unignited lamp to behave similarly to the lamp open condition.

FIGS. 4 and 5 (a) to 5 (f) show another preferred embodiment of the DC / AC converter circuit according to the present invention. In this embodiment, the circuit operates in a manner similar to that described with respect to FIGS. 2 and 3 (a) -3 (f). However, this embodiment further includes a phase locked loop circuit (PLL) (70) for controlling the frequency sweeper (22) and a flip-flop circuit (72) for timing the signal input into the C_drive. ). As can be understood from the timing chart, 50 of switches C and D
When the% drive pulse is shifted to the right by increasing the CMP level, the overlap between switches A, C and B, D increases, thereby increasing the energy delivered to the transformer. I do. In practice, this corresponds to a high current operation of the lamp (required, for example, by manually increasing the REF voltage as described above). Conversely, by shifting the drive pulses of switches C and D to the left (by reducing the CMP signal), the energy delivered is reduced. The phase locked loop circuit (70) is shown in FIG.
, A phase relationship is maintained between the feedback current (due to R _S ) and the tank current (due to TX1 / C1) during normal operation. PLL circuit (70)
Is preferably the tank circuit (primary side of C1 and TX1) signal (98) and the signal from R _S (the FB signal described above)
Are provided as input signals. After the CCFL is ignited and the current in the CCFL is detected by _RS , P
The LL circuit (70) is activated to lock the phase relationship between the lamp current and the current in the primary resonance tank (C1 and the transformer primary). That is, the PLL has all the effects that affect capacitance and inductance, such as temperature effects and mechanical components such as wires between the converter and the LCD panel, and the distance between the lamp and the metal chassis of the LCD panel. With respect to stray factors, the frequency of the frequency sweeper (22) can be adjusted. Preferably, the system comprises a resonant tank circuit and R
The phase difference between the current through _S (the load current) is 180
° to maintain. Thus, regardless of the specific load conditions and the operating frequency of the resonant tank circuit, the system finds the optimal operating point.

The operation of the feedback loop in the circuit configuration of FIG. 4 is the same as that described above with reference to FIG. However, as shown in FIG. 5B, in this embodiment, the timing of starting the signal output to the C_ drive is controlled by the flip-flop (72). For example, during normal operation, the output from the error amplifier (32) is controlled through the switch block (38) (described above) and is consequently provided as a signal (24). The amount of overlap between switches A and C and between B and D is controlled through comparator (28) and flip-flop (72). Flip-flop (72) drives switches C and D (recall that D_drive generates a signal that is complementary to C_drive). This results in steady state operation for CCFL (panel) loads. If the CCFL (panel) is removed during normal operation, the CMP raises the rail (reference) of the output of the error amplifier and immediately activates the protection circuit. This function is prohibited during the ignition period.

As shown in FIGS. 5 (a) -5 (f), in this embodiment, the triggering of switches C and D through the C_drive and D_drive alternates as a result of flip-flop circuit (72). It is typical. As shown in FIG. 5B, the flip-flops sequentially trigger. For this reason, the C_ drive is started (and the D_ drive is started sequentially).
For other operation modes, FIGS.
The operation is the same as described above with reference to (f).

FIGS. 6 to 11 show the execution results of the output circuit of FIG. 2 or 4. FIG. For example, FIG.
75.7K frequency sweeper for 21V input
It shows that the output becomes 16.7 KVp-p when Hz (overlap of 0.5 μs) is set. This voltage is insufficient to turn on the CCFL if 3300 Vp-p is required to ignite the CCFL. When the frequency is reduced to as low as 68 KHz, the minimum overlap is about 3.
Generate 9KVp-p. This is sufficient for CCFL ignition. This is shown in FIG.
At this frequency, the overlap increases to 1.5 μs, resulting in an output of about 1.9 KVp-p, driving a lamp with an impedance of 130 KΩ.
This is shown in FIG. As another example, FIG.
Shows the operation when the input voltage is 7V. At 71.4 KHz, the output is 750 Vp-p before ignition of the lamp. As the frequency decreases, the output voltage increases until the lamp ignites. Figure 1
0 means that the output is 3500 Vp- at 65.8 kHz.
p. Control of the CCFL circuit is obtained by controlling the overlap so that it can support an impedance of 130 KΩ after ignition. For lamps of 660 Vrms, CCF
The voltage across L is 1.9 KVp-p. This is shown in FIG. Although not shown, the execution result of the circuit of FIG. 4 has the same behavior.

The difference between the first embodiment and the second embodiment (ie, the flip-flop and the PLL in FIG. 4)
Has no effect on the entire operation parameter as shown in FIGS. 6 to 11. However, the addition of the PLL is to eliminate the undesired impedance generated in the circuit.
Can be added to the circuit shown in FIG. Also, by adding a flip-flop, as described above,
The constant current circuit can be omitted.

Thus, it should be apparent that there has been provided a highly efficient adaptive DC / AC converter circuit that meets the objects and goals set forth above. It will be apparent to those skilled in the art that changes can be made. For example, while the present invention describes the use of MOSFETs for switching, those skilled in the art will appreciate using BJT transistors or MOSFETs.
It will be appreciated that the entire circuit can be reconfigured to use any type of transistor in combination, such as s and BJTs. Other changes are possible. For example, the drive circuits associated with the B_drive and D_drive can comprise conventional collector-type circuits. Because the associated transistor is grounded and therefore not floating.
The PLL circuit described herein is preferably a general PLL circuit (70) known to those of ordinary skill in the art, suitably adapted to receive an input signal and generate a control signal as described above. Can be changed. Pulse generator (2
2) is preferably a pulse width modulation circuit (PWM) or a frequency width modulation circuit (F
WM) or both. Similarly, the protection circuit (62) and the timer can be comprised of known circuits, and can be suitably modified to operate as described above. Other circuit modifications will be apparent to those skilled in the art. All such modifications fall within the spirit and scope of the invention as defined by the appended claims.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a DC / AC converter circuit according to the related art.

FIG. 2 is a diagram showing a preferred embodiment of a DC / AC converter circuit according to the present invention.

FIGS. 3A to 3F are diagrams illustrating examples of timing in the circuit of FIG. 2;

FIG. 4 is a diagram showing another preferred embodiment of the DC / AC converter circuit according to the present invention.

5 (a) to 5 (f) are diagrams showing examples of timing in the circuit of FIG.

FIG. 6 is a diagram showing an execution result of the circuits shown in FIGS. 2 and 4;

FIG. 7 is a diagram showing an execution result of the circuits shown in FIGS. 2 and 4;

FIG. 8 is a diagram showing an execution result of the circuits shown in FIGS. 2 and 4;

FIG. 9 is a diagram showing an execution result of the circuits shown in FIGS. 2 and 4;

FIG. 10 is a diagram showing an execution result of the circuits shown in FIGS. 2 and 4;

FIG. 11 is a diagram showing an execution result of the circuits shown in FIGS. 2 and 4;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 12 Power supply 20 Load 22 Frequency sweeper 26 Gradient signal 28 Comparator 38 Switch block 40 Control loop 42 Detection current comparator 50 Drive circuit 60 Protection circuit 62 Protection comparator 64 Timer 70 Phase lock loop circuit (PLL circuit) 72 Flip-flop Circuit 80 Switch 90 Pulse signal 92 Complementary pulse signal TX1 Transformer

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Yun-Lin Lin United States, 94303 California, Palo Alto, Indian Drive, 2518 F-term (reference) 3K072 AA19 BC03 BC07 DD04 DE02 DE04 DE06 EA02 EA06 EB01 EB05 EB07 GA03 GB18 GC04 HA06 5H007 AA06 BB03 CA02 CB04 CB05 CB09 CC32 DB01 DC02 EA03 FA01 FA03

Claims (42)

[Claims] 1. A DC / AC converter circuit for transmitting power while controlling a load, comprising: an input voltage source; and a first set of mutually connected selectively connected to the voltage source. A plurality of overlapping switches and a second set of switches overlapping each other, wherein the first set of switches forms a first conductive path and the second set of plurality of switches. A first set of overlapping switches and a second set of overlapping switches, wherein the switches form a second conductive path; and a pulse for generating a pulse signal. A generator; a drive circuit for receiving the pulse signal and controlling a conductive state of the first and second sets of switches; a primary side and a secondary side And the voltage source is selectively connected to the primary side by alternately passing through the first conductive path and the second conductive path. A load connected to the secondary side of the transformer; and a feedback disposed between the load and the drive circuit for providing a feedback signal representing power supplied to the load. Wherein the drive circuit alternately switches the conductive state of the plurality of switches of the first set and the second set, and switches the plurality of switches in the first set. Controlling the overlap time between the plurality of switches in the second set and controlling the overlap time between the plurality of switches in the second set, such that the feedback signal and the pulse signal have at least a portion. Circuit which is characterized in that it is adapted to connect the primary side of the voltage source based on. 2. The circuit according to claim 1, wherein said input voltage source is a DC voltage source. 3. The circuit according to claim 1, wherein the drive circuit generates a first complementary pulse signal complementary to the pulse signal; and a gradient signal, wherein the pulse signal is the first set. The first pulse is supplied to a first switch of the plurality of switches forming the second switch, and is supplied to control the conduction state of the first switch. The second pulse is obtained by comparing the tilt signal with at least the feedback signal. A signal is generated, and the second pulse signal is supplied to a second switch of the plurality of switches in the first set, and is used for controlling a conduction state of the second switch. An overlap state between the conduction state of the first switch and the conduction state of the second switch of the plurality of switches in the first set is controlled, and the driving circuit comprises: Generating a second complementary pulse signal based on the second pulse signal, wherein the first and second complementary pulse signals are a first switch and a second switch of the second set of switches.
Controlling the conduction state of each of the switches, whereby the overlap state between the conduction state of the first switch and the conduction state of the second switch of the second set of switches is controlled. A circuit characterized by the following. 4. The circuit of claim 3, wherein said first set and said second set of switches are:
A circuit comprising a MOSFET transistor. 5. The circuit according to claim 4, wherein each of said transistors includes a unique switch connected in parallel to each of said transistors in a state of being reversely biased with respect to said voltage source. Each discharges energy stored in the primary side of the transformer by forming a conductive path between the voltage source and the primary side when a respective transistor is non-conductive. A circuit characterized in that: 6. The circuit according to claim 5, wherein said unique switch is a diode. 7. The circuit according to claim 3, wherein a phase difference between the pulse signal and the first complementary pulse signal is about 180 °, and wherein the second pulse signal and the second complementary pulse signal are different from each other. Wherein the phase difference between the first and second conductive paths is about 180 °, so that a short circuit between the first conductive path and the second conductive path does not occur. 8. The circuit according to claim 7, wherein the conductive states of the first set of switches and the second switch are connected to each other.
A circuit, wherein the conductive state of a set of switches determines the power supplied to the load. 9. The circuit according to claim 3, wherein the feedback loop circuit compares a reference signal with the feedback signal to generate a first output signal, and the first output signal. And a second comparator for comparing the ramp signal and generating a second output signal based on an intersection between the first output signal and the ramp signal;
A circuit comprising: 10. The circuit according to claim 9, wherein said feed signal is a measure of the current flowing through said load. 11. The circuit according to claim 9, further comprising a current detection circuit for receiving the feedback signal and generating a trigger signal, wherein the feedback loop circuit further includes a first comparator and a current detection circuit. A switch circuit between the second comparator and the second comparator, the switch circuit receiving the trigger signal, and determining whether the signal is the first output signal or a predetermined minimum signal based on a value of the trigger signal. A circuit for generating any one of the following. 12. The circuit according to claim 9, wherein the reference signal is generated by a reference signal generator and represents a desired power value to be supplied to the load. A circuit characterized by the above. 13. The circuit of claim 9, further comprising: an overcurrent protection circuit receiving the feedback signal and controlling the pulse generator based on a value of the feedback signal; and a voltage signal applied to the load. And an overvoltage protection circuit that receives the first output signal and the first output signal, compares the voltage signal with the first output signal, and controls the pulse generator based on a value of the voltage signal applied to the load; A circuit comprising: 14. The circuit of claim 1, wherein said pulse generator is programmed to start said converter circuit with a duty cycle of 50%, is started at a predetermined frequency, and further has a predetermined speed and A circuit comprising a programmable pulse frequency generation circuit adapted to sweep said frequency downward in a predetermined number of stages. 15. The circuit according to claim 1, wherein the load comprises one or more cold cathode fluorescent lamps (CC).
FLs). 16. The circuit of claim 1, wherein said primary side comprises a resonant tank circuit having an inductor and a capacitor. 17. The circuit according to claim 1, wherein said secondary side comprises a voltage divider circuit connected in parallel to an inductor connected in parallel to said load. 18. A converter circuit for transmitting power to a CCFL load, comprising: a voltage source; a transformer having a primary side and a secondary side; and the voltage source and the primary side. A second pair of switches forming a first conductive path between the voltage source and the primary side; and a second pair of switches forming a second conductive path between the voltage source and the primary side. CCF connected to the side
An L load circuit; a pulse generator for generating a pulse signal; a feedback circuit connected to the load for generating a feedback signal; and receiving the pulse signal and the feedback signal; , Based on the control pulse signal and the feedback signal so that power can be supplied to the load,
A drive circuit for connecting a pair of switches or the second pair of switches to the voltage source and the primary side. 19. The circuit according to claim 18, wherein the pulse signal has a predetermined frequency, and the driving circuit comprises a first driving circuit, a second driving circuit, a third driving circuit, and a fourth driving circuit. Wherein the first pair of switches has a first transistor and a second transistor, and the second pair of switches has a third transistor and a fourth transistor; A second drive circuit, the third drive circuit, and the fourth drive circuit are connected to respective control lines of the first transistor, the second transistor, the third transistor, and the fourth transistor; The pulse signal is supplied to the first drive circuit,
Accordingly, the first transistor is switched in response to the pulse signal, the third drive circuit generates a first complementary pulse signal and a gradient signal based on the pulse signal,
Supplying a complementary pulse signal to the third transistor, whereby the third transistor is switched according to the first complementary pulse signal, and the slope signal and the feedback signal are compared, A second pulse signal is generated, and the second pulse signal is supplied to the second driving circuit, whereby the second transistor is switched according to the second pulse signal, and the fourth driving signal is generated. A circuit generates a second complementary pulse signal based on the second pulse signal, and further supplies the second complementary pulse signal to the fourth transistor, so that the fourth transistor (2) switching in response to a complementary pulse signal; and conducting simultaneously between the first transistor and the second transistor; Circuit, wherein each of the simultaneous conduction between the transistor and the fourth transistor controls power supplied to the load. 20. The circuit of claim 18, wherein a phase difference between the pulse signal and the first complementary pulse signal is about 180 °, and wherein the second pulse signal and the second complementary pulse signal Wherein the pulse signal and the second pulse signal control power supply through the first conductive path, and the first complementary pulse signal The circuit according to claim 2, wherein the second complementary pulse signal controls power supply through the second conductive path. 21. The circuit according to claim 19, wherein the feedback circuit compares the feedback signal with a reference signal to generate a first output signal; A second comparator for comparing the ramp signal and generating a second output signal based on an intersection between the first output signal and the ramp signal. 22. The circuit of claim 21, wherein the reference signal is generated by a reference signal generator and represents a desired power value to be supplied to the load. A circuit characterized by the above. 23. The circuit according to claim 21, further comprising an overvoltage protection circuit connected to the load and the pulse generator, wherein the overvoltage protection circuit receives a voltage applied to the load as an input. Receiving, based on the value of the voltage across the load,
A circuit adapted to control the pulse generator. 24. The circuit of claim 23, wherein the overvoltage protection circuit compares a voltage signal across the load with the first output signal to control power supply by the pulse generator. A circuit for supplying a control signal to a pulse generator. 25. The circuit of claim 24, wherein the overvoltage protection circuit comprises a timer circuit, and wherein the control signal is controlled for a predetermined time generated by the timer circuit. A circuit characterized by the following. 26. The circuit of claim 21, further connected to the pulse generator, receiving the feedback signal as an input, and controlling the pulse generator based on a value of the feedback signal. A circuit comprising an overcurrent protection circuit. 27. The circuit according to claim 19, wherein the first transistor and the third transistor are connected in series with each other, and are connected in parallel to the voltage source and the primary side. A circuit, wherein a transistor and the fourth transistor are connected in series with each other, and are connected in parallel to the voltage source and the primary side. 28. The circuit of claim 19, further comprising a unique switch connected in parallel to each of said transistors, wherein said unique switch is connected before each transistor is switched to a conductive state. Is a circuit adapted to permit energy flow from said primary side through said first conductive path or said second conductive path. 29. The circuit of claim 18, wherein said primary forms a resonance tank circuit having a single resonance frequency. 30. The circuit according to claim 19, wherein said first drive circuit and said third drive circuit are totem pole circuits, and wherein said second drive circuit and said fourth drive circuit are connected to a bootstrap circuit and a high level. A circuit selected from the group consisting of a side drive circuit and a level shift circuit. 31. The circuit according to claim 19, wherein said second drive circuit and said fourth drive circuit further comprise:
A circuit comprising an inverter for generating each of the first complementary pulse signal and the second complementary pulse signal. 32. The circuit according to claim 31, wherein the second drive circuit further includes a sawtooth waveform generating circuit for generating the tilt signal, wherein the generated sawtooth waveform is A circuit having a frequency suitable for a pulse signal. 33. The circuit according to claim 21, further comprising: being connected to the second pulse signal, and providing the second drive signal to the second drive circuit only when the third transistor is switched to a conductive state. A circuit including a flip-flop circuit for supplying a two-pulse signal. 34. The circuit of claim 18, further comprising a phase locked loop (PLL) circuit having a first input signal from the primary side and a second input signal using the feedback signal. The PLL circuit transmits a control signal to the pulse generator to control a pulse width of the pulse signal based on a phase difference between the first input and the second input. Circuit. 35. A method for performing control using a zero voltage switching circuit in transmitting power to a load, comprising: providing a DC voltage source; connecting the voltage source to a primary side of a transformer. On the other hand, a first transistor and a second transistor for forming a first conductive path are connected, and a second transistor for forming a second conductive path with respect to the voltage source and the primary side of the transformer. Connecting a third transistor and a fourth transistor; generating a pulse signal having a predetermined pulse width; connecting a load to a secondary side of the transformer;
Generating a feedback signal from the load; controlling the feedback signal and the pulse signal to determine a conduction state of the first transistor, the second transistor, the third transistor, and the fourth transistor; A method characterized by that: 36. The method according to claim 35, further comprising the step of preventing the first transistor and the third transistor from conducting simultaneously, and the second transistor and the fourth transistor not conducting simultaneously. A method of timing conduction between transistors. 37. The method of claim 35, further comprising: generating a first complementary signal and a second complementary signal; generating a ramp signal; and comparing the ramp signal with the feedback signal. Generating a pulse signal;
By supplying the pulse signal to the first transistor, the conduction state of the first transistor is controlled, and by supplying the second pulse signal to the second transistor, the second transistor is supplied. The first complementary pulse signal to the third
By supplying to the transistor, the conduction state of the third transistor is controlled, and by supplying the second complementary pulse signal to the fourth transistor, the conduction state of the fourth transistor is controlled. Supplying power to the primary side by controlling simultaneous conduction of the first transistor and the second transistor and controlling simultaneous conduction of the third transistor and the fourth transistor; how to. 38. The method according to claim 37, wherein a first output signal is generated based on a result of the comparison by comparing the feedback signal and a reference signal; Generating said second pulse signal by comparing. 39. The method of claim 35, further comprising controlling the pulse generator based on a voltage signal across the load. 40. The method of claim 35, further comprising controlling the pulse generator based on the feedback signal. 41. The method according to claim 35, further comprising: supplying a first signal representing a voltage applied to the primary side and a second signal representing a current flowing through the load to the phase lock circuit. Locking a phase difference between the first signal and the second signal and generating a control signal based on the phase difference; supplying the control signal to the pulse generator, Adjusting a pulse width of the pulse signal based on a phase difference between the first signal and the second signal. 42. The method of claim 37, wherein generating the second pulse signal by comparing the first output signal with the ramp signal further comprises:
Generating the second pulse signal based on an intersection between the ramp signal and the first output signal.