JP2002232890A - Block distortion reduction circuit, reproducing device, receiver, block distortion reduction method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a block distortion reduction circuit that can reduce a block noise at a low cost with high accuracy in the case of reproducing image data that are block-coded. SOLUTION: A 1st detection circuit 81, a 2nd detection circuit 82, a 3rd detection circuit 83 and a 4th detection circuit 84 respectively detect that a target point P exists on a block boundary, block noise reduction processing is applied to the target point P and a degree of the reduction processing is decided depending on a boundary difference value and threshold values H, M at the target point P.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention reduces block distortion (block noise) from digital image data to be reproduced when, for example, digital image data compressed and coded by using a block coding method is reproduced. The present invention relates to a block distortion reducing circuit, a block distortion reducing method, and a reproducing apparatus and a receiving apparatus to which these are applied.

[0002]

2. Description of the Related Art In order to efficiently record or transmit still image data and moving image data having a huge data amount on a recording medium, the still image data and the moving image data have , 8 pixels × 8 pixels, and the like, a compression coding method using block coding for compressing data using the block as a processing unit is widely used.

For example, JPEG (Joint Ph) which is widely used as a compression coding method for still image data
autographic Experts Group)
And MPEG (Moving Picture) which is widely used as a compression coding method for moving image data.
The Experts Group system is a compression encoding system using a block encoding system.

[0004] In a compression coding method using a block coding method, an image is decomposed into a spatial frequency sequence, and an important part (low frequency component) is left as an impression of the image. This is a so-called lossy compression method in which (high-frequency components) are discarded. Therefore, as the compression ratio increases, continuity at a block boundary (boundary portion between adjacent blocks) cannot be ensured, and a shift in a reproduced data value at a block boundary portion is perceived as noise, and the block itself is seen. A so-called block noise may appear.

As a method of reducing such block noise, for example, Japanese Patent Laid-Open No. Hei 10-191335 discloses a method of detecting a block boundary portion and performing filtering on image data of the block boundary portion. A method of performing correction has been proposed.

Further, Japanese Patent Application Laid-Open No. H11-2155001 proposes a method in which motion between adjacent blocks is also determined, and block noise is reduced by performing appropriate block noise correction on image data. Have been.

[0007]

In the above-described block noise reduction method, for example, block boundaries are sequentially detected in the horizontal direction, and it is determined that block noise is generated at the block boundaries. In this case, since the correction processing is performed on the image data in the vicinity of the block boundary, the block noise can be quickly reduced with a relatively simple processing without using a memory for storing the image data.

However, depending on the former block noise reduction method, the pixel value between adjacent images may be large due to the occurrence of block noise, or a large difference in pixel values between adjacent images. It is considered that it may not be possible to reliably determine whether the difference is merely a contour portion of the image. Therefore, when the outline of the image is erroneously determined to be the block boundary, block noise correction processing is performed on the image data of the outline, and the outline of the image may be blurred. There is.

In the latter block noise reduction method, since the motion between adjacent blocks is also determined and the block noise is reduced, the block noise can be reduced reliably and satisfactorily. However, since the motion between adjacent blocks is determined, a memory for storing the image data is required, and the processing becomes complicated, so that the cost of the device for performing the block noise reduction processing increases. This means that the cost of an image data reproducing device or a receiving device equipped with a device for performing a block noise reduction process increases.

[0010] DVD (Digital Versati)
With the spread of “le Disc” and the start of digital television broadcasting, the provision of digital image data to be subjected to compression encoding using block encoding is expected to increase more and more in the future. For this reason, in using digital image data, it is possible to reduce block noise at lower cost,
In addition, it is required to perform the process with high accuracy.

In view of the above, the present invention provides a block distortion reduction circuit, a reproducing apparatus, and a method capable of reducing block noise at low cost and high accuracy when reproducing block-coded image data. An object of the present invention is to provide a receiving device and a block distortion reduction method.

[0012]

According to a first aspect of the present invention, there is provided a block distortion reduction circuit for decoding a block-coded digital image data in a block-decoding manner and outputting the block-coded digital image data. Circuit for reducing block distortion of input image data supplied in sequence and sequentially supplied, the input image data including a difference value of a pixel value between pixels adjacent to a predetermined target position and the target position A step detecting means for detecting whether or not the target position is a block boundary based on an average value of difference values between adjacent pixel values within a predetermined range; and At least one of after and after the block, a front and rear boundary detecting means for detecting whether or not a block boundary exists; and a pixel adjacent to the target position with respect to the input image data. A pixel difference detection unit that detects whether the target position is a block boundary based on a difference value between the pixel values of the pixel values, a step difference detection unit, the front and rear boundary detection unit, and the pixel difference detection unit, When the target position is detected to be a block boundary, a reduction processing unit that outputs input image data that has been subjected to block distortion reduction processing at the target position is provided.

According to the block distortion reduction circuit of the first aspect, the step detecting means, the front and rear boundary detecting means, and the pixel difference detecting means determine whether or not the predetermined target position is truly a block boundary. Is detected. When each of the detection means determines that the predetermined target position is a block boundary, the reduction processing means reduces the block noise with respect to the image data near the block boundary which is the target position. Processing is performed and this is output.

As described above, the step detecting means, the front and rear boundary detecting means, and the pixel difference detecting means reliably detect the block boundary where the block noise is generated, and detect the block noise with high accuracy. So that it can be reduced. In addition, since block noise can be reduced by a relatively simple process without using a memory for storing image data in the block boundary determination process, a block noise reduction circuit can be configured at low cost. can do.

Further, the block distortion reduction circuit according to the second aspect of the present invention, when the block-decoded digital image data is decoded and output, the block-decoded input image data supplied sequentially. A circuit for reducing the block distortion of the input image data, the difference value of the pixel value between pixels adjacent to a predetermined position of interest, the difference value of the adjacent pixel value within a predetermined range including the position of interest A step detecting means for detecting whether or not the target position is a block boundary based on the average value, and, for the input image data, an average value of pixel values of a plurality of pixels at a preceding stage of the target position and a plurality of A plurality of pixel difference detecting means for detecting whether or not the target position is a block boundary based on an average value of pixel values, and an image adjacent to the target position for the input image data; A pixel difference detection unit that detects whether the target position is on a block boundary based on a difference value between pixel values between the pixel values, a step difference detection unit, the multiple pixel difference detection unit, and the pixel difference detection unit. And a reduction processing unit configured to output, when it is detected that the target position is a block boundary, input image data obtained by performing a block distortion reduction process on the target position. .

According to the block distortion reducing circuit of the second aspect, the step detecting means, the plural pixel difference detecting means, and the pixel difference detecting means determine whether or not the predetermined target position is truly a block boundary. Is detected. When each of the detection means determines that the predetermined target position is a block boundary, the reduction processing means reduces the block noise with respect to the image data near the block boundary which is the target position. Processing is performed and this is output.

As described above, the step difference detecting means, the plural pixel difference detecting means, and the pixel difference detecting means surely detect the block boundary where the block noise occurs, and detect the block noise with high accuracy. So that it can be reduced. In addition, since block noise can be reduced by a relatively simple process without using a memory for storing image data in the block boundary determination process, a block noise reduction circuit can be configured at low cost. can do.

The block distortion reduction circuit according to the third aspect of the present invention, when the block-encoded digital image data is decoded into blocks and output, is block-decoded and sequentially supplied input image data. A circuit for reducing the block distortion of the input image data, the difference value of the pixel value between pixels adjacent to a predetermined position of interest, the difference value of the adjacent pixel value within a predetermined range including the position of interest A step detecting means for detecting whether or not the target position is a block boundary based on the average value; and a block boundary at least one of one block before and one block after the target position with respect to the input image data. Front and rear boundary detecting means for detecting whether or not there is an image, and for the input image data, an average value of pixel values of a plurality of pixels at a preceding stage of the target position and a plurality of pixels at a subsequent stage Based on the average value of the pixel value,
A plurality of pixel difference detection means for detecting whether or not the target position is a block boundary; and a method for detecting whether the target position is a block boundary based on a difference value of pixel values between pixels adjacent to the target position with respect to the input image data. The target position may be a block boundary by the pixel difference detecting means for detecting whether or not, the step difference detecting means, the front and rear boundary detecting means, the plural pixel difference detecting means, and the pixel difference detecting means. A detection unit configured to output, when the detection is performed, input image data obtained by performing a block distortion reduction process on the position of interest.

According to the block distortion reducing circuit of the third aspect, the predetermined target position is truly determined by the step detecting means, the front and rear boundary detecting means, the plural pixel difference detecting means, and the pixel difference detecting means. It is detected whether or not it is a block boundary.
When each of the detection means determines that the predetermined target position is a block boundary, the reduction processing means reduces the block noise with respect to the image data near the block boundary which is the target position. Processing is performed and this is output.

As described above, the step difference detecting means, the front and rear boundary detecting means, the plural pixel difference detecting means, and the pixel difference detecting means can more reliably detect the block boundary where the block noise is generated, and achieve high precision. Block noise can be reduced. In addition, since block noise can be reduced by a relatively simple process without using a memory for storing image data in the block boundary determination process, a block noise reduction circuit can be configured at low cost. can do.

A block distortion reduction circuit according to a fourth aspect of the present invention is the block reduction circuit according to the second or third aspect, wherein the plurality of pixel difference detection means is provided in a stage preceding the target position. Detecting, based on a difference between an average value of the pixel values of a plurality of pixels and an average value of the pixel values of a plurality of subsequent pixels, and a predetermined threshold, whether or not the target position is a block boundary, Can be changed as necessary.

According to the block distortion reduction circuit of the present invention, the difference value between the average value of the pixel values of a plurality of pixels at the preceding stage of the target position and the average value of the pixel values of the plurality of pixels at the subsequent stage of the target position is calculated. The predetermined threshold value to be compared can be changed according to, for example, an instruction input from the user. Thereby, according to the state of the input image data, etc.,
The degree of discrimination as to whether or not the boundary is a block boundary can be changed.

A block distortion reduction circuit according to a fifth aspect of the present invention is the block reduction circuit according to the first, second or third aspect, wherein the reduction processing means is located at the position of interest. The degree of the reduction processing is changed according to a difference value of a pixel value between adjacent pixels.

According to the block distortion reduction circuit of the fifth aspect, the filter coefficient of the noise filter for reducing the block noise is changed according to the difference between the pixel values of the pixels adjacent to the target position. For example, the degree of block noise reduction processing can be changed by using different noise filters or the like.

As a result, it is possible to perform a block noise reduction process in accordance with the actually generated block noise, thereby causing inconveniences such as unnecessary noise reduction and insufficient noise reduction. I try not to be.

According to a sixth aspect of the present invention, there is provided the block distortion reduction circuit according to the fifth aspect, wherein the reduction processing means includes a pixel value between pixels adjacent to the target position. And the degree of the reduction processing is determined based on the difference value of (i) and a predetermined threshold value. The degree of the reduction processing according to the difference value can be changed by changing the predetermined threshold value. And

According to the block distortion reduction circuit of the sixth aspect, whether or not to perform the block noise reduction processing is determined. If the block noise reduction processing is performed, the degree of the block noise reduction processing is determined as follows. Whether to perform “strong” or “weak” is determined based on a comparison result between a pixel value difference value between pixels adjacent to the target position and a predetermined threshold value. Then, the threshold value can be changed, for example, by the user. This makes it possible to perform an appropriate degree of block noise reduction processing according to the state of the input image data.

[0028]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of a block distortion reducing circuit, a block distortion reducing method, a reproducing apparatus, and a receiving apparatus according to the present invention. In the embodiments described below, a case where the block distortion reduction circuit, the block distortion reduction method, and the reproducing apparatus according to the present invention are applied to a DVD reproducing apparatus, and a block distortion reducing circuit, a block distortion reducing method, and a receiving apparatus according to the present invention. An example in which the apparatus is applied to digital television broadcast reception measures will be described.

[First Embodiment] FIG. 1 is a diagram for explaining a DVD reproducing apparatus to which a block distortion reducing circuit, a block distortion reducing method and a reproducing apparatus according to the present invention are applied. In FIG. 1, a disc 20 is a DVD loaded in a DVD reproducing apparatus (hereinafter, simply referred to as a reproducing apparatus) according to the first embodiment. For example, image data such as a movie is compressed by an MPEG method. It is encoded and recorded.

In the compression coding of the MPEG system, the compression coding of an image is performed by utilizing the correlation in the time direction and the space direction of the image. The use of the correlation in the space direction is performed by a DCT code which is block coding. (Discrete Cosi)
n Transform). That is, the image data recorded on the disk 20 is data that has been data-compressed by a compression coding method using block coding.

As shown in FIG. 1, the reproducing apparatus according to the first embodiment comprises an optical head 1, a disk rotation drive unit 2,
It is provided with a drive unit 3 of the optical head 1. Optical head 1
Includes an optical system such as a laser light source, a beam splitter, an objective lens, and a photodetector (light receiving element), a two-axis actuator, and the like.

The rotation drive unit 2 includes a spindle motor and the like, and drives the disk loaded in the reproducing apparatus of the first embodiment to rotate at a constant linear velocity (CLV), for example. Further, the driving unit 3 of the optical head 1
Is composed of a slide mechanism such as a sled motor for moving the optical head 1 in the radial direction of the disc loaded in the reproducing apparatus.

At the time of reproducing image data and audio data from the disk 20, the optical head 1 irradiates the disk 20 with a laser beam from a laser light source, and receives the reflected light of the laser beam from the disk 20 with a photodetector. . The photodetector of the optical head 1 converts the received reflected light into an electric signal, and supplies the electric signal to the RF processor 5. Thus, the data recorded on the disk 20 is read.

The RF processor 5 receives the supply of the electric signal from the optical head 1 and reproduces an RF signal corresponding to data recorded on the disk 20, a focus error signal,
Form a tracking error signal. The focus error signal and tracking error signal formed here are supplied to the servo controller 4. The reproduced RF signal is supplied to the MPEG decoder / AV decoder 6.
Further, address information and the like read from the disk 20 are supplied from the RF processor 5 to the system controller 15.

The servo controller 4 controls the rotation drive unit 2 and the drive unit 3 of the optical head 1 based on a control signal from the system controller 15 and a focus error signal and a tracking error signal from the RF processor 5. Is supplied to the rotation drive unit 2 and the drive unit 3 of the optical head 1.

Thus, the disk 20 loaded in the reproducing apparatus according to the first embodiment is controlled by the rotary drive unit 2 to have a constant linear velocity, and the biaxial actuator of the optical head 1 A track on the disk 20 on which data is recorded is driven by a driving section 3 of the head 1 with a laser beam having a spot shape of an appropriate size.
It is made possible to scan accurately.

On the other hand, the MPEG decoder 6 performs inverse quantization and inverse DC on the reproduced RF signal from the RF processor 5.
Processing such as T-encoding is performed to decode the image data and the audio data which are compressed by the MPEG method, thereby restoring the original image data and the audio data before the compression encoding. Here, the decoded audio data is supplied to the audio reproduction processing unit 7, and the image data is supplied to the block distortion reduction unit 8.

The audio reproduction processing section 7 forms digital audio data for reproduction from the decoded digital audio data supplied thereto. The digital audio data for reproduction formed here is output through a digital I / F or D / A converted and output.

On the other hand, the block distortion reduction unit 8 performs a block noise reduction process for reducing block distortion (block noise), which will be described in detail later, on the decoded image data from the MPEG decoder 6. Digital image data to digital output encoder 9, NTSC / PA
It is supplied to the L encoder 12.

The digital output encoder 9 forms digital image data for output from the supplied digital image data after the block noise reduction processing, and outputs the digital image data through a digital I / F 10 and an output terminal 11 for digital image data. It is supplied to a subsequent stage, for example, a monitor receiver.

On the other hand, the NTSC / PAL encoder 12
Forms digital image data according to the NTSC system / PAL system from the digital image data after the block noise reduction processing supplied thereto, and converts the digital image data into a D / A converter 13.
To supply. The D / A converter 13 converts the N
The digital image data converted into the TSC / PAL format is converted into an analog signal, and this is supplied to a subsequent stage, for example, a monitor receiver through an analog image signal output terminal 14.

In FIG. 1, a system controller 15 controls each section of the reproducing apparatus of the first embodiment, and includes a CPU, a ROM, a RAM, and an EEPROM.
This is a microcomputer including an OM and the like. The operation unit 16 receives an input operation from a user, and is provided with various operation keys such as a play key, a stop key, and a pause key. The display unit 17
For example, LCD (Liquid Crystal Dis)
play), and by displaying various guidance messages and the like, the user can be notified of this.

When the system controller 15 receives a reproduction instruction input from the user through the operation section 16, the reproduction start control of the reproduction operation for reproducing the image data and the audio data recorded on the disk 20 is performed. The signal is supplied to the servo controller 4.

The servo controller 4 includes the rotation driving unit 2,
As described above, the drive unit 3 of the optical head 1 and a control signal for operating the optical head 1 are formed and supplied to the rotary drive unit 2, the drive unit 3 of the optical head 1, and the optical head 1, thereby forming a disk. The disk 20 is rotated at a constant linear velocity, a laser beam is irradiated on the disk 20, and a track on the disk 20 on which data is recorded is scanned to read data recorded on the disk 20. To play.

As described above, the reproducing apparatus according to the first embodiment can read out and reproduce the image data and the audio data recorded on the disk 20 by compression encoding according to the MPEG system. Things. And
With respect to image data, block noise generated at the time of block coding can be reduced (removed) easily and highly accurately by the block distortion reduction unit 8 and output.

FIG. 2 is a block diagram for explaining the block distortion reduction section 8 of the reproducing apparatus according to the first embodiment shown in FIG. 1, and shows a block distortion reduction circuit and a block distortion reduction circuit according to the present invention. The method has been applied. As shown in FIG. 2, the block distortion reduction unit 8 includes a first detection circuit (step difference detection means) 81 and a second detection circuit (multiple pixel difference detection means) 82 as four detection circuits for detecting block boundaries. , A third detection circuit (front and rear boundary detection means) 83,
And a fourth detection circuit (pixel difference detection means) 84.
The fourth detecting means also has a function as a means for detecting the correction intensity, as described later.

Also, as shown in FIG.
5, 86, latch circuit section 87, block clock signal B
A block boundary detection circuit 58 for generating LK, and delay circuits 59, 62, and 6 for matching the phases of the luminance signal and the chrominance signal supplied to the block distortion reduction unit 8 as described later.
4. Two block noise removal filters having different filter coefficients (hereinafter referred to as block noise filters) 6
0, 61 and a data selector 63 are provided.

In FIG. 2, latch circuits 85 and 86, each latch circuit constituting a latch circuit portion (a portion composed of nine stages of latch circuits) 812 of the first detection circuit 81, and a latch circuit of the second detection circuit 82 Each of the latch circuits included in the section (a section including a 10-stage latch circuit) 821 operates on a pixel clock (in units of one pixel).

Each of the latch circuits constituting the latch circuit portion (portion consisting of three stages of latch circuits) 832 of the third detection circuit 83 and the latch circuit portion (portion consisting of three stages of latch circuits) 87 are constituted. Each of the latch circuits is operated by a block clock (in units of 8 pixels).

In the block distortion reduction section 8 of the first embodiment, four detection circuits 81, 82, 83 and 84 are provided.
In each case, when a block boundary where block noise occurs is detected, block noise reduction processing is performed on the block boundary.
As described above, by performing the block noise reduction process only when a block boundary is detected in each of the plurality of block boundary detection circuits, the outline portion of the image is not erroneously determined to be a block boundary. Block noise reduction processing is performed appropriately.

The block distortion reduction section 8 of the first embodiment detects a horizontal block boundary using a luminance signal, and performs block noise reduction processing on the luminance signal. This is an example of a case in which block noise is reduced by using. Therefore, the luminance signal Yin to be processed is input to the latch circuit 55 of the block distortion reduction unit 8. The horizontal synchronizing signal H is supplied to the block boundary detection circuit 58 of the block distortion reduction unit 8.
D and the pixel clock signal Pclk are input. The delay circuit 64 of the block distortion reduction unit 8 includes the color signal C
in is input.

These luminance signal Yin, color signal Cin,
In this embodiment, the horizontal synchronization signal HD and the pixel clock signal Pclk are separated from the decoded image data by the MPEG decoder 7, for example.
It is extracted and supplied to the corresponding circuit of the block reduction unit 8.

Hereinafter, each detection circuit 81, 82, 83, 8 of the block distortion reduction section 8 of the first embodiment will be described.
4 will be described, and the overall operation of the block distortion reduction unit 8 will also be described.

FIG. 3 is a diagram for explaining a range of pixel data used for a block boundary detection process performed in each of the detection circuit units 81, 82, 83, and 84 of the block distortion reduction unit 8. . As described above, the playback device of the first embodiment processes image data that has been subjected to MPEG compression coding using block DCT coding.

In this case, the processing unit of DCT coding is 8
This is a block of pixels × 8 pixels (DCT block).
A block of pixels × 8 pixels is a processing unit of DCT coding.

If attention is paid to the horizontal direction, for example,
In FIG. 3, a region of a total of 10 pixels, that is, 5 pixels each on the left and right in the horizontal direction from the boundary 0 is a boundary detection processing range 32 for the block boundary detection processing. In this embodiment, a range of four pixels on the left and right (front and back) in the horizontal direction from the block boundary is a filtering range 33 for performing filtering in order to reduce block noise.

In the following, description will be made by taking an example in which each block boundary in the horizontal direction is detected and block noise is reduced. In the vertical direction, similarly, for example, in FIG. As shown in FIG. 3, in FIG. 3 sandwiching the block boundary in the vertical direction, a range of 10 pixels of 5 pixels vertically and vertically (front and rear) is
It becomes a boundary detection range, and it is possible to detect each block boundary in the vertical direction and perform a block noise reduction process.

In the boundary detection processing ranges 32 and 34, alphabets a, b, c, d, e, f, g, h,
Each of i and j indicates a pixel value (luminance data) at each pixel position represented by, for example, 8 bits.

FIG. 4 is a diagram showing the horizontal boundary detection processing range 32 shown in FIG. 3 and image data in the vicinity thereof. In the first embodiment, each detection circuit 81, 82, 8 of the block distortion reduction unit 8 is used.
Each of 3 and 84 uses the absolute value of the difference between the pixel values (luminance data) between the pixels in the boundary detection processing range 32 or the absolute value of the average value of the pixel values in the predetermined range to obtain the block boundary. Is to be detected.

As shown in FIG. 4, in the first embodiment, a target point (target position) M is provided at a predetermined position in the horizontal direction. In the example shown in FIG. 4, a point of interest P is defined between the pixel e and the pixel f sandwiching the block boundary 1.

Then, as shown in FIG. 4, the absolute value of the difference between the pixel e and the pixel f sandwiching the point of interest P is defined as a block boundary difference value (hereinafter, referred to as a boundary difference value) bound1. In the boundary detection processing range 32, the absolute value of the difference between adjacent pixels (excluding pixels e and f) is calculated as the adjacent difference value diff0, diff1, diff2, diff.
3, diff4, diff5, diff6, diff7
And

More specifically, the boundary difference value bound1 and the adjacent difference values diff0 to diff7 are obtained by the equation (1) shown in FIG. 5A. Further, each adjacent difference value diff0-diff7 is
It is obtained by the equations (1) to (8) shown in FIG. 5B.

Then, the first detection circuit 81 of the block distortion reduction section 8 detects whether or not a step occurs in an image between adjacent pixels sandwiching the point of interest P. The presence or absence of a step in the image between adjacent pixels sandwiching the point of interest P is determined by a so-called activity value (d) in which the boundary difference value bound1 is the average value of the adjacent pixel values, as shown in equation (1).
+ diff7) / 8, it can be determined that there is a step in the image between adjacent pixels sandwiching the point of interest P.

That is, when the expression (1) shown in FIG. 6 is satisfied, the difference between adjacent pixels sandwiching the target point P is larger than the difference between neighboring pixels around the target point P.
It can be determined that the image has a step.

Therefore, the block distortion reduction unit 8 shown in FIG.
, The pixel values (luminance data) A and B of the adjacent pixels latched by the latch circuits 85 and 86 are set to the first values.
It is supplied to the difference calculation circuit 811 of the detection circuit 81. In this case, the pixel value B supplied to the difference calculation circuit 811 is the pixel value of the previously input pixel, and the pixel value A is the pixel value of one pixel after the pixel value B.

The difference calculation circuit 811 obtains the absolute value of the difference between adjacent pixels, thereby obtaining the adjacent difference value di.
ff0 to diff7 and a block boundary difference value bo
und1 is calculated. The difference value calculated by the difference calculation circuit 811 is supplied to the latch circuit unit 812.

The adjacent difference values diff0, diff1, diff2, and diff in the boundary determination processing range 32 shown in FIG.
f3, boundary difference value bound1, adjacent difference value diff
4, diff5, diff6, diff7 are latched in this order.

The averaging circuit 8 of the first detection circuit 81
In FIG. 13, adjacent difference values diff4, diff5, and
diff6 and diff7 are supplied and the first detection circuit 81
In FIG. 4, the adjacent difference values diff0 and diff for the pixel on the right side of the point of interest P in FIG.
1, diff2 and diff3 are supplied.

The averaging circuits 813 and 814 calculate the average value of the four adjacent difference values supplied thereto, and supply the calculated average value to the averaging circuit 815. Averaging circuit 81
5 receives the supply of the calculation results from the averaging circuits 813 and 814 at the preceding stage, and obtains a further average value of these two calculation results.

Thus, the three averaging circuits 81
3, 814 and 815, the adjacent difference values diff0
An activity value, which is an average value of adjacent difference values for diff7, is obtained and supplied to the comparison circuit 816. In addition, as shown in FIG.
The difference value latched by the fifth latch circuit is supplied to the comparison circuit 816 as a boundary difference value bound1.

In comparison circuit 816, FIG.
As described using, the boundary difference value bound1 and
Activity value and threshold OFST (Threshold
OFST) and a value obtained by adding the boundary difference value b
If it is detected that sound1 is greater than the value obtained by adding the activity value and the threshold OFST, the target point P
(In the case of the examples shown in FIGS. 3 and 4, block boundary 1)
It is determined that there is a step in the image between adjacent pixels sandwiching
An output signal which becomes high level ("1") is output. If it is detected that the boundary difference value bound1 is smaller than the value obtained by adding the activity value and the threshold value OFST, it is determined that there is no image step at the target point P, and the low level (“0”) is set. An output signal is output.
The output signal from the comparison circuit 816 of the first detection circuit 81 is
AND circuit (logical AND circuit) 8 of the second detection circuit 82 at the subsequent stage
21.

As described above, in the first detection circuit 81,
It is possible to detect whether or not there is a step in the image between the pixels sandwiching the point of interest P, and notify the second detection circuit 82 of this. However, even if the equation (1) shown in FIG. 6 is established and it is found that a step occurs in the image between the pixels sandwiching the point of interest P, whether the step of the image is a block boundary or the contour of the image It cannot be determined whether it is a part. If block noise reduction processing is performed on the outline of an image, the image will be blurred and deteriorated.

Therefore, in this embodiment, in the second detection circuit 82 of the block distortion reduction section 8, the point of interest P
The difference between the average value of the pixel values of the four pixels before and the average value of the pixel values of the four pixels after the point of interest P is verified to more reliably determine whether or not the point of interest P is a block boundary. To be able to. To verify the difference between the average value of the pixel values of the four pixels before the target point P and the average value of the pixel values of the four pixels after the target point P, the difference between the luminance before and after the block boundary and the outline of the image This is because there is a clear difference between the luminance difference before and after the portion.

That is, block noise occurs because:
When the bit rate of the image data is low (when the compression ratio is high) or when the motion of the image is fast, the luminance difference before and after the block boundary is relatively small. On the other hand, in the case of an outline of an image, the luminance difference before and after the outline is large. For example, even in the case of a lattice pattern image, the luminance difference is often very different between the lattice part and its background part.

Utilizing this, in the second detection circuit 82 of the block distortion reduction unit 8, as shown in FIG. 7, as shown in (1), four pixels (pixel b, pixel c, pixel An average difference value ArvS, which is the absolute value of the difference between the average pixel value of d, pixel e) and the average pixel value of the four pixels (pixel f, pixel g, pixel h, pixel i) after the point of interest P is determined.

A predetermined threshold value D is set for the average difference value ArvS. If the average difference value ArvS is larger than the threshold value D as shown in equation (2) of FIG.
Since the luminance difference between the preceding and succeeding pixels is large, it is possible to determine that the point of interest P is the contour portion of the image. On the contrary,
When the average difference value ArvS is smaller than the threshold value D, since the luminance difference between the pixels before and after the target point P is small, the target point P can be determined to be a block boundary.

In this case, a predetermined value is set as the threshold value D, such as threshold value D = 16 (10h in hexadecimal notation (h indicates that 10 is hexadecimal notation)). Of course, the threshold value D can be appropriately changed according to the video source to be reproduced.

The second detection circuit 82 will be specifically described. A pixel value (luminance data) is supplied to the latch circuit section 821 of the second detection circuit 82 via the latch circuits 85 and 86. As a result, in the second detection circuit 82, each latch circuit of the latch
Pixel values a to j in the boundary determination processing range 32 shown in FIG.
Will be latched. Then, the second detection circuit 82
Pixel values f, g, h, and i are supplied to the averaging circuit 822 of the second detection circuit 82.
Is supplied with pixel values b, c, d, and e.

The averaging circuit 822 and the averaging circuit 8
23 calculates an average value of the pixel values supplied thereto, and supplies the average value to the comparison circuit 824. In this embodiment, the comparison circuit 824 is configured as shown in the equation (1) of FIG.
An average difference value ArvS that is an absolute value of a difference between the average values from the averaging circuit 822 and the averaging circuit 823 is calculated.

Then, the comparison circuit 824 calculates the average difference value ArvS and the threshold value (Threshold) from the system controller 15 of the reproducing apparatus of this embodiment.
D, and if the average difference value ArvS is smaller than the threshold value D, it is determined that the point of interest P is a block boundary, an output signal having a high level (“1”) is output, and the average difference value ArvS is , The output signal becomes low level (“0”). Second detection circuit 8
In this embodiment, the output signal from the second comparison circuit 824 is supplied to an AND circuit (logical product circuit) 831 of the third detection circuit 83 as shown in FIG.

Then, as described above, the first detection circuit 8
Even if the target point P is determined to be a block boundary by the first detection circuit 82 and the second detection circuit 82, it is still not possible to reliably determine that the target point P is a block boundary. There is a possibility that there is an outline portion of the image that satisfies the condition for determining the block boundary shown in the equation (2) of FIG.

Therefore, in the second detection circuit 82 of the block distortion reduction section 8, when it is determined that the point of interest P is a block boundary, a position one block (eight pixels) away from the point of interest P is determined. And one block (8
It is determined whether or not there is a block boundary at one of the positions separated by (pixels), and if it is determined that there is a block boundary at either one of the positions, the target point P is determined to be a block boundary. To

That is, in this embodiment, the image data read from the disk 20 is DCT-encoded, and block boundaries surely exist every eight pixels. However, the probability that an image outline exists every eight pixels is extremely low. That is, the outline of an image rarely appears regularly like a block boundary. Therefore, when it is determined that the target point P has a block boundary, if it is confirmed that there is no block boundary at least one block before and one block after the target point P, the target point P is determined. Is more likely to be a block boundary than an image outline.

More specifically, as shown in FIG.
In the first detection circuit 81, when a step in the image occurs between adjacent pixels sandwiching the point of interest P, the step of the image is located at least one block before the point of interest P and one block behind the point of interest P. It is determined whether or not there is.

In other words, similarly to the case where it is detected whether or not a step is generated in the image at the point of interest P (block boundary 1) shown in FIG. 4, the block boundary one block before the point of interest P is detected. 0, as shown in the equation (2) in FIG.
d0 is compared with the activity value of the boundary discrimination processing range for 10 pixels based on the block boundary 0, and it is determined whether or not the image has a step even at the block boundary 0.

Similarly, for the block boundary 2 one block after the point of interest P, as shown in equation (3) of FIG.
The boundary difference value bound2 at the block boundary 2 is compared with the activity value of the boundary determination processing range for 10 pixels based on the block boundary 2, and it is determined whether or not a step occurs in the image at the block boundary 2 as well. to decide.

As described above, the step of the image occurs at the point of interest P, and the step of the image occurs at least one block before and one block after the point of interest P. In this case, there is a high possibility that the target point P is a block boundary. Utilizing this, in the third detection circuit 83 of this embodiment, the detection output from the first detection circuit 81 and the detection output from the second detection circuit 82 are ANDed.
The circuit 831 obtains the logical product, and the logical product is always latched by the latch circuit unit 832 of the third detection circuit 83 for three blocks.

In this case, only when both the detection outputs of the first detection circuit 81 and the second detection circuit 82 are at the high level, that is, in both the first detection circuit 81 and the second detection circuit 82, When it is determined that the point P is on the block boundary, the output signal of the AND circuit 831 becomes high level.

Each latch circuit of the latch circuit section 832 of the third detection circuit 83 operates with the block clock BLK as described above. The latch circuit 832 latches the detection result indicating whether or not the point of interest P and a portion that may be a block boundary before and after the point of interest P is a block boundary.

Then, the information latched by each latch circuit in the latch circuit section 832 of the third detection circuit 83 is supplied to the continuity check circuit 832, and the point of interest P and one block before or after that point ( It is confirmed whether one of the positions separated by 8 pixels) is a block boundary.

Then, in the continuity check circuit 832,
When it is confirmed that at least two adjacent block boundaries exist, the continuity check circuit 523 outputs the high-level (“1”) output signal to the subsequent stage because the attention point P is likely to be a block boundary. Data selector 63
To supply. If the continuity check circuit 523 cannot confirm the existence of at least two adjacent block boundaries, the continuity check circuit 523 outputs the output signal of low level (“0”) to the data selector at the subsequent stage. 6
Supply 3

As described above, the third detection circuit 83 detects whether or not a block boundary exists at a position separated by one block before and after the target point P, so that the target point P is truly a block. It is checked whether it is a boundary.

Therefore, at the point of interest P, it is confirmed that there is a step in the image and that the luminance difference between adjacent pixels is small, so that it is a block boundary.
In any one of the positions one block away before and after, when it is confirmed that there is a step in the image and that there is a block boundary because the luminance difference between adjacent pixels is small, the point of interest P is: It is likely to be a block boundary.

However, in the case of an image of a high-rise building having many lattice patterns and windows, there is still a slight possibility that the image may be erroneously determined to be a block boundary despite the outline of the image.

Therefore, in the fourth detection circuit 84 of the block distortion reduction section 8 of this embodiment, the target point P is determined based on the boundary difference value bound1 at the target point P.
Is truly a block boundary.

When it is determined that the point of interest P is truly a block boundary, the degree of block noise reduction processing is determined according to the value of the boundary difference value bound1. In this way, even if a block boundary is erroneously determined, the effect of performing the block noise reduction processing can be reduced.

That is, as shown in FIG. 2, the fourth detection circuit 84 is constituted by a filter coefficient discrimination circuit, and focuses only on two pixels sandwiching the point of interest P, and there is a step having a predetermined level or more between the two pixels. It is determined whether the generated image is an outline portion or a block boundary in which a step of a predetermined level or more is not generated between two pixels. When it is determined that the target point P is truly a block boundary, the boundary difference value bou
Block noise reduction processing of a degree corresponding to nd1 is performed.

Therefore, the fourth detection circuit 84 of the block distortion reduction section 8 receives the boundary difference value bound1 detected by the first detection circuit 81, and receives a signal from the system controller 15 of the reproducing apparatus of this embodiment.
Two thresholds H (Threshold Hi) and a threshold M (Threshold Mid) are supplied. Here, the threshold value H is, for example, about 32, and the threshold value M is
For example, about 16.

When the boundary difference value bound1 is larger than the threshold value M and smaller than the threshold value H as shown in the equation (1) of FIG. 9, the degree of block noise is reduced. When the boundary difference value bound1 is smaller than the threshold value M, the degree of block noise is increased. In other cases, that is, when the boundary difference value bound1 is equal to or larger than the threshold value H, the target point P
Is determined not to be a block boundary but to a contour portion of an image, so that block noise reduction processing is not performed.

FIG. 10 shows the processing in the fourth detection circuit 84 simply. As shown in FIG. 10, depending on which range the boundary difference value bound1 at the point of interest P belongs to the threshold value H and the threshold value M, whether or not the block noise reduction processing is not performed (correction OF
F), whether to perform weak block noise reduction processing or strong block noise reduction processing.

In this embodiment, when the boundary difference value bound1 is larger than the threshold value H, the filter coefficient discriminating circuit as the fourth detecting circuit 84 outputs a signal which becomes low level (“00”). When the boundary difference value bound1 is smaller than the threshold value H and larger than the threshold value M, a signal that becomes “01” is output. Further, the fourth detection circuit 84 determines that the boundary difference value bound1 is
If the value is equal to or smaller than the threshold value M, a signal that becomes “11” is output. As described above, in this embodiment, an output signal expressing three states by two bits is output, for example, so as to be repeated a predetermined number of times.

In FIG. 2, a latch circuit section 87 provided after the fourth detection circuit 84 is for adjusting the phase with the output signal from the third detection circuit 83. Then, an output signal from the fourth detection circuit 84 is supplied to the data selector 93 through the latch circuit section 87.

As described above, in this embodiment, the first detection circuit 81, the second detection circuit 82, and the third detection circuit 83
And the detection result of the fourth detection circuit 84 are supplied to the data selector 93.

On the other hand, as shown in FIG. 2, the data selector 93 includes a noise filter 90 and a noise filter 9.
1. The pixel value (luminance data) from the delay circuit 92 is supplied. That is, the block distortion reduction unit 8 of this embodiment
Is supplied to the latch circuits 85 and 8
6, the noise filter 90, the noise filter 9 through the latch circuit portion 821 of the second detection circuit 82 and the delay circuit 89.
1, supplied to each of the delay circuits 92. Each of the noise filters 90 and 91 performs a predetermined amount of correction on the supplied pixel value.

The noise filter 90 performs a process of reducing the intensity of block noise on the filter range shown in FIG. 3 (a region consisting of eight pixels of four pixels sandwiching the point of interest). That is, the noise filter 90
Performs a correction with a large filter coefficient and a large correction amount.

The noise filter 91 performs the process of reducing the weakness of the block noise in the filter range shown in FIG. 3, as in the case of the noise filter 90. That is. The noise filter 90 performs correction with a small filter coefficient and a small correction amount.

The delay circuit 92 matches the phase of the luminance signal (image data) output from the delay circuit 92 with the phase of the luminance signal (image data) output from the noise filters 90 and 91. And the noise filter 9
The luminance signals subjected to the block noise reduction processing (filtering processing) from 0 and 91 are supplied to the data selector 93 as described above. The luminance signal from the delay circuit 92 on which the block noise reduction processing has not been performed is supplied to the data selector 93.

Then, the data selector 93 outputs a low level signal to either one of the output signal from the third detection circuit 82 and the output signal from the fourth detection circuit 84 supplied through the delay circuit section 87. If the signal is a signal, a luminance signal from the delay circuit 92 on which block noise reduction processing has not been performed is output as an output luminance signal Yout.

Further, the data selector 93 outputs a high-level signal to both the output signal from the second detection circuit 82 and the output signal from the fourth detection circuit 84 supplied through the delay circuit section 87. In some cases, the luminance signal subjected to the intensity block noise reduction processing from the noise filter 90 is output as the output luminance signal Yout.

The data selector 93 determines that the output signal from the second detection circuit 82 is at the high level and the output signal from the fourth detection circuit 84 supplied through the delay circuit 87 is "01". Has a noise filter 9
The luminance signal subjected to the block noise reduction processing of the weakness from 1 is output as an output luminance signal Yout.

The block distortion reduction section 8 includes a delay circuit 9 for adjusting the phase of a luminance signal to be delayed for block boundary detection processing and block noise reduction processing.
4, a color signal whose phase matches the luminance signal Yout is output as an output color signal Cout.

These luminance signal Yout and color signal Cou
The t is supplied to the digital output encoder 9 and the NTSC encoder 12 at the subsequent stage, where they are subjected to respective encoding processes and output.

Next, the detection processing in the four detection circuits 81, 82, 83, and 84 of the block distortion reduction section 8 shown in FIG. 2 will be described with reference to FIGS. 11 to 14. The overall processing flow of the block noise reduction processing in the block distortion reduction unit 8 shown in FIG. 2 will be described with reference to the flowchart in FIG.

FIG. 11 is a flowchart for explaining the block boundary detection process (the process of detecting the presence or absence of a step at the point of interest) performed in the first detection circuit of the block distortion reduction section 8 shown in FIG. .

As shown in FIG. 11, latch circuits 55, 5
The pixel value (luminance data) of the adjacent pixel from No. 6 is
When supplied to the difference calculation circuit 811 of the detection circuit 81, the difference calculation circuit 811 calculates the absolute value of the difference between the pixel values, thereby calculating the adjacent difference value (absolute value) between adjacent pixels in the boundary detection range. The calculated value is supplied to the latch circuit unit 812 and latched for a predetermined number by the multi-stage latch circuit (step S101). As described above with reference to FIG. 5, the processing in step S101 is performed with diff0 to diff
This is a process for sequentially calculating f7 and bound1.

In the first detection circuit 81, the adjacent difference values diff0 to diff7 from the latch circuit section 812 are used by the average value circuits 813, 814, and 815 as described above with reference to FIG. A value Act1 is calculated (step S102), and an output from a predetermined latch circuit of the latch circuit unit 812 is obtained as a boundary difference value bound1 (step S103).

Next, in the first detection circuit 81, the comparison circuit 816 determines whether or not the boundary difference value bound1 is larger than the activity value Act1 (step S104). In the determination processing in step S104, when it is determined that the boundary difference value bound1 is larger than the activity value Act1, the predetermined attention point P shown in FIG. 4 is set as a candidate for a block boundary, and a high-level signal is output. (Step S105), FIG.
The process shown in FIG.

If it is determined in step S104 that the boundary difference value bound1 is not larger than the activity value Act1, it is determined that the predetermined point of interest P shown in FIG. A signal is output, and the processing shown in FIG. 11 ends.

As described above, the first detection circuit 81 of the block distortion reduction section 8 generates a step in an image between pixels sandwiching a predetermined point of interest P based on the boundary difference value bound1 and the activity value Act1. By examining whether or not the target point P is a candidate for a block boundary, whether or not the target point P is a candidate for a block boundary is detected.

FIG. 12 shows a block boundary detection process (verification process of a difference between average values of a plurality of pixel values near a point of interest) performed in the second detection circuit 82 of the block distortion reduction unit 8 shown in FIG. It is a flowchart for explaining.

As shown in FIG. 2, the block distortion reduction section 8
The pixel value (luminance data) from the latch circuit 56 of the second
The pixel values are supplied to the latch circuit portion 821 of the detection circuit 82, and the pixel values of a predetermined number of pixels are latched by the multi-stage latch circuits of the latch circuit portion 821. Then, using the pixel value from the latch circuit portion 821, the averaging circuit 823 obtains an average value AveF of the pixel values of the four pixels before the target point P (step S201). P
Then, the average value AveB of the pixel values of the four pixels is obtained (step S202).

The comparison circuit 82 of the second detection circuit 82
4 obtains an average difference value AveS which is an absolute value of a difference between the average value AveF and the average value AveB (step S20).
3) It is determined whether or not the average difference value AveS is smaller than a predetermined threshold D (step S204).

When it is determined by the determination processing in step S204 that the average difference value AveS is smaller than the predetermined threshold value D, the target point P is set as a block boundary candidate, and a high-level signal is output (step S20).
5), the process shown in FIG. 12 ends. Further, by the determination processing of step S204, the average difference value AveS becomes
When it is determined that the point of interest P is not smaller than the predetermined threshold value D, it is determined that the point of interest P is not on a block boundary, a low-level signal is output, and the processing shown in FIG. 12 ends.

As described above, the second detection circuit 82 of the block distortion reduction unit 8 calculates the average value of four pixels before the target point P,
Whether the target point P is a candidate for a block boundary is detected depending on whether the difference from the average value of the subsequent four pixels is smaller than a predetermined threshold value D.

FIG. 13 is a block boundary detection process (detection of the presence / absence of a block boundary at a position one block before and after a point of interest) performed in the third detection circuit 83 of the block distortion reduction unit 8 shown in FIG. 3 is a flowchart for explaining (processing).

The third detection circuit 83 calculates the logical product of the detection output from the first detection circuit 81 and the detection output from the second detection circuit, and latches the logical product in the latch circuit of the latch circuit section 832. In addition, information indicating whether there is a block boundary one block before the target point P is obtained (step S301), and information indicating whether there is a block boundary one block after the target point P is obtained. (Step S302).

Then, based on the information obtained in step S301, the continuity check circuit 833 of the second detection circuit checks whether or not there is a block boundary before the target point P and one block before the target point P ( Step S30
3).

In the confirmation processing in step S303, when it is confirmed that the target point P and the block boundary exist one block before the target point P, the predetermined target point P shown in FIG. Then, a high-level signal is output (step S304), and the process shown in FIG. 13 ends.

In the confirmation processing in step S303, if it is not confirmed that there is a block boundary before the target point P and one block before the target point P, step S30
In the continuity confirmation circuit 833 of the second detection circuit, based on the information obtained in
It is checked whether there is a block boundary after the block (step S305).

In the confirmation processing in step S305, when it is confirmed that the target point P and the block boundary exists one block after the target point P, the predetermined target point P shown in FIG. , And outputs a high-level signal (step S304), and terminates the processing shown in FIG.

In the confirmation processing in step S305, if it is not confirmed that the target point P and the block boundary exists one block after the target point P, the predetermined target point P shown in FIG. Not determined,
The processing shown in FIG. 13 is completed by outputting a low-level signal.

As described above, the third detection circuit 83 of the block distortion reduction unit 8 determines whether one block before the point of interest P or one block.
By checking whether or not a block boundary exists after the block, it is detected whether or not the point of interest P is a candidate for a block boundary.

FIG. 14 is a block boundary detection process (verification and verification process of a pixel value difference between two pixels near a point of interest) performed in the fourth detection circuit 84 of the block distortion reduction unit 8 shown in FIG. 5 is a flowchart for explaining the following.

As shown in FIG. 2, the fourth detection circuit 84
Is a boundary difference value bound1 that is an absolute value of a difference between pixel values of two pixels sandwiching the point of interest P from the first detection circuit 81.
Is obtained (step S401). Then, the boundary difference value bo
It is determined whether or not und1 is smaller than a predetermined threshold value H from the system controller 15 (step S40).
2).

In step S402, the boundary difference value b
When it is determined that sound1 is smaller than the threshold value H,
The boundary difference value bound1 is determined by the system controller 15
It is determined whether the threshold value is smaller than a predetermined threshold value M (step S403). If it is determined in step S403 that the boundary difference value bound1 is smaller than the threshold value M, a strong block noise reduction process is performed (step S404), and the process illustrated in FIG. 14 ends.

If it is determined in step S403 that the boundary difference value bound1 is greater than or equal to the threshold value M, weak block noise reduction processing is performed (step S405), as shown in FIG. The process ends.

If it is determined in step S402 that the boundary difference value bound1 is equal to or larger than the threshold value H, the point of interest P is determined not to be a block boundary, and a low-level signal is output. Then, the process illustrated in FIG. 14 ends.

As described above, the fourth detection circuit 84 of the block distortion reduction section 8 detects whether or not the target point P is a candidate for a block boundary based on the difference value between two pixels sandwiching the target point P. When the point of interest P is determined to be a block boundary, the degree of block noise reduction processing is determined based on a difference value between two pixels sandwiching the point of interest P. is there.

In the block distortion reduction section 8,
First detection circuit 81, second detection circuit 82, third detection circuit 8
When each of the third and fourth detection circuits 84 determines that the point of interest P is a block boundary, the pixel data near the point of interest is subjected to block noise reduction processing. The processing in the block distortion reduction unit 8 can be summarized as in a flowchart shown in FIG.

That is, in the block distortion reduction section 8, when the luminance signal Yin, the chrominance signal Cin, the horizontal synchronization signal HD, and the pixel clock signal Pclk are supplied thereto, the detection circuits 81, 82, 83, 84 The block boundary detection process starts (step S501).

The first detection circuit 81 determines whether or not the predetermined point of interest P is detected as a block boundary (step S502). The first detection circuit 81 determines whether the point of interest P is at a block boundary. If it is determined that a certain point has been detected, the second detection circuit 82 determines whether or not the predetermined point of interest P has been detected as a block boundary (step S503).

In the determination processing of step S503, when the second detection circuit 82 determines that the target point P is a block boundary, the third detection circuit 83 sets the predetermined target point P at the block boundary. It is determined whether or not the presence is detected (step S504).

In the determination processing of step S504, when the third detection circuit determines that the point of interest P is a block boundary, the fourth detection circuit 84
It is determined whether or not the boundary difference value bound1 at the predetermined point of interest P is smaller than a threshold value H (step S505).
If it is determined that it is smaller, it is determined whether the boundary difference value bound1 at the predetermined point of interest P is smaller than the threshold value M (step S506).

Then, in the determination processing of step S506, the boundary difference value bound1 at the predetermined point of interest P
Is determined to be less than or equal to the threshold value M, the block noise reduction processing of the intensity is executed (step S507), and if it is determined that the boundary difference value Then, the weak block noise reduction processing is executed (step S508).

The process of step S507 is a process of outputting a luminance signal from the noise filter 90 which performs a process of reducing the intensity of block noise. The process of step S508 is a process of outputting a noise filter which performs a process of reducing the weak block noise. This is a process of outputting a luminance signal from the pixel 91.

The first detection circuit 81 and the second detection circuit 8
In any one of the second and third detection circuits 83, if it is detected that the target point P is not a block boundary, the block noise reduction processing is not performed on the luminance signal. In the fourth detection circuit 84, the boundary difference value b
When it is determined that sound1 is larger than the threshold value H, it is determined that the target point P is not a block boundary, and the block noise reduction processing is not performed on the luminance signal.

In the flowchart shown in FIG. 15, the processing in step S501 is performed by each detection circuit 81,
The determination processes in steps S502 to S504 are performed by the first detection circuit 81, the second detection circuit 82, and the third detection circuit 83 in cooperation with each other.

Then, steps S505 and S5
The process 06 is a process performed by the fourth detection circuit 84, and based on the detection output from the third detection circuit 83 and the detection output from the fourth detection circuit 84, the data selector 93.
In step S507, the luminance signal subjected to the block noise reduction processing in steps S507 and S508 or the luminance signal not subjected to the block noise reduction processing is output.

Note that the processes shown in FIGS. 11 to 15 are processes in units of one pixel, and the pixels in the boundary detection processing range are slid one by one in the horizontal direction.
By performing the process for all pixels forming an image, block noise of the entire image can be effectively reduced.

As described above, the block distortion reduction section 8 of the reproducing apparatus of this embodiment includes four detection circuits 81, 82, 8
Luminance signals (pixel values) sequentially supplied using 3, 84
Are sequentially detected as to whether or not the predetermined point of interest P is a block boundary where block noise occurs,
When each of the four detection circuits 81, 82, 83, and 84 determines that the target point P is a block boundary where block noise occurs, pixel data (luminance data) near the target point P On the other hand, block noise reduction processing is performed and output.

The four detection circuits 81, 82, 83,
By using the block boundary 84, the block boundary can be reliably detected without making a mistake between the block boundary and the contour portion of the image, and the block noise reduction processing can be performed with high accuracy. Moreover, since a block boundary can be detected by a relatively simple process as shown in FIG. 2 without using a memory such as a frame memory, the configuration of the block distortion reduction unit 8 and the block An inexpensive block distortion reduction circuit can be configured without complicating the processing in the distortion reduction unit 8.

Note that, in response to an instruction input from the user received through the operation unit 16, the system controller 15 of the reproducing apparatus sets the threshold value D to be supplied to the second detection circuit 82 of the block noise reduction unit 8 stepwise, for example. By switching, the detection accuracy of the block boundary in the fourth detection circuit 84 can be adjusted.

Similarly, in response to an instruction input from the user received through the operation unit 16, the system controller 15 of the reproducing apparatus sets the threshold values H, M, and M to be supplied to the fourth detection circuit 84 of the block noise reduction unit 8. Alternatively, the degree of block noise reduction may be adjusted by, for example, switching the filter coefficients stepwise.

[Other Examples of Block Distortion Reduction Unit 8]
The block distortion reduction unit shown in FIG.
And the second detection circuit 82, the third detection circuit 83, and the fourth detection circuit 84 are used, but the present invention is not limited to this.

For example, when it is desired to configure the block distortion reduction section 8 at a lower cost while maintaining the detection accuracy of the block boundary to some extent, the second detection circuit 82 of the block distortion reduction section 8 shown in FIG. 2 is omitted. You can do so. In this case, the AND circuit 831 of the third detection circuit 83 is not required. Further, the amount of delay in the delay circuit 89 may be increased by the amount of omitting the third detection circuit 83.

In this case, the first detection circuit 8
Since the block boundary is detected by the first, third detection circuit 83, and fourth detection circuit 84, the first detection circuit causes a step in the image between the pixels sandwiching the point of interest P, and the third detection circuit Accordingly, when there is a block boundary one block before or one block after the point of interest P, and the boundary difference bound1 is smaller than a predetermined threshold H,
It is possible to determine that the point of interest P is a block boundary and to perform a block noise reduction process.

Further, as another example, the third detection circuit 83 can be omitted. Specifically, the third detection circuit 83
The latch circuit section 832 and the continuity check circuit 833 may be omitted, and the output signal from the AND circuit 831 may be supplied to the data selector 93 as it is. Further, in this case, the latch circuit section 87 at the subsequent stage of the fourth detection circuit 84 is also unnecessary.

In this case, the first detection circuit 8
Since the block boundary is detected by the first, second and fourth detection circuits 82 and 84, the first detection circuit causes a step in the image between the pixels sandwiching the point of interest P, and the third detection circuit Accordingly, when the average of the luminance difference between a plurality of pixels before and after the target point P is smaller than the predetermined threshold D and the boundary difference bound1 is smaller than the predetermined threshold H, the target point P is determined to be a block boundary. Judgment can be made and block noise reduction processing can be performed.

It is also conceivable to omit the first detection circuit 81. However, in order to obtain the boundary difference value bound1 used in the fourth detection circuit 84, the difference calculation circuit 811 and the latch circuit unit 812 are necessary. If only the block boundary is detected, the fourth
The detection circuit 84 can be omitted. In this case, the reduction level of the block noise may be changed by changing the coefficient of the noise filter with any value. Thus, the four detection circuits 8
A configuration using any three detection circuits among 1, 82, 83, and 84 can also be adopted.

As a minimum necessary detection circuit, a first detection circuit 81 and a fourth detection circuit 84 may be used to detect a block boundary. Further, the first detection circuit 81 and the second detection circuit, the first detection circuit 81 and the third detection circuit 83, the second detection circuit and the third detection circuit, the second detection circuit 82 and the fourth detection circuit 84, the third detection Like the circuit 83 and the fourth detection circuit 84, a configuration using any two detection circuits out of the four detection circuits 81, 82, 83, 84 may be adopted.

However, in order to reduce erroneous discrimination between the block boundary and the outline of the image, at least in addition to the first detection circuit 81 and the fourth detection circuit 84, the second detection circuit It is preferable to use either the second detection circuit 82 or the third detection circuit 83. Most preferably, as shown in FIG.
1, 82, 83 and 84 are used.

The four detection circuits 81, 82, 83,
Even when using 84, the configuration is not limited to FIG. For example, an AND circuit 831 of the third detection circuit 83 is provided at the subsequent stage of the third detection circuit 83, and the detection output from the third detection circuit 83 and the detection output from the second detection circuit 82 are input to this. Is also good. In this case, the first
The detection output from the detection circuit 81 is supplied to the latch circuit section 832 of the third detection circuit 83 as it is.

The first detection circuit 81 and the second detection circuit 8
2. A third detection circuit 83 and a fourth detection circuit 84 are provided in parallel, and a detection output signal from each of them is supplied to one AND circuit. When all the detection circuits detect a block boundary, Alternatively, block noise reduction processing may be performed. In short, in each of the four detection circuits, block noise reduction processing may be performed on the point of interest P detected as a block boundary.

[Second Embodiment] In the first embodiment described above, the case where the block distortion reduction section 8 is provided in a DVD reproducing apparatus has been described as an example. However, it is not limited to this. In recent years, digital satellite broadcasting, digital cable television broadcasting, and the like have also been performed, and image data compressed by block coding using compression encoding may be provided by broadcasting. . Therefore, it is conceivable to mount the block distortion reduction unit in a receiving device that receives digital image data.

The second embodiment is an example in which a receiving apparatus for receiving a digital broadcast is provided with a block distortion reduction unit. FIG. 16 is a block diagram for explaining the receiving apparatus according to the second embodiment. FIG.
As shown in FIG. 16, the receiving apparatus according to the second embodiment receives, tunes to, and demodulates a target digital broadcast signal, and a front end unit (in FIG. 16, described as an FE unit) 101, A descrambling unit 102 for decrypting an encryption process applied to a digital broadcast signal, a digital broadcast signal in which a plurality of broadcast programs are time-division multiplexed,
It has a demultiplexer 103 for extracting data of a target broadcast program.

At the subsequent stage of the demultiplexer 103, an MPEG decoder 104 for decoding image data which has been compression-encoded by the MPEG system is provided as in the case of the reproducing apparatus of the first embodiment. And M
An audio reproduction processing unit 105 is provided after the PEG decoder 104.
And the block distortion reduction unit 8, digital output encoder 9, digital I / F 10, digital output terminal 11, NTSC encoder 12, DSC A / A converter 14 and an analog output terminal 14 are provided.

As shown in FIG. 16, the receiving apparatus according to the second embodiment includes a system controller 115 for controlling each section, an operation section 116, a display section 117,
An IC card I / F 118 and a modem 120 are provided. The system controller 115 includes a CPU, R
It is a microcomputer provided with OM, RAM, EEPROM, and the like.

The operation unit 116 is provided with the system controller 1
15 and receives an instruction input from the user received through the operation unit 116 from the system controller 115.
Being able to be notified. Accordingly, the system controller 115 controls each unit in response to an instruction input from the user, and can perform various controls such as, for example, selecting and selecting a broadcast program in accordance with the instruction of the user. To be.

[0169] Various display messages such as channel selection, operation guidance, and error messages are displayed on the display unit 117 to notify the user. In addition, the IC card I / F 118 includes:
For example, an IC card 119 in which information such as key information necessary for decrypting encryption applied to, for example, a broadcast signal issued from a broadcast company of a digital broadcast program and information such as billing information is loaded and used. Have to be able to.

The modem 120 is connected, for example, to a modular jack 121 connected to a telephone network via a telephone line, so that information can be supplied and information can be transmitted through the telephone network. . For example, it communicates with a charging management center (conditional access center) on the broadcasting station side so that charging processing can be performed when viewing a pay broadcast, or information provided on an IC card can be provided. Have been able to.

The block distortion reduction section 8 at the subsequent stage of the MPEG decoder 104 has the same configuration as the block distortion reduction section 8 of the above-described embodiment. For this reason,
The description of the block distortion reduction unit 8 is omitted. In the case of the receiving apparatus according to the second embodiment, the block distortion reduction unit 8 of the receiving apparatus applies the same processing to the received image data of the digital television broadcast program as in the case of the above-described reproducing apparatus. , Properly reduce the block noise, and reproduce the image provided by the digital TV broadcast well,
You can take advantage of this.

As described in the first and second embodiments, the present invention is applicable not only to a DVD reproducing apparatus and a digital television broadcast receiving apparatus, but also to reproducing block-coded image data. The present invention can also be applied to various types of reproducing apparatuses and recording / reproducing apparatuses, and various receiving apparatuses for receiving image data which is block-encoded and transmitted by wire or wirelessly.

Further, the block distortion reduction circuit according to the present invention can be mounted on various devices for processing digital image data, such as a monitor receiver, to effectively reduce the block noise of the image data to be processed. Can be.

As described above, it is also possible to perform a process of reducing block noise in the vertical direction. Further, in the above-described embodiment, an example has been described in which the block noise reduction processing is performed on a luminance signal, but the same processing can be performed on a color signal.

[0175]

As described above, according to the present invention, the accuracy of discriminating a block boundary is increased, and a process that causes image degradation such as performing a process of reducing block noise on an outline portion of an image is prevented. be able to.

Further, since a memory for storing image data is not used, the block noise can be reduced at low cost without complicating the circuit configuration and processing contents.

The threshold used for the block discrimination and the threshold for determining the degree of the block noise reduction processing are parameterized so that they can be freely changed, so that an appropriate discriminating condition can be found and more effective. It is possible to perform the block boundary discrimination and the block noise reduction processing.

[Brief description of the drawings]

FIG. 1 is a block diagram for explaining an embodiment of a reproducing apparatus according to the present invention.

FIG. 2 is a block diagram illustrating a block distortion reduction circuit according to the present invention.

FIG. 3 is a diagram for describing pixel data used for block boundary detection processing and block noise reduction processing.

FIG. 4 is a diagram for describing pixel data used for block boundary detection processing and block noise reduction processing.

FIG. 5 shows a boundary difference value bound1 and an adjacent difference value diff.
FIG.

FIG. 6 is a diagram for explaining a process of detecting a step at a point of interest P;

FIG. 7 is a diagram for describing block boundary determination according to an average difference value of luminance values at a point of interest P.

FIG. 8 is a diagram for describing detection of whether or not a block boundary exists one block before or one block after a point of interest P;

FIG. 9 is a diagram illustrating a block boundary detection process using a boundary difference value bound1.

FIG. 10 is a diagram for describing setting of a degree of block noise reduction processing using a boundary difference value bound1.

FIG. 11 is a flowchart illustrating a process of a first detection circuit.

FIG. 12 is a flowchart illustrating a process of a second detection circuit.

FIG. 13 is a flowchart illustrating a process of a third detection circuit.

FIG. 14 is a flowchart illustrating a process performed by a fourth detection circuit;

FIG. 15 is a flowchart illustrating a process performed by a block distortion reduction unit.

FIG. 16 is a block diagram for explaining a receiving device according to the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Optical head, 2 ... Rotation drive part, 3 ... Optical head drive part, 4 ... Servo controller, 5 ... RF processor, 6
... MPEG decoder / AV decoder, 7 ... Audio reproduction processing unit, 8 ... Block distortion reduction unit, 9 ... Digital output encoder, 10 ... Digital interface (digital I /
F), 11: digital output terminal, 12: NTSC encoder, 13: D / A converter, 14: analog output terminal,
Reference numeral 15: system controller, 16: operation unit, 17: display unit, 20: disk, 81: first detection circuit, 82: second detection circuit, 83: third detection circuit, 84: fourth detection circuit, 85, 86 ... Latch circuit, 87 ... Latch circuit section, 8
8 ... Block boundary position detection circuit, 89 ... Delay circuit, 9
0, 91: noise filter, 92, 94: delay circuit, 9
3 Data selector 101 Front end (FE
Section), 102: descramble section, 103: demultiplexer, 104: MPEG decoder

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5C052 AA02 CC11 DD06 5C053 FA24 GA11 GB22 GB36 GB37 5C059 KK03 MA00 MA23 PP16 PP25 SS02 SS13 SS30 TA69 TB08 TC10 TC33 TD03 TD05 TD12 UA02 UA05 UA12 5C078 AA04 BA21 CA01 DA01 BC07 BC11 BC14 BC21 BC25 BD03

Claims (24)

[Claims] 1. A circuit for reducing block distortion of input image data which is block-decoded and sequentially supplied when block-encoded digital image data is output after being block-decoded. For the data, based on a difference value of pixel values between pixels adjacent to a predetermined target position and an average value of difference values of adjacent pixel values within a predetermined range including the target position, whether the target position is a block boundary. Step detection means for detecting whether or not the input image data, at least one of one block before and one block after the target position, before and after boundary detection means for detecting whether there is a block boundary, Pixel difference detection for detecting whether or not the target position is a block boundary based on a difference value of pixel values between pixels adjacent to the target position with respect to the input image data A step, the step difference detecting means, the front / rear boundary detecting means, and the pixel difference detecting means, when it is detected that the target position is a block boundary, a block distortion reduction process for the target position portion And a reduction processing means for outputting the input image data subjected to the processing. 2. A circuit for reducing the block distortion of input image data which is block-decoded and sequentially supplied when block-encoded digital image data is output after being block-decoded. For the data, based on a difference value of pixel values between pixels adjacent to a predetermined target position and an average value of difference values of adjacent pixel values within a predetermined range including the target position, whether the target position is a block boundary. A step detecting means for detecting whether or not the input image data has the target position based on an average value of pixel values of a plurality of pixels at a preceding stage and a pixel value of a plurality of pixels at a subsequent stage of the target position. A plurality of pixel difference detection means for detecting whether or not the target position is a block boundary; and, for the input image data, the target position Pixel difference detecting means for detecting whether or not the target position is a block boundary, the step difference detecting means, the plural pixel difference detecting means, and the pixel difference detecting means have detected that the target position is a block boundary. And a reduction processing unit that outputs input image data obtained by performing a block distortion reduction process on the position of interest in the case. 3. A circuit for reducing the block distortion of input image data which is block-decoded and sequentially supplied when block-encoded digital image data is output after being block-decoded. For the data, based on a difference value of pixel values between pixels adjacent to a predetermined target position and an average value of difference values of adjacent pixel values within a predetermined range including the target position, whether the target position is a block boundary. Step detection means for detecting whether or not the input image data, at least one of one block before and one block after the target position, before and after boundary detection means for detecting whether there is a block boundary, For the input image data, based on the average value of the pixel values of a plurality of pixels at the preceding stage of the target position and the average value of the pixel values of the plurality of pixels at the subsequent stage, the target position is shifted. A plurality of pixel difference detecting means for detecting whether or not the target position is a block boundary, based on a difference value of a pixel value between pixels adjacent to the target position with respect to the input image data. The pixel difference detecting means to be detected, the step difference detecting means, the front and rear boundary detecting means, the plural pixel difference detecting means, and the pixel difference detecting means have detected that the target position is a block boundary. And a reduction processing unit that outputs input image data obtained by performing a block distortion reduction process on the position of interest in the case. 4. The block distortion reduction circuit according to claim 2, wherein said plurality of pixel difference detecting means comprises: an average value of pixel values of a plurality of pixels at a preceding stage of said target position and a plurality of pixels at a subsequent stage thereof. Based on a difference between the average value of the pixel values and a predetermined threshold value, it is to detect whether the target position is a block boundary, and the predetermined threshold value can be changed as necessary. Block distortion reduction circuit. 5. The block distortion reduction circuit according to claim 1, wherein said reduction processing means is configured to determine a difference between pixel values of pixels adjacent to the target position. A block distortion reduction circuit, wherein a degree of the reduction processing is changed. 6. The block distortion reduction circuit according to claim 5, wherein said reduction processing means is configured to determine the difference between pixel values between pixels adjacent to the target position and a predetermined threshold value based on a predetermined threshold value. A block distortion reduction circuit for determining a degree of reduction processing, wherein the degree of reduction processing according to the difference value can be changed by changing the predetermined threshold value. 7. A reading means for reading the digital image data from a recording medium on which block-encoded digital image data is recorded, and receiving the digital image data from the reading means, A block decoding unit that performs block decoding on the input image data from the block decoding unit, and a difference value of a pixel value between pixels adjacent to a predetermined target position and a predetermined value within a predetermined range including the target position. A step detecting means for detecting whether or not the target position is a block boundary based on an average value of difference values between adjacent pixel values; and one block before the target position with respect to input image data from the block decoding means. Front and rear boundary detecting means for detecting whether or not a block boundary exists in at least one of the block and one block after; A pixel difference detection unit that detects whether or not the target position is a block boundary based on a difference value of a pixel value between pixels adjacent to the target position with respect to the input image data from the lock decoding unit; Means, the front / rear boundary detecting means, and the pixel difference detecting means, when it is detected that the target position is a block boundary, input image data obtained by subjecting the target position portion to block distortion reduction processing And a reduction processing means for outputting a signal. 8. A reading means for reading the digital image data from a recording medium on which block-encoded digital image data is recorded, and receiving the digital image data from the reading means, A block decoding unit that performs block decoding on the input image data from the block decoding unit, and a difference value of a pixel value between pixels adjacent to a predetermined target position and a predetermined value within a predetermined range including the target position. A step detecting means for detecting whether or not the target position is a block boundary based on an average value of difference values of adjacent pixel values; and a plurality of input image data from the block decoding means, Based on the average value of the pixel values of the pixels and the average value of the pixel values of a plurality of subsequent pixels, it is determined whether the target position is a block boundary. A plurality of pixel difference detecting means for detecting the input image data from the block decoding means, and detecting whether or not the target position is a block boundary based on a pixel value difference between pixels adjacent to the target position. Pixel difference detecting means, the step detecting means, the multiple pixel difference detecting means, and the pixel difference detecting means, when it is detected that the target position is a block boundary, the target position part A reproduction apparatus comprising: a reduction processing unit configured to output input image data that has been subjected to block distortion reduction processing. 9. A reading means for reading the digital image data from a recording medium on which block-encoded digital image data is recorded; and receiving the digital image data from the reading means to receive the digital image data. A block decoding unit that performs block decoding on the input image data from the block decoding unit, and a difference value of a pixel value between pixels adjacent to a predetermined target position and a predetermined value within a predetermined range including the target position. A step detecting means for detecting whether or not the target position is a block boundary based on an average value of difference values between adjacent pixel values; and one block before the target position with respect to input image data from the block decoding means. Front and rear boundary detecting means for detecting whether or not a block boundary exists in at least one of the block and one block after; For the input image data from the lock decoding means, based on the average value of the pixel values of a plurality of pixels at the preceding stage of the target position and the average value of the pixel values of the following pixels at the subsequent stage, the target position is a block boundary. A plurality of pixel difference detecting means for detecting whether the target position is a block boundary based on a difference between pixel values of pixels adjacent to the target position with respect to input image data from the block decoding unit. Pixel difference detection means, the step difference detection means, the front and rear boundary detection means, the multiple pixel difference detection means, and the pixel difference detection means, it is detected that the target position is a block boundary And a reduction processing means for outputting input image data obtained by performing a block distortion reduction process on the position of interest in the event of occurrence. 10. The reproducing apparatus according to claim 8, wherein the plurality of pixel difference detecting means includes an average value of pixel values of a plurality of pixels at a preceding stage of the target position and a plurality of pixels of a following stage. Detecting whether or not the target position is a block boundary based on a difference between the average value of the values and a predetermined threshold value, wherein the predetermined threshold value can be changed as necessary. apparatus. 11. The reproducing apparatus according to claim 7, wherein the reduction processing means is configured to perform the reduction processing in accordance with a difference value of a pixel value between pixels adjacent to the target position. A reproducing apparatus characterized by changing the degree of reduction processing. 12. The reproducing apparatus according to claim 11, wherein the reduction processing means performs the reduction processing based on a difference value between pixel values of pixels adjacent to the target position and a predetermined threshold. A reproducing apparatus, wherein the degree of the reduction processing can be changed by changing the predetermined threshold value, and the degree of the reduction processing according to the difference value can be changed. 13. A receiving means for receiving digital image data transmitted by being block-encoded, a demodulating means for demodulating the digital image data received by the receiving means, and a demodulated signal from the demodulating means. A block decoding unit that receives the supply of the digital image data and performs block decoding on the digital image data; and, for input image data from the block decoding unit, a pixel value between pixels adjacent to a predetermined target position. A step detecting means for detecting whether or not the target position is a block boundary, based on the difference value of the target pixel and an average value of the difference values of adjacent pixel values within a predetermined range including the target position; , The input image data has a block boundary at least one block before and one block after the target position. Means for detecting whether or not the target position is a block boundary based on a difference between pixel values of pixels adjacent to the target position with respect to input image data from the block decoding unit. A pixel difference detecting unit that detects whether the target position is a block boundary by the pixel difference detecting unit, the step difference detecting unit, the front / rear boundary detecting unit, and the pixel difference detecting unit. A receiving apparatus comprising: a reduction processing unit configured to output input image data obtained by performing a block distortion reduction process on a portion thereof. 14. A receiving means for receiving digital image data transmitted by being block-encoded, a demodulating means for demodulating the digital image data received by the receiving means, and a demodulated signal from the demodulating means. A block decoding unit that receives the supply of the digital image data and performs block decoding on the digital image data; and, for input image data from the block decoding unit, a pixel value between pixels adjacent to a predetermined target position. A step detecting means for detecting whether or not the target position is a block boundary, based on the difference value of the target pixel and an average value of the difference values of adjacent pixel values within a predetermined range including the target position; Of the input image data from the target pixel based on the average value of the pixel values of a plurality of pixels at the preceding stage of the target position and the average value of the pixel values of the following pixels at the subsequent stage A plurality of pixel difference detecting means for detecting whether or not the target position is a block boundary; and, for input image data from the block decoding means, based on a difference value of pixel values between pixels adjacent to the target position. The target position is a block boundary by the pixel difference detecting means for detecting whether the target position is a block boundary, the step detecting means, the multiple pixel difference detecting means, and the pixel difference detecting means. And a reduction processing unit configured to output input image data obtained by performing block distortion reduction processing on the position of interest when the detection is detected. 15. A receiving means for receiving digital image data transmitted by being block-encoded, a demodulating means for demodulating the digital image data received by the receiving means, and a demodulated signal from the demodulating means. A block decoding unit that receives the supply of the digital image data and performs block decoding on the digital image data; and, for input image data from the block decoding unit, a pixel value between pixels adjacent to a predetermined target position. A step detecting means for detecting whether or not the target position is a block boundary, based on the difference value of the target pixel and an average value of the difference values of adjacent pixel values within a predetermined range including the target position; , The input image data has a block boundary at least one block before and one block after the target position. The front and rear boundary detecting means for detecting whether or not, the input image data from the block decoding means, the average value of the pixel value of a plurality of pixels of the preceding stage of the target position and the pixel value of a plurality of pixels of the subsequent stage A plurality of pixel difference detecting means for detecting whether or not the target position is a block boundary, and a difference value of a pixel value between pixels adjacent to the target position for input image data from the block decoding means. Pixel difference detecting means for detecting whether or not the target position is a block boundary, based on the, the step difference detecting means, the front and rear boundary detecting means, the plurality of pixel difference detecting means, and the pixel difference detecting means And a reduction processing unit configured to output, when the target position is a block boundary, input image data obtained by performing a block distortion reduction process on the target position. Receiving apparatus according to claim Rukoto. 16. The receiving apparatus according to claim 14, wherein said plurality of pixel difference detecting means includes an average value of pixel values of a plurality of pixels at a preceding stage of said target position and a plurality of pixels of a following stage. Detecting whether or not the target position is a block boundary based on a difference between the average value and a predetermined threshold value, wherein the predetermined threshold value can be changed as necessary. circuit. 17. The method of claim 13, claim 14 or claim 1.
5. The receiving apparatus according to claim 5, wherein the reduction processing unit changes a degree of the reduction processing according to a difference value of a pixel value between pixels adjacent to the target position. 18. The receiving apparatus according to claim 17, wherein said reduction processing means performs the reduction processing based on a difference value between pixel values of pixels adjacent to the target position and a predetermined threshold value. The receiving apparatus, wherein the degree of the reduction processing can be changed by changing the predetermined threshold, and the degree of the reduction processing according to the difference value can be changed. 19. A method for reducing the block distortion of input image data that is block-decoded and sequentially supplied when block-encoded digital image data is output after being block-decoded. For the data, based on a difference value of pixel values between pixels adjacent to a predetermined target position and an average value of difference values of adjacent pixel values within a predetermined range including the target position, whether the target position is a block boundary. A level difference detecting step of detecting whether or not a block boundary exists at least one of one block before and one block after the target position with respect to the input image data; For the input image data, a pixel difference detection for detecting whether or not the target position is a block boundary based on a difference value of a pixel value between pixels adjacent to the target position. In the step detecting step, the front and rear boundary detecting step, and the pixel difference detecting step, when it is detected that the target position is a block boundary, block distortion of the target position portion A block distortion reduction method characterized by outputting input image data subjected to a reduction process. 20. A method for reducing the block distortion of input image data that is block-decoded and sequentially supplied when block-coded digital image data is output after being block-decoded. For the data, based on a difference value of pixel values between pixels adjacent to a predetermined target position and an average value of difference values of adjacent pixel values within a predetermined range including the target position, whether the target position is a block boundary. A step detecting step of detecting whether or not the input image data has the target position based on an average value of pixel values of a plurality of pixels at a preceding stage of the target position and an average value of pixel values of a plurality of pixels at a subsequent stage of the target position. A plurality of pixel difference detecting step of detecting whether or not the target position is a block boundary, and regarding the input image data, the target position is determined based on a pixel value difference value between pixels adjacent to the target position. A pixel difference detecting step of detecting whether or not the boundary is a lock boundary, wherein the step difference detecting step, the multiple pixel difference detecting step, and the pixel difference detecting step detect that the target position is a block boundary. A block distortion reduction circuit configured to output input image data obtained by performing a block distortion reduction process on the position of interest in the case of performing the processing. 21. A method for reducing block distortion of input image data which is block-decoded and sequentially supplied when block-encoded digital image data is output after being block-decoded. For the data, based on a difference value of pixel values between pixels adjacent to a predetermined target position and an average value of difference values of adjacent pixel values within a predetermined range including the target position, whether the target position is a block boundary. A level difference detecting step of detecting whether or not a block boundary exists at least one of one block before and one block after the target position with respect to the input image data; For the input image data, the target position is determined based on an average value of pixel values of a plurality of pixels at a preceding stage of the target position and an average value of pixel values of a plurality of pixels at a subsequent stage. A plurality of pixel difference detecting step of detecting whether or not the target position is a lock boundary; and detecting whether or not the target position is a block boundary based on a difference value of a pixel value between pixels adjacent to the target position with respect to the input image data. A pixel difference detecting step, wherein the step detecting step, the front and rear boundary detecting step, the plural pixel difference detecting step, and the pixel difference detecting step detect that the target position is a block boundary. In such a case, a block distortion reduction method is characterized in that input image data obtained by performing a block distortion reduction process on the position of interest is output. 22. The block distortion reduction method according to claim 20, wherein in the multiple pixel difference detecting step, an average value of pixel values of a plurality of pixels at a preceding stage of the target position and a plurality of pixels at a subsequent stage are included. Based on the difference between the average value of the pixel values of the pixels and a predetermined threshold, whether or not the target position is a block boundary is detected, and the predetermined threshold can be changed as necessary. Characteristic block distortion reduction method. 23. Claim 19, Claim 20, or Claim 2
The block distortion reduction method according to claim 1, wherein in the reduction processing step, a degree of the reduction processing is changed according to a difference value of a pixel value between pixels adjacent to the target position. Distortion reduction method. 24. The block distortion reduction method according to claim 23, wherein, in the reduction processing step, a difference between pixel values between pixels adjacent to the target position and a predetermined threshold value are determined.
The degree of the reduction processing is determined, and the degree of the reduction processing according to the difference value can be changed by changing the predetermined threshold value.