JP2002231601A - Method of forming resist pattern, and method of manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method of forming a resist pattern, by which the dimension of a resist pattern can be reduced with high dimensional controllability, regardless of the roughness and denseness of the pattern, and to provide a method of manufacturing a semiconductor device using the method. SOLUTION: At heat treatment on the resist pattern for adjusting the dimension of the pattern after the pattern has been formed by lithography, heat treatment is performed at a temperature T1( deg.C), which falls within the range of T2( deg.C) to T+4 deg.C (where T2 is the softening temperature of the resist forming the pattern). Alternatively, the heat treatment is divided into a first heat treatment, which is performed at a temperature T3( deg.C) (T3<T2) and a second heat treatment which is performed at the temperature T1( deg.C) (T1>=T2). Still alternatively, the heat treatment is performed, by continuously making the temperature change from the temperature T3( deg.C) (T3<T2) to the temperature T1( deg.C) (T1>=T2).

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for forming a resist pattern and a method for manufacturing a semiconductor device.

[0002]

2. Description of the Related Art In recent years, elements have been miniaturized, and patterns formed in a photolithography process have been required to be further miniaturized. In order to satisfy this demand, the exposure wavelength has been shortened, and the high NA
While many methods for miniaturizing a resist pattern, such as (numerical aperture) and optimizing a resist material, have been proposed, JP-A-1-307228 and JP-A-7-45510 have been proposed.
As described in Japanese Patent Application Publication, there is a method in which after forming a resist pattern composed of an unexposed portion resist, a heat treatment is performed at a temperature equal to or higher than the resist softening temperature, and the pattern is miniaturized by thermal flow of the resist.

[0003]

However, in the above-mentioned method, since all the resist patterns on the entire wafer thermally flow, there are problems such as shape distortion in asymmetric pattern arrangement and poor dimensional controllability. In particular, in a dense pattern with a narrow pitch, the ratio of the volume of the resist flown per unit volume is smaller than that in the sparsely arranged pattern, so that the amount of change due to the heat treatment is small.
That is, the amount of deformation of the resist pattern due to the heat treatment varies due to the difference in density between the patterns, and it is difficult to control the pattern size reduction by the heat treatment, particularly for a dense pattern.

Accordingly, an object of the present invention is to provide a method of forming a resist pattern and a method of forming a resist pattern capable of reducing the pattern size with high dimensional controllability irrespective of the pattern density. An object of the present invention is to provide a method for manufacturing a semiconductor device using the method.

[0005]

According to a first aspect of the present invention, a resist pattern is formed by lithography, and a heat treatment is performed to adjust the pattern size. In the method of forming a resist pattern, when the softening temperature of the resist used to form the resist pattern is T ₂ (° C.), T ₂ ≦ T ₁
The heat treatment is performed at a temperature T ₁ (° C.) in a range of ≦ T ₂ + 5 ° C.

According to a second aspect of the present invention, there is provided a method of manufacturing a semiconductor device having a step of forming a resist pattern by lithography and then performing a heat treatment for adjusting the pattern dimension. T ₂ (° C.), T ₂ ≦
The heat treatment is performed at a temperature T ₁ (° C.) within a range of T ₁ ≦ T ₂ + 4 ° C.

In the first and second aspects of the present invention, from the viewpoint of effectively suppressing the rapid flow of the resist due to the heat treatment and realizing a gentle flow, the heat treatment temperature T
₁ (° C.) is preferably T ₂ + 3.5 ° C. or less, more preferably T ₂ + 3 ° C. or less. On the other hand, from the viewpoint of flowing the resist by heat treatment while maintaining high dimensional controllability, the temperature T ₁ (° C.) of the heat treatment is preferably T ₂ +0.
5 ° C. or higher, more preferably T ₂ + 1 ° C. or higher. The temperature T ₁ (° C.) of the heat treatment can be set to a temperature within the range of each combination of these upper and lower limits.

According to a third aspect of the present invention, there is provided a resist pattern forming method in which a resist pattern is formed by lithography, and then a heat treatment is performed to adjust the pattern size. T ₂ (° C.), the softening temperature of
_A step of performing a first heat treatment at a temperature T ₃ (° C.) in a range of ₃ <T ₂ and a temperature T ₁ (° C.) in a range of T ₁ ≧ T ₂ after performing the first heat treatment. And performing a second heat treatment.

According to a fourth aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising a step of forming a resist pattern by lithography and then performing a heat treatment for adjusting the pattern size. T ₂ (° C.), the softening temperature of T ₃ <
Performing a first heat treatment at a temperature T ₃ (° C.) within a range of T ₂ , and performing a first heat treatment at a temperature T ₁ (° C.) within a range of T ₁ ≧ T ₂ after performing the first heat treatment. 2) performing a heat treatment.

In the third and fourth aspects of the present invention, the flow does not start, but from the viewpoint of obtaining a uniform state in which the movement of the segments in the constituent resin molecules in the resist or the intramolecular movement is active. Heat treatment temperature T ₃ (° C)
Is preferably T ₂ -2 ° C. or higher, more preferably T ₂ -1.
5 ° C. or higher, more preferably T ₂ −1 ° C. or higher, still more preferably T ₂ −0.5 ° C. or higher, while preferably T ₂ −0.
5 ° C. or less. Temperature T ₃ (° C.) of this first heat treatment
Can be set to a temperature within the range of each combination of these upper and lower limits. Further, the temperature T ₁ (° C.) of the second heat treatment is determined according to the first and second embodiments of the present invention.
It is the same as the invention of the above.

[0011] The fifth invention of the present invention, after forming a resist pattern by lithography, the resist pattern forming method which is to perform a heat treatment to adjust the pattern dimension, T ₂ -2 ℃ ≦ T _From the temperature T ₃ (° C.) in the range of ₃ <T ₂ , T ₂ ≦ T ₁ ≦ T ₂ + 4 ° C.
The above heat treatment is performed while continuously changing the temperature to a temperature T ₁ (° C.) within the range described above.

According to a sixth aspect of the present invention, there is provided a method of manufacturing a semiconductor device having a step of forming a resist pattern by lithography and then performing a heat treatment for adjusting the pattern dimension, wherein T ₂ -2 ° C. ≦ T _The above heat treatment is performed while the temperature is continuously changed from a temperature T ₃ (° C.) in a range of ₃ <T _{2 to} a temperature T ₁ (° C.) in a range of T ₂ ≦ T ₁ ≦ T ₂ + 4 ° C. It is characterized by doing so.

In the fifth and sixth aspects of the present invention, the temperature T ₃ (° C.) is the same as the third and fourth aspects of the present invention, and the temperature T ₁ (° C.) This is the same as the first and second inventions.

FIG. 1 shows the relationship among T ₁ , T ₂ , and T _{3 in} the present invention. In the present invention, typically, the resist pattern has a repeating pattern. In particular,
The pattern shape has a shape such as a circle, an ellipse, a groove, or a punched shape having a contour including a plurality of curves and sides.

In the first and second aspects of the present invention configured as described above, when a heating process is performed on a resist pattern formed by lithography, the heating temperature is set to a value close to the softening temperature of the unexposed portion resist. By setting the temperature, rapid flow of the resist can be suppressed. Thereby, even when there is a density difference between patterns in which the volume ratio of the resist to be flown per unit volume is different from each other, it is possible to maintain the tendency of density dependence during normal pattern formation and resize the pattern dimension. It becomes possible.

In the third and fourth aspects of the present invention, the softening temperature is lower than the softening temperature of the resist before flowing the resist by the second heat treatment.
By performing the heat treatment at a temperature close to the softening temperature, the flow does not start, but a uniform state in which the movement of the segments in the constituent resin molecules in the resist or the intramolecular movement is active can be obtained. Then, in this state, by performing the second heat treatment at a temperature higher than or equal to the softening temperature of the unexposed portion resist, a very gentle pattern flow can be realized. Thereby, even when there is a density difference between patterns in which the volume ratio of the resist to be flown per unit volume is different from each other, it is possible to maintain the tendency of density dependence during normal pattern formation and resize the pattern dimension. It becomes possible.

In the fifth and sixth aspects of the present invention constructed as described above, the temperature of the unexposed portion is lower than the softening temperature of the unexposed portion resist and close to the softening temperature T ₃ (° C.). By performing the heat treatment while continuously changing the temperature to a temperature T ₁ (° C.) which is equal to or higher than the softening temperature of the resist, the flow does not start, but the movement of the segments in the constituent resin molecules in the resist or Starting from a homogeneous state in which intramolecular motion is active, the state can be changed to a flowing state, and a very gentle pattern flow can be realized. Thereby, even when there is a density difference between patterns in which the volume ratio of the resist to be flown per unit volume is different from each other, it is possible to maintain the tendency of density dependence during normal pattern formation and resize the pattern dimension. It becomes possible.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings. Unless otherwise specified, the handling and implementation process of the photoresist solution after microfiltration was performed in a clean room of a yellow room where temperature and humidity were controlled. FIG. 2 shows a process flow of a method for forming a resist pattern according to an embodiment of the present invention.

In this embodiment, first, a resist is coated on a substrate to be processed to a predetermined thickness, for example, 0.73 μm.
m (Step 1). As the substrate, a silicon wafer, a silicon wafer having steps on which various insulating films, wirings, electrodes, etc. are formed on the surface or other semiconductor wafers can be used. Here, an 8-inch silicon wafer is used as an example. Used. Further, as the resist material, a positive type chemically amplified resist for KrF (acetal type) is used, but is not limited thereto. That is, any other resist material that causes heat flow can be used, and the exposure wavelength is not limited to KrF. Further, the baking temperature, heating temperature, and time described later are not limited thereto. ACT8 manufactured by Tokyo Electron Ltd. was used for resist coating and development.

Next, when forming a pattern by selectively removing a desired portion of the resist by a normal photolithography process, the following steps were performed. After applying the resist, the coated substrate is placed on a hot plate at 90 ° C.
Prebaking treatment at a heating temperature of 1 minute (step 2), and then a Nikon KrF scanner (NSR-2)
02A), exposure is performed at an exposure amount of 55 mJ / cm ² through a photomask (reticle) for forming a contact hole pattern (step 3).

Subsequently, the exposed substrate is placed on a hot plate and subjected to a post-exposure bake treatment at a heating temperature of 100 ° C. for one minute (Step 4). After this,
The resist pattern is formed by developing with a 2.38% aqueous solution of tetramethylammonium hydroxide (step 5) and rinsing with pure water (step 6).

Usually, after this, the substrate after development is placed on a hot plate and subjected to a post-baking treatment at a heating temperature of 110 ° C. for 1 minute (step 7).
A contact hole pattern having a diameter of 260 nm is formed for the design of an isolated hole (space 2 μm) equivalent to nm. The reticle used includes a plurality of arrays having different pattern array densities, that is, different distances from adjacent patterns. This is used as a reference when showing the effect of the present invention. The process flow of this reference corresponds to FIG.
The measurement results of the hole diameters in the dense pattern arrangement of nm and the sparse pattern arrangement of 2000 nm in space are as shown in FIG.

The resist pattern formed in step 6 has a softening temperature T ₂ = 135 ° C. and T ₁ = 136.
Heat treatment was performed at 90 ° C. for 90 seconds (step 8). The process flow corresponds to FIG. 2B, and the hole diameter measurement results for the dense pattern array with a space of 260 nm and the sparse pattern array with a space of 2000 nm are as shown in FIG. 3B.

For the resist pattern formed in step 6, the softening temperature T ₂ = 135 ° C., and T ₁ = 138.
Heat treatment was performed at 45 ° C. for 45 seconds (step 9). The process flow corresponds to B in FIG. 2, and the measurement results of the hole diameters in the dense pattern arrangement in the space of 260 nm and the sparse pattern arrangement in the space of 2000 nm are as shown in FIG.

For the resist pattern formed in step 6, the softening temperature T ₂ = 135 ° C., and T ₃ = 134.
C. for 60 seconds, then T ₁ = 138 ° C.
For 45 seconds (step 10). The process flow corresponds to C in FIG. 2, and the measurement results of the hole diameters in the dense pattern arrangement in the space 260 nm and the sparse pattern arrangement in the space 2000 nm are as shown in FIG. 3D.

The resist pattern formed in step 6 was subjected to a heat treatment at 140 ° C. for 45 seconds (step 1).
1). The hole diameter measurement results for the dense pattern arrangement in the 260 nm space and the sparse pattern arrangement in the 2000 nm space are as shown in FIG. 3E. This is a comparative example with the present invention. Compared with the dimensional difference of B, C, and D in FIG.

The resist pattern formed in step 6 was subjected to a heat treatment at 138 ° C. for 60 seconds (step 1).
2). The measurement results of the hole diameters in the dense pattern arrangement in the space 260 nm and the sparse pattern arrangement in the space 2000 nm are as shown in FIG. 3F. This is a comparative example with the present invention. Compared with the dimensional difference of B, C, and D in FIG.

As can be seen from FIG. 3, the pattern size is reduced by the processes of Steps 8, 9, and 10 with respect to the hole size serving as the reference of Step 7. However, the coarse / dense dependencies are different for each process, and the coarse / dense dependencies are significantly reduced for steps 8, 9 and 10 within the scope of the present invention, while the steps outside the scope of the present invention are reduced. 11 and 12 have remarkably coarse / dense dependency.

The resist pattern formed in step 6 has a softening temperature T ₂ = 135 ° C. and T ₃ =
The heat treatment was performed while changing the temperature continuously from 134 ° C. to T ₁ = 138 ° C. over 90 seconds. The process flow corresponds to D in FIG. As a result, it was possible to form a fine hole having a small dependency on density. FIG. 4 shows the coarse / dense dependency (space dependency) of the pattern arrangement of the hole diameter measurement result for each heat treatment condition.

As described above, according to this embodiment,
After forming a resist pattern after development rinsing in a lithographic process, a heat treatment at a temperature T ₁ of the softening temperature near the unexposed portion resist applied, or lower than the softening temperature of the unexposed portions resist, at a temperature T ₃ of the softening temperature near After the heat treatment, heat treatment is performed at a temperature T ₁ near the softening temperature of the unexposed portion resist, or the unexposed portion resist is softened from a temperature T ₃ lower than the softening temperature of the unexposed portion resist and near the softening temperature. by that the heat treatment is performed while continuously changing the temperature to the temperature T ₁ of the temperature near, it is possible to form a fine pattern having reduced density dependency after the pattern deformation. In particular, it is possible to form fine holes in which a plurality of arrangement patterns of different densities, which are difficult to miniaturize, are present in the same layer, and it is possible to realize the manufacture of an VLSI using photolithography.

The method of forming a resist pattern according to this embodiment is applicable to various semiconductor devices, specifically, for example,
In a MOS LSI, a CMOS LSI, a bipolar LSI, a bipolar CMOS LSI, and the like, the present invention can be applied to forming various patterns by etching, ion implantation, or the like.

Although the embodiment of the present invention has been specifically described above, the present invention is not limited to the above-described embodiment, and various modifications based on the technical idea of the present invention are possible. .

For example, the numerical values and processes described in the above-described embodiment are merely examples, and different numerical values and processes can be used as necessary.

In the process of forming a resist pattern by lithography and then performing heat treatment at a temperature near the softening temperature of the resist to reduce the pattern size, a resin composition film layer is interposed between the layer to be processed and the resist layer. To increase the pattern size change control range (the width of the difference between the initial pattern size and the critical dimension when the pattern flows due to heat treatment and resizing), and determines whether or not the processing is performed. Use
A resist pattern having a desired fine dimension can be formed. More specifically, when a resin composition film layer is interposed between the layer to be processed and the photoresist layer, the amount of pattern reduction in the heat treatment after pattern formation is large, It is possible to obtain dimensions. Further, on the same plane, a resin composition film layer is selectively provided between a layer to be processed and a photoresist layer, and a portion where the resin composition film layer is not provided is provided. In processing, it is possible to selectively control the dimensions of the pattern.

That is, the above-mentioned Japanese Patent Application Laid-Open No. Hei.
In the method described in Japanese Patent Application Laid-Open No. 7-45510 and Japanese Patent Application Laid-Open No. 7-45510, since the entire resist pattern of the wafer thermally flows, there are problems such as distortion of the shape in an asymmetric pattern arrangement and poor dimensional controllability. Above, even under the same thermal conditions, the hurdles that must be solved for use in the actual manufacturing process, such as the reduction amount differs depending on the size of the initial diameter and the reduction amount differs depending on the pitch of the pattern arrangement, etc. There are several methods, but these methods can solve these problems.

That is, when a heat treatment is performed on the formed resist pattern, the resist flows and the dimensions of the pattern are reduced. Factors that determine the size reduction amount are determined by a plurality of conditions such as the physical properties of the resist composition, the heat treatment temperature, time, pattern shape, pattern arrangement, and heating step. Many studies and discussions have been made on these factors so far, but here, in addition to the above-mentioned factors, when this flow occurs, the resist pattern that flows and the lower layer existing under the pattern The relationship was found.

In a resist pattern flowing by heat treatment, interfacial tension acts between the resist layer and the lower layer, and at the pattern interface, interfacial tension acts on the resist layer and the lower layer. The force that resists the flow due to the heat treatment
Works at the interface with the lower layer. That is, it is considered that the balance of these forces changes the flow state of the resist pattern due to the heat treatment, and consequently greatly affects the dimensional change amount due to the heat treatment. That is, when the direction vector of the flow of the resist pattern by the above-described heat treatment is large with respect to the sum vector of the interfacial tension and the surface tension of the lower layer, the resist pattern is likely to flow and the size reduction amount can be increased. , The size of the initial can be set large, and the effect of easily securing the lithography characteristic margin can be obtained. Further, at this time, since the flow rate per unit temperature is large, the heat treatment temperature can be set lower, and there is an effect of suppressing the drooping shape of the shoulder of the pattern opening.

Conversely, if the direction vector of the flow of the resist pattern due to the above-mentioned heat treatment is not large relative to the sum vector of the interfacial tension and the surface tension of the lower layer, the resist pattern becomes difficult to flow and the desired reduction amount is reduced. To ensure this, the heat treatment temperature must be set higher.
As a result, the wall shape of the resist pattern after resizing is curved in an arc shape, or the shoulder of the opening becomes a drooping shape,
This has an adverse effect on the processing steps of the layer to be processed.

Hereinafter, a specific example of this process will be described. Unless otherwise specified, the handling and implementation process of the photoresist solution after the microfiltration was performed in a clean room of a yellow room where temperature and humidity were controlled.
The exposure and development of the photoresist film can be performed according to a conventional method. As the substrate, a silicon wafer, a silicon wafer having steps on which various insulating films, wirings, electrodes, and the like are formed on the surface, other semiconductor wafers, and the like can be used. FIG. 5 shows a process flow of the method for forming a resist pattern. FIG.
FIG. 4 shows how the hole size of the resist pattern is reduced by this process.

Specific Example 1 First, a resist was applied to a thickness of 0.73 μm on a substrate.
A bare silicon wafer was used as a substrate. Further, as the resist material, a positive type chemically amplified resist for KrF (acetal type) was used, but the present invention is not limited to this, and any other resist material that causes heat flow can be used. Further, the exposure wavelength is not limited to KrF. Further, the baking temperature, heating temperature, and time described later are not limited to these. ACT8 manufactured by Tokyo Electron Ltd. was used for resist coating and development. Regarding application,
Although a coater was used, it is not limited to this. The same applies to the specific examples described later. Next, when a pattern was formed by selectively removing a desired portion of the resist by a normal photolithography process, the following steps were performed. After applying the resist, the coated substrate is placed on a hot plate and subjected to a pre-baking process at a heating temperature of 90 ° C. for 1 minute, and then a Nikon KrF scanner (N
In SR-202A), exposure was performed at an exposure amount of 60 mJ / cm ² through a photomask (reticle) having a contact hole pattern. Subsequently, the exposed substrate was placed on a hot plate and subjected to a post-exposure bake treatment at a heating temperature of 100 ° C. for 1 minute. After this, 2.
Development is carried out with a 38% aqueous solution of tetramethylammonium hydroxide, followed by rinsing with pure water to form a resist pattern (Step A).

Usually, after this, the substrate after development is placed on a hot plate and subjected to a post-baking process at a heating temperature of 110 ° C. for 1 minute, whereby a hole (a space of 0.52 μm) equivalent to a 260 nm diameter on the mask is formed. 240 design
nm contact hole pattern is formed. This is used as a reference (initial pattern) on a bare silicon wafer to show the effect of the above-described heat treatment.
In addition, the post-bake treatment described here refers to development,
This is a process for drying the wafer after rinsing.
On the other hand, the heat treatment that appears in many cases below refers to a process intended to flow and resize an initial resist pattern.

Example 2 The resist pattern formed in step A was heated to 140 ° C.
For 90 seconds. As a result, the hole pattern size became 198 nm.

As in Example 3 , a resist was applied to a thickness of 0.73 μm on the substrate. As the substrate, a substrate in which a SiO ₂ film was formed on a bare silicon wafer was used. Further, the same positive type chemically amplified resist for KrF (acetal type) as used in Example 1 was used. Next, when a resist pattern was formed by selectively removing a desired portion of the resist by a normal photolithography process, the following steps were performed. After applying the resist, the coated substrate is placed on a hot plate and subjected to a pre-bake treatment at a heating temperature of 90 ° C. for 1 minute, and then a Nikon KrF scanner (NSR)
At -202A), exposure was performed at 53 mJ / cm ² through a photomask (reticle) having a contact hole pattern. Subsequently, the exposed substrate was placed on a hot plate and subjected to a post-exposure bake treatment at a heating temperature of 100 ° C. for 1 minute. Thereafter, the resist pattern is developed with a 2.38% aqueous solution of tetramethylammonium hydroxide and rinsed with pure water to form a resist pattern (Step B).

Usually, after this, the substrate after development is placed on a hot plate and subjected to a post-baking treatment at a heating temperature of 110 ° C. for 1 minute, whereby a hole (space 0.52 μm) having a diameter of 260 nm on the mask is obtained. 215 for the design of
nm contact hole pattern is formed. This is used as a reference (initial pattern) on the SiO ₂ film to show the effect of the above heat treatment.

Example 4 The resist pattern formed in the step B was 138 ° C.
For 90 seconds. As a result, the hole pattern size was 188 nm.

Example 5 The resist pattern formed in step B was
For 60 seconds. As a result, the hole pattern size was 177 nm.

Example 6 The resist pattern formed in step B was heated at 140 ° C.
For 90 seconds. As a result, the hole pattern size became 165 nm.

Specific Example 7 Next, a commercially available organic anti-reflection film for deep UV (for example, called BARC) is applied to a thickness of 70 nm on a bare silicon wafer, and is heated at 220 ° C. for 60 seconds. A resist was applied thereon with a thickness of 0.73 μm. Here, a commercially available deep UV is used as a resin composition film.
Organic anti-reflective material is used, but is not limited to this.
Does not cause intermixing with the resist film on the upper layer (that is, the two layers do not mix at the interface)
Any material can be used, and the antireflection function may not be provided depending on the purpose.

For coating the lower layer film, A
CT8 was used. Although a coater was used for application, it is not limited to this. Next, when a resist pattern was formed by selectively removing a desired portion of the resist by a normal photolithography process, the following steps were performed. After applying the resist, the coated substrate is placed on a hot plate and subjected to a pre-bake treatment at a heating temperature of 90 ° C. for 1 minute, and then a Nikon KrF scanner (NSR-20)
2A), exposure was performed at a light exposure of 59 mJ / cm ² through a photomask having a contact hole pattern. Subsequently, the exposed substrate is placed on a hot plate and
A post-exposure bake treatment was performed at a heating temperature of 00 ° C. for one minute. Thereafter, the resist pattern is developed with a 2.38% aqueous solution of tetramethylammonium hydroxide and rinsed with pure water to form a resist pattern (Step C).

Normally, after this, the substrate after development is placed on a hot plate and subjected to a post-baking process at a heating temperature of 110 ° C. for 1 minute, whereby a hole having a diameter of 260 nm (space 0.52 μm) on the mask is formed. 240 design
nm contact hole pattern is formed. This is used as a reference (initial pattern) in the case where a resin composition film layer is interposed between the substrate and the resist layer to show the effect of the above-described heat treatment.

EXAMPLE 8 The resist pattern formed in step C was 138.degree.
For 60 seconds. As a result, the hole pattern size was 201 nm.

EXAMPLE 9 The resist pattern formed in step C was 138.degree.
For 90 seconds. As a result, the hole pattern size was 183 nm.

FIG. 7 shows the amount of change in the pattern size under various conditions. FIG. 8 shows a cross-sectional shape of the wafer.

As described above, by interposing the resin composition film layer between the substrate and the resist layer, it becomes possible to expand the control range of the amount of reduction of the pattern dimension by the heat treatment after the pattern deformation. Thus, deformation of the resist pattern due to the heat treatment is suppressed, and a fine pattern with reduced dependency on density can be formed by providing a portion where the resin composition film layer exists and a portion where the resin composition film layer does not exist. In particular, a plurality of arrangement patterns having different densities, which are difficult to miniaturize, can form holes in the same layer, and the manufacture of an VLSI can be realized using photolithography.

[0055]

As described above, according to the present invention, when the softening temperature of a resist used for forming a resist pattern is T ₂ (° C.), the softening temperature falls within the range of T ₂ ≦ T ₁ ≦ T ₂ + 4 ° C. Heat treatment at a temperature T ₁ (° C.)
After performing the first heat treatment at a temperature T ₃ (° C.) within a range of T ₃ <T _2, a _second heat treatment is performed at a temperature T ₁ (° C.) within a range of T ₁ ≧ T ₂ , Alternatively, T ₂ -2 ° C. ≦ T ₃ <T
_From the temperature T ₃ (° C.) within the range of ₂ , T ₂ ≦ T ₁ ≦ T ₂ +
By performing the heat treatment while continuously changing the temperature to a temperature T ₁ (° C.) within the range of 4 ° C., the pattern size can be reduced with high dimensional controllability regardless of the density of the pattern. Can be planned.

[Brief description of the drawings]

FIG. 1 is a schematic diagram showing a temperature relationship of a heat treatment in a method for forming a resist pattern according to the present invention.

FIG. 2 is a schematic diagram illustrating a process flow of a method for forming a resist pattern according to an embodiment of the present invention.

FIG. 3 is a schematic diagram for explaining the effect of the method for forming a resist pattern according to one embodiment of the present invention;

FIG. 4 is a schematic diagram showing the density dependence by a reflow process in the method for forming a resist pattern according to one embodiment of the present invention;

FIG. 5 is a schematic diagram showing a process flow for explaining another method for reducing a pattern size.

FIG. 6 is a cross-sectional view for explaining another method for reducing a pattern dimension.

FIG. 7 is a schematic diagram for explaining an effect of another method for reducing a pattern dimension.

FIG. 8 is a schematic diagram for explaining another method for reducing a pattern size.

Claims (60)

[Claims] 1. A after forming a resist pattern by lithography, the resist pattern forming method which is to perform a heat treatment to adjust the pattern dimension, the softening temperature of the resist used for forming the resist pattern T ₂ A method of forming a resist pattern, wherein the heat treatment is performed at a temperature T ₁ (° C.) in a range of T ₂ ≦ T ₁ ≦ T ₂ + 4 ° C. 2. The formation of a resist pattern according to claim 1, wherein said heat treatment is performed at a temperature T ₁ (° C.) within a range of T ₂ ≦ T ₁ ≦ T ₂ + 3.5 ° C. Method. 3. The method for forming a resist pattern according to claim 1, wherein said heat treatment is performed at a temperature T ₁ (° C.) within a range of T ₂ ≦ T ₁ ≦ T ₂ + 3 ° C. 4. The resist pattern according to claim 1, wherein said heat treatment is performed at a temperature T ₁ (° C.) within a range of T ₂ + 0.5 ° C. ≦ T ₁ ≦ T ₂ + 4 ° C. Formation method. 5. T ₂ + 0.5 ° C. ≦ T ₁ ≦ T ₂ + 3.5 ° C.
2. The method for forming a resist pattern according to claim 1, wherein the heat treatment is performed at a temperature T ₁ (° C.) within the range of ( ₁ ). 6. The resist pattern according to claim 1, wherein said heat treatment is performed at a temperature T ₁ (° C.) within a range of T ₂ + 0.5 ° C. ≦ T ₁ ≦ T ₂ + 3 ° C. Formation method. 7. The formation of a resist pattern according to claim 1, wherein said heat treatment is performed at a temperature T ₁ (° C.) within a range of T ₂ + 1 ° C. ≦ T ₁ ≦ T ₂ + 4 ° C. Method. 8. The resist pattern according to claim 1, wherein said heat treatment is performed at a temperature T ₁ (° C.) within a range of T ₂ + 1 ° C. ≦ T ₁ ≦ T ₂ + 3.5 ° C. Formation method. 9. The formation of a resist pattern according to claim 1, wherein said heat treatment is performed at a temperature T ₁ (° C.) within a range of T ₂ + 1 ° C. ≦ T ₁ ≦ T ₂ + 3 ° C. Method. 10. The method according to claim 1, wherein the resist pattern has a repetitive pattern. 11. A method for forming a resist pattern, wherein after forming a resist pattern by lithography, a heat treatment is performed to adjust the pattern dimension, wherein the softening temperature of the resist used for forming the resist pattern is set to T _2. (° C.), performing a first heat treatment at a temperature T ₃ (° C.) within a range of T ₃ <T ₂ , and after performing the first heat treatment, satisfying T ₁ ≧ T ₂ Performing a second heat treatment at a temperature T ₁ (° C.) within the range. 12. The resist pattern according to claim 11, wherein the first heat treatment is performed at a temperature T ₃ (° C.) in a range of T ₂ −2 ° C. ≦ T ₃ <T _2. Formation method. 13. The resist pattern according to claim 11, wherein the second heat treatment is performed at a temperature T ₁ (° C.) in a range of T ₂ ≦ T ₁ ≦ T ₂ + 4 ° C. Forming method. 14. The first heat treatment is performed at a temperature T ₃ (° C.) in a range of T ₂ -2 ° C. ≦ T ₃ <T ₂ , and T ₂ ≦ T ₁
12. The method of forming a resist pattern according to claim 11, wherein the second heat treatment is performed at a temperature T ₁ (° C.) in a range of ≦ T ₂ + 4 ° C. 15. The method according to claim 11, wherein the first heat treatment is performed at a temperature T ₃ (° C.) in a range of T ₂ −1.5 ° C. ≦ T ₃ <T ₂ . A method for forming a resist pattern. 16. The resist pattern according to claim 11, wherein the first heat treatment is performed at a temperature T ₃ (° C.) in a range of T ₂ -1 ° C. ≦ T ₃ <T _2. Formation method. 17. The method according to claim 11, wherein the first heat treatment is performed at a temperature T ₃ (° C.) in a range of T ₂ −0.5 ° C. ≦ T ₃ <T ₂ . A method for forming a resist pattern. 18. The method according to claim 1, wherein the first heat treatment is performed at a temperature T ₃ (° C.) in a range of T ₂ −2 ° C. ≦ T ₃ ≦ T ₂ −0.5 ° C. 12. The method for forming a resist pattern according to item 11. 19. T_Two-1.5 ° C ≦ T_Three≤T_Two-0.5
Temperature T in the range of ° C _Three(° C) to perform the first heat treatment.
The resist according to claim 11, wherein:
Pattern formation method. 20. The method according to claim 1, wherein the first heat treatment is performed at a temperature T ₃ (° C.) in a range of T ₂ -1 ° C. ≦ T ₃ ≦ T ₂ −0.5 ° C. 12. The method for forming a resist pattern according to item 11. 21. The resist according to claim 11, wherein the second heat treatment is performed at a temperature T ₁ (° C.) in a range of T ₂ ≦ T ₁ ≦ T ₂ + 3.5 ° C. The method of forming the pattern. 22. The resist pattern according to claim 11, wherein the second heat treatment is performed at a temperature T ₁ (° C.) in a range of T ₂ ≦ T ₁ ≦ T ₂ + 3 ° C. Forming method. 23. The method according to claim 11, wherein the second heat treatment is performed at a temperature T ₁ (° C.) in a range of T ₂ + 0.5 ° C. ≦ T ₁ ≦ T ₂ + 4 ° C. Method of forming resist pattern. 24. T_Two+ 0.5 ° C ≦ T₁≤T_Two+3.5
Temperature T in the range of ° C ₁(° C) to perform the second heat treatment.
The resist according to claim 11, wherein:
Pattern formation method. 25. The method according to claim 11, wherein the second heat treatment is performed at a temperature T ₁ (° C.) in a range of T ₂ + 0.5 ° C. ≦ T ₁ ≦ T ₂ + 3 ° C. Method of forming resist pattern. 26. The resist according to claim 11, wherein the second heat treatment is performed at a temperature T ₁ (° C.) in a range of T ₂ + 1 ° C. ≦ T ₁ ≦ T ₂ + 4 ° C. The method of forming the pattern. 27. The method according to claim 11, wherein the second heat treatment is performed at a temperature T ₁ (° C.) within a range of T ₂ + 1 ° C. ≦ T ₁ ≦ T ₂ + 3.5 ° C. Method of forming resist pattern. 28. The formation of a resist pattern according to claim 11, wherein said heat treatment is performed at a temperature T ₁ (° C.) in a range of T ₂ + 1 ° C. ≦ T ₁ ≦ T ₂ + 3 ° C. Method. 29. The method according to claim 11, wherein the resist pattern has a repeating pattern. 30. A method for forming a resist pattern, comprising forming a resist pattern by lithography and then performing a heat treatment to adjust the pattern dimension, wherein T ₂ −2 ° C. ≦ T ₃ <T ₂ Temperature T ₁ (° C.) within the range of T ₂ ≦ T ₁ ≦ T ₂ + 4 ° C. from the temperature T ₃ (° C.)
A method of forming a resist pattern, wherein the heat treatment is performed while continuously changing the temperature. After forming the 31. The resist pattern by lithography, in a manufacturing method of a semiconductor device having a step of performing heat treatment to adjust the pattern dimension, the resist pattern a softening temperature of the resist used to form the T ₂ (C) wherein the heat treatment is performed at a temperature T ₁ (° C.) within a range of T ₂ ≦ T ₁ ≦ T ₂ + 4 ° C. 32. The semiconductor device according to claim 31, wherein the heat treatment is performed at a temperature T ₁ (° C.) in a range of T ₂ ≦ T ₁ ≦ T ₂ + 3.5 ° C. Method. 33. The method according to claim 31, wherein the heat treatment is performed at a temperature T ₁ (° C.) in a range of T ₂ ≦ T ₁ ≦ T ₂ + 3 ° C. 34. The semiconductor device according to claim 31, wherein the heat treatment is performed at a temperature T ₁ (° C.) in a range of T ₂ + 0.5 ° C. ≦ T ₁ ≦ T ₂ + 4 ° C. Manufacturing method. 35. T_Two+ 0.5 ° C ≦ T₁≤T_Two+3.5
Temperature T in the range of ° C ₁(° C)
32. The semiconductor device according to claim 31, wherein
Production method. 36. The semiconductor device according to claim 31, wherein the heat treatment is performed at a temperature T ₁ (° C.) within a range of T ₂ + 0.5 ° C. ≦ T ₁ ≦ T ₂ + 3 ° C. Manufacturing method. 37. The semiconductor device according to claim 31, wherein the heat treatment is performed at a temperature T ₁ (° C.) in a range of T ₂ + 1 ° C. ≦ T ₁ ≦ T ₂ + 4 ° C. Method. 38. The semiconductor device according to claim 31, wherein the heat treatment is performed at a temperature T ₁ (° C.) in a range of T ₂ + 1 ° C. ≦ T ₁ ≦ T ₂ + 3.5 ° C. Manufacturing method. 39. The semiconductor device according to claim 31, wherein the heat treatment is performed at a temperature T ₁ (° C.) in a range of T ₂ + 1 ° C. ≦ T ₁ ≦ T ₂ + 3 ° C. Method. 40. The method according to claim 37, wherein the least pattern has a repeating pattern. 41. A method for manufacturing a semiconductor device, comprising the step of forming a resist pattern by lithography and then performing a heat treatment for adjusting the pattern dimension, wherein the softening temperature of the resist used for forming the resist pattern is set to T _2. (° C.), performing a first heat treatment at a temperature T ₃ (° C.) within a range of T ₃ <T ₂ , and after performing the first heat treatment, satisfying T ₁ ≧ T ₂ Performing a second heat treatment at a temperature T ₁ (° C.) within the range. 42. The semiconductor device according to claim 41, wherein the first heat treatment is performed at a temperature T ₃ (° C.) in a range of T ₂ −2 ° C. ≦ T ₃ <T _2. Manufacturing method. 43. The semiconductor device according to claim 41, wherein the second heat treatment is performed at a temperature T ₁ (° C.) in a range of T ₂ ≦ T ₁ ≦ T ₂ + 4 ° C. Production method. 44. The first heat treatment is performed at a temperature T ₃ (° C.) in a range of T ₂ -2 ° C. ≦ T ₃ <T ₂ , and T ₂ ≦ T ₁
42. The method of manufacturing a semiconductor device according to claim 41, wherein the second heat treatment is performed at a temperature T ₁ (° C.) in a range of ≦ T ₂ + 4 ° C. 45. The method according to claim 41, wherein the first heat treatment is performed at a temperature T ₃ (° C.) in a range of T ₂ −1.5 ° C. ≦ T ₃ <T ₂ . A method for manufacturing a semiconductor device. 46. The semiconductor device according to claim 41, wherein said first heat treatment is performed at a temperature T ₃ (° C.) in a range of T ₂ -1 ° C. ≦ T ₃ <T _2. Manufacturing method. 47. The method according to claim 41, wherein the first heat treatment is performed at a temperature T ₃ (° C.) in a range of T ₂ −0.5 ° C. ≦ T ₃ <T ₂ . A method for manufacturing a semiconductor device. 48. The first heat treatment at a temperature T ₃ (° C.) in a range of T ₂ -2 ° C. ≦ T ₃ ≦ T ₂ −0.5 ° C. 42. The method for manufacturing a semiconductor device according to 41. 49. T_Two-1.5 ° C ≦ T_Three≤T_Two-0.5
Temperature T in the range of ° C _Three(° C) to perform the first heat treatment.
42. The semiconductor according to claim 41, wherein:
Device manufacturing method. 50. The first heat treatment at a temperature T ₃ (° C.) in a range of T ₂ -1 ° C. ≦ T ₃ ≦ T ₂ −0.5 ° C. 42. The method for manufacturing a semiconductor device according to 41. 51. The semiconductor according to claim 41, wherein the second heat treatment is performed at a temperature T ₁ (° C.) in a range of T ₂ ≦ T ₁ ≦ T ₂ + 3.5 ° C. Device manufacturing method. 52. The semiconductor device according to claim 41, wherein said second heat treatment is performed at a temperature T ₁ (° C.) in a range of T ₂ ≦ T ₁ ≦ T ₂ + 3 ° C. Production method. 53. The method according to claim 41, wherein the second heat treatment is performed at a temperature T ₁ (° C.) in a range of T ₂ + 0.5 ° C. ≦ T ₁ ≦ T ₂ + 4 ° C. Of manufacturing a semiconductor device. 54. T_Two+ 0.5 ° C ≦ T₁≤T_Two+3.5
Temperature T in the range of ° C ₁(° C) to perform the second heat treatment.
42. The semiconductor according to claim 41, wherein:
Device manufacturing method. 55. The method according to claim 41, wherein the second heat treatment is performed at a temperature T ₁ (° C.) in a range of T ₂ + 0.5 ° C. ≦ T ₁ ≦ T ₂ + 3 ° C. Of manufacturing a semiconductor device. 56. The semiconductor according to claim 41, wherein the second heat treatment is performed at a temperature T ₁ (° C.) in a range of T ₂ + 1 ° C. ≦ T ₁ ≦ T ₂ + 4 ° C. Device manufacturing method. 57. The method according to claim 41, wherein the second heat treatment is performed at a temperature T ₁ (° C.) within a range of T ₂ + 1 ° C. ≦ T ₁ ≦ T ₂ + 3.5 ° C. Of manufacturing a semiconductor device. 58. The semiconductor device according to claim 41, wherein the heat treatment is performed at a temperature T ₁ (° C.) in a range of T ₂ + 1 ° C. ≦ T ₁ ≦ T ₂ + 3 ° C. Method. 59. The method according to claim 50, wherein the resist pattern has a repetitive pattern. 60. A method for manufacturing a semiconductor device, comprising the step of performing a heat treatment for adjusting a pattern size after forming a resist pattern by lithography, wherein T ₂ −2 ° C. ≦ T ₃ <T ₂ Temperature T ₁ (° C.) within the range of T ₂ ≦ T ₁ ≦ T ₂ + 4 ° C. from the temperature T ₃ (° C.)
Wherein the heat treatment is performed while continuously changing the temperature.