JP2002230060A - Method for calculating number of division of memory and method for the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To shorten the time to generate a storage device whose delay is a little. SOLUTION: The delay time of a memory can be approximated by a×W+b (W is the number of words and (a) and b are constants), and when the delay time of a selector for selecting one signal from C input signals is d, an integral value M which is the closest to a value m to be calculated from m= loge(a×A×logeC/d) is calculated so that M-th power of the C can be defined as a number of division which is N in a step S2. Thus, it is possible to generate a storage device whose delay is minimized.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of calculating the number of divisions of a memory of a semiconductor integrated circuit, a method of generating a storage device, a memory division number calculation device, and a storage device generation device.
In particular, the present invention relates to a memory division number calculation method and a storage device generation method, a memory division number calculation device, and a storage device generation device that minimize a delay speed of reading data from a memory.

[0002]

2. Description of the Related Art Conventionally, a memory incorporated in a semiconductor integrated circuit has to be selected from a fixed library. However, in recent years, CAD (Computer Aided D
esign) Advances in technology have allowed circuit designers to freely specify specifications and create memories.

However, even though the specification can be freely selected, the items that can be selected are limited only by the number of words and the like, and the setting range is limited. Therefore, a large-capacity memory cannot be made, or even if it can be made, the delay speed cannot be satisfied.
Therefore, when a high-speed and large-capacity memory is required, a single memory is not generally used. Instead, a storage device that combines small memories and performs the same operation as a large-capacity memory is used.

FIG. 7 is a flowchart of a storage device generation method in a conventional CAD system. In this conventional storage device generation method, a designer first inputs the number of words A as shown in the flowchart of FIG.
1). Next, the designer inputs the number N of memory divisions (step S12). Then, N A / N word memories are generated (step S13). Then, a selector tree for selecting the outputs of the N memories is generated (Step S).
14).

[0005] Next, the delay value of the memory generated in step S13 and the delay value of the selector tree generated in step S14 are summed to obtain a delay value as a storage device (step S15). Then, if the delay value of the storage device satisfies the required specification, the process ends. If the delay value does not satisfy the required specification, the process proceeds to step S17 (step S1).
6). In step S17, the number of memory divisions N is changed, and the process returns to step S12.

[0006]

The conventional storage device generation method is performed from the above steps. If the delay value of the storage device does not satisfy the requirement, steps S12 to S16 must be repeated, and There was a problem that a lot of time was required to generate the device.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and a method of calculating the number of memory partitions, a method of generating a memory device, and a method of calculating the number of memory partitions, which eliminates repetition of processing and reduces the time for generating a storage device It is an object to provide a device and a storage device generation device.

[0008]

In order to achieve the above object, the method of calculating the number of memory divisions according to the present invention uses a memory delay time of a × W + b (where W is the number of words and a and b are constants).
And a delay time of a selector for selecting one signal from the C input signals is a memory division number calculation method for a semiconductor integrated circuit, in which a required word number A is input. The first step and m = log e (a × A
.Times.log eC / d) (Equation 1), calculating an integer value M closest to the value m, and outputting the C power of M as the number of divisions N.

According to the storage device generation method of the present invention, the delay time of a memory can be approximated by a × W + b, and the delay time of a selector for selecting one signal from C input signals is d.
A first step of inputting a required number of words A, and calculating an integer M closest to a value m obtained from (Equation 1). A second step of calculating the M-th power as the number of divisions N, and a third step of generating N memories of A / N words according to the number of divisions N calculated in the second step.
And a fourth step of generating a selector tree for selecting one from the outputs of the N memories according to the number of divisions N determined in the second step.

The memory division number calculation device according to the present invention is a semiconductor device in which the delay time of a memory can be approximated by a × W + b, and the delay time of a selector for selecting one signal from C input signals is d. A memory division number calculation device for an integrated circuit, wherein when a required word number A is input, an integer value M closest to a value m obtained from (Equation 1) is calculated, and C is raised to the Mth power by the division number. N is output.

In the storage device generation apparatus of the present invention, the delay time of the memory can be approximated by a × W + b, and the delay time of the selector for selecting one signal from the C input signals is d.
And when the required number of words A is input, calculates the integer M closest to the value m obtained from (Equation 1) and divides the C to the Mth power A memory division number calculating means for outputting as the number N; a memory generation means for generating N memories of A / N words according to the division number N;
Selector tree generating means for generating a selector tree for selecting one from the outputs of the memories.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A general memory is schematically shown in FIG. Generally, as shown in FIG. 2, a memory is a memory cell array 10 in which memory cells for actually storing data are gathered.
, An address decoder 11 and an input / output buffer 12. The address decoder 11 decodes an input address, and selects an address line 13 of a selected memory cell.
Drive. The memory cell array 10 performs input / output of a selected memory cell based on an address line 13 from an address decoder 11. The input / output buffer 12 amplifies the input / output signal of the memory cell array 10 because the input / output signal is weak.

Therefore, the length of the data line 14 until the data read from the memory cell is transmitted to the input / output buffer 12 is proportional to the number of words. The delay time is proportional to the length of the data line through which the signal is transmitted.

Therefore, the delay time Tacc of the memory is given by (Equation 2)
(Where W is the number of words,
a and b are constants).

[0015]

(Equation 2)

Accordingly, if the required number of words of the memory is A and the memory is divided into N memories and used, the number of words per memory is A / N words. Since the access speed of the memory is (Equation 2), it can be set as (Equation 3).

[0017]

(Equation 3)

If a selector 20 that can select one signal from two signals is used, output signals from two memories can be selected as shown in FIG. If two selectors 20 are connected in series as shown in FIG. 5, four memories can be selected.

Similarly, the use of the T-stage selector 20 enables the selection of 2 T memories, and the use of the T-stage selector that can select one signal from the C signals. It is possible to select C to the Tth power. Conversely, to select N memories, a selector that selects from C signals may be used in log ↓ cN stages.

Therefore, assuming that the delay time per stage of the selector that selects from the C signals is d, the delay time Tsel of the selector tree that selects N memories is

[0021]

(Equation 4)

## EQU1 ## In summary, the total delay time T including the selector tree when the memory is divided into N is

[0023]

(Equation 5)

## EQU1 ## Also, the access time T is set to the number of divisions N
Differentiating with

[0025]

(Equation 6)

## EQU1 ## Therefore,

[0027]

(Equation 7)

If N is α, then N, a, d, A,
Since C is all positive, ∂T / ∂N is negative when N <α, N
= Α when 0, and positive when N> α.

Therefore, as shown in (Table 1), the total access time T decreases as N increases when N <α, takes a minimum value when N = α, and decreases when N> α. It increases as it gets larger.

[0030]

[Table 1]

Therefore, the division number N

[0032]

(Equation 8)

By setting the value close to the above, the total access time can be reduced. However, since the number of stages of the selector must be an integer value, assuming that the number of stages of the selector is M, M is an integer value closest to m obtained from m = log e (a × A × log eC / d) (Equation 1) Must.

Thus, by setting the number of divisions N to C to the power of M, the total access time including the selector can be minimized.

FIG. 3 shows a CA according to an embodiment of the present invention.
FIG. 2 is a block diagram illustrating a hardware configuration of a D system. A CAD system for performing the storage device generation includes a central processing unit (CPU) 1 and a data input / output system 2 for storing data necessary for storage device generation and inputting / outputting data.
It is composed of

Here, the data input / output system 2 includes an input device 3 including a keyboard and a mouse for inputting necessary data and instructions for a circuit designer to generate a storage device, and a data input / output system 2 for generating the storage device. It comprises a disk device 4 for storing necessary integrated circuit parameters and generated design data of a storage device, and a main storage device 5 for storing the input device 3, a control program for the disk device 4, and the like. The central processing unit 1 also includes a memory division number calculation unit 6
And a memory generation means 7 and a selector tree generation means 8.

The memory division number calculation means 6 selects one signal from the number of words A of the storage device input from the input device 3, the parameter a of the memory stored in the disk device, and the C signals. From the delay value d of the selector to be executed, m is obtained from the equation (Equation 1), the nearest integer M is calculated,
Is sent to the memory generation means 7 and the selector tree generation means 8 as the memory division number N.

The memory generation means 7 determines the A / A based on the number of divisions N sent from the memory division number calculation means 6 and the parameters necessary for memory generation stored in the disk device 4.
N pieces of N-word memory design data are generated and stored in the disk device. The selector tree generating means 8 selects one of the outputs of the N memories from the number of divisions N sent from the memory division number calculating means 6 and the data of the integrated circuit stored in the disk device 4. Is generated and stored in the disk device 4.

Hereinafter, the memory delay time Tacc is 0.01 ×
It can be approximated by W + 2 ns (W is the number of words) and the delay time of the selector for selecting one signal from two signals is 0.45 ns
A design operation for generating a 512-word storage device in a semiconductor integrated circuit will be described with reference to the flowchart of FIG.

The memory delay time Tacc is 0.01 × W + 2
ns, and the delay time of the selector is 0.45 ns, so the parameters in (Equation 1) are a = 0.01, C =
2, d = 0.45, and this value is stored in the storage device 4.

First, the designer inputs "512" as the word number A using the input device 3 (step S1). Next, in the memory division number calculation means 6, m = 2.97 is obtained from the input word number “512” and the data stored in the main storage device 5 using the equation (Equation 1). Since the nearest integer M is 3, C is raised to the power of M by 2 to 3.
The power is calculated, and 8 is output as the memory division number (step S2).

Next, in the memory generating means 7, the number of divisions 8 outputted from the memory dividing number calculating means 6 and the semiconductor parameters stored in the disk device 4 are used to calculate 512/8.
Eight = 64 words of memory design data are generated and written to the disk device 4 (step S3).

Next, in the selector tree generating means 8, the division number 8 output from the memory division number calculating means 6
And design data of a selector tree for selecting eight memories from the semiconductor parameters stored in the disk device 4, and writes the design data to the disk device 4 (step S
4).

FIG. 6 shows the generated design data of the storage device. The delay time of the generated storage device is the delay time of the 64-word memory of 0.01.
× 64 + 2 = 2.64 ns, three-stage selector tree 0.45
× 3 = 1.35 ns, which is 3.99 ns.

If the data is divided into nine memories, 5
Since 12/9 = 56.88, it is divided into 56 words and 57 words of memory. The delay time of the 56-word memory is 0.01 × 56 + 2 = 2.56 ns, and the delay time of the 57-word memory is 0.01 × 57 + 2 = 2.57 ns. Since the selector tree for selecting nine memories has four stages of selectors, the delay time of the selector tree is 0.45.
× 4 = 1.80 ns. The total storage device delay time is 2.57 + 1.80 = 4.37 ns, which is greater than 3.99 ns when divided into eight memories.

If the memory is divided into seven memories, 5
Since 12/7 = 73.14, the memory is divided into 73-word and 74-word memories. The delay time of the 73 word memory is 0.01 × 73 + 2 = 2.73 ns, and the delay time of the 74 word memory is 0.01 × 74 + 2 = 2.74 ns. Since the selector tree for selecting seven memories has three stages of selectors, the delay time of the selector tree is 0.4.
5 × 3 = 1.35 ns. The total storage device delay time is 2.74 + 1.35 = 4.09 ns, which is greater than 3.99 ns when divided into eight memories.

If the selector tree has four levels and the memory is divided into 16 parts, which can divide the memory most, since 512/16 = 32, the memory is divided into 32 words. The delay time of a 32-word memory is 0.01 × 32 + 2 = 2.32 ns, and the delay time of four stages of a selector tree for selecting 16 memories is 0.45 × 4 = 1.
80 ns. Total storage delay is 2.32+
1.80 = 4.12 ns, which is larger than 3.99 ns when divided into eight memories.

If the memory is divided into four parts which can divide the memory most when the selector tree has two stages,
Since 512/4 = 128, the memory is divided into 128 words. The delay time of a 128-word memory is 0.01 × 128 + 2 = 3.28 ns, and the delay time of a two-stage selector tree for selecting four memories is 0.45 × 2 = 0.45 ns.
90 ns. Total storage delay is 3.28+
0.90 = 4.18 ns, which is larger than 3.99 ns when divided into eight memories.

As described above, the storage device generation method according to the present embodiment can generate the storage device with the least delay without repeated processing, and has the effect of reducing the time required to generate the storage device.

In this embodiment, the delay time of the memory
Although the case of a semiconductor integrated circuit in which Tacc can be approximated by 0.01 × W + 2 ns (W is the number of words) has been described, the same effect can be obtained even when the coefficient which is a parameter is different.

In this embodiment, 1 signal is output from two signals.
Although the case where the selector tree is formed by using the selectors for selecting the three signals has been described, the same effect can be obtained by forming the selector tree by using the selector for selecting one signal from three or more signals. I can do it.

In this embodiment, the case of the semiconductor integrated circuit in which the delay time of the selector is 0.45 ns has been described, but the same effect can be obtained even when the delay time which is a parameter is different.

When the memory division number calculating means used in the present embodiment is used, the same effect can be obtained by using another selector tree generating means without using the selector tree generating means.

If the memory division number calculating means used in this embodiment is used, the same effect can be obtained even if another memory generating means is used without using the memory generating means.

[0055]

As described above, the method of calculating the number of memory divisions according to the present invention can calculate the number of memory divisions in a storage device with the least delay without repetitive processing, thereby reducing the time required to generate a storage device. have.

The storage device generation method of the present invention can generate a storage device with the least delay without repetitive processing, and has the effect of shortening the time required to generate a storage device.

The memory division number calculation device of the present invention can calculate the number of memory divisions in the storage device with the least delay without repetitive processing, and has the effect of shortening the time for generating the storage device.

The storage device generation apparatus of the present invention can generate a storage device with the least delay without repetitive processing, and has the effect of reducing the time required to generate a storage device.

[Brief description of the drawings]

FIG. 1 is a flowchart of a storage device generation method according to an embodiment of the present invention;

FIG. 2 is a diagram schematically showing a general memory;

FIG. 3 is a block diagram illustrating a configuration of a storage device generation device according to an embodiment of the present invention.

FIG. 4 is a diagram showing an example of a selector tree for selecting two memories.

FIG. 5 is a diagram showing an example of a selector tree for selecting four memories.

FIG. 6 is a diagram showing a storage device generated by a storage device generation method according to an embodiment of the present invention;

FIG. 7 is a flowchart of a conventional storage device generation method.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Central processing unit (CPU) 2 Data input / output system 3 Input device 4 Disk device 5 Main storage device 6 Memory division number calculation means 7 Memory generation means 8 Selector tree generation means 10 Memory cell array 11 Address decoder 12 Input / output buffer 13 Address line 14 data line 20 selector 21 memory

Claims (4)

[Claims] A delay time of a selector for selecting one signal from C input signals can be approximated by a × W + b (W is the number of words, a and b are constants). a memory division number calculation method for a semiconductor integrated circuit, wherein d is a first step of inputting a required number of words A; And calculating the integer value M closest to the value m obtained from the above, and outputting the C power of the M as the number of divisions N. 2. The delay time of a memory which can be approximated by a × W + b (W is the number of words, a and b are constants), and the delay time of a selector for selecting one signal from C input signals. d, a method for generating a storage device for a semiconductor integrated circuit, wherein a first step of inputting a required number of words A;
Calculate the integer value M closest to the value m obtained from (Equation 1),
A second step of calculating the M to the power of M as the number of divisions N, and the number of divisions N calculated in the second step
A third step of generating N memories of A / N words according to the following formula: and a selector tree for selecting one from the outputs of the N memories according to the division number N determined in the second step And a fourth step of generating a storage device. 3. The delay time of a memory which can be approximated by a × W + b (W is the number of words, a and b are constants), and the delay time of a selector for selecting one signal from C input signals. a memory division number calculation device for a semiconductor integrated circuit, wherein when d is a required word number A, an integer value M closest to a value m obtained from (Equation 1) is calculated; A memory division number calculation device which outputs a power as a division number N. 4. The delay time of a memory which can be approximated by a × W + b (W is the number of words, a and b are constants), and the delay time of a selector for selecting one signal from C input signals. a memory device generation device for a semiconductor integrated circuit, wherein d is a number, and an integer value M closest to a value m obtained from inputting the required number of words A (Equation 1) is calculated; Memory division number calculation means for outputting as the division number N; memory generation means for generating N memories of A / N words according to the division number N determined by the memory division number calculation means; And a selector tree generating means for generating a selector tree for selecting one from outputs of the N memories according to the number of divisions N determined by the number calculating means.