JP2002229921A - Interface circuit, logical circuit verification method, logical device, information processing equipment - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve such a problem that every conventional means for increasing the speed of the simulation of logical circuit requires the extraction process of specific circuit and the element for the determination, and the process thereof requires considerable design man-hours, and that a circuit different from the logical circuit, unlike the hardware model, is produced for performing the simulation, so that the time taken for the debug for the verification of validity thereof is generated. SOLUTION: This logical device is composed of a device A3 having a cycle of operation controlling mechanism 9, a device B4 composed of LSIA 46, LSIB 47, LSIC 48 equipped with interface circuits 10 that operate on different clocks respectively and have, like the device A3, the cycle of operation controlling mechanisms 9, and an other connected device 5 composed of a plurality of LSID 51s and LSIE 51s equipped with the interface circuits 10 having, like the device A3, the cycle of operation controlling mechanisms 9. Regarding the device A3, the device B4 and the other connected device 5, the data transmission between the device B4 and the device connected thereto is made in the same or a different cycle of operation.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to an interface circuit, and more particularly to a control mechanism for facilitating logic verification of an interface circuit.

[0002]

2. Description of the Related Art Conventional simulation speed-up or efficiency improvement methods are disclosed in, for example, JP-A-11-96196, "Circuit Conversion Method and Circuit Design Support Device", and
As disclosed in JP-A-149385, “Logic Circuit Simulation Apparatus and Simulation Method”, a logic circuit is converted to reduce the number of data transfers without changing the output operation timing of the logic circuit to be simulated. Or a means to extract specific combinational circuits to reduce registers and change register allocation positions, or to simplify clock signals,
The simulation was speeded up by designating variable conversion of a register signal or the like.

Conventionally used large-scale circuit simulation methods include an event-driven system and a cycle-based system. The event-driven method is a method in which if there is a change in the input of an element at a certain time, the logical operation of the element is performed at the next time, and if there is no change, nothing is performed. A change (event) in the signal value is detected, the signal value is sequentially propagated, and the time is updated only when all the signals have no change.

In the cycle-based method, dependencies are statically analyzed in advance in the processing of a simulation model, and the execution order of processes and the like is determined so that the result is the same at the time of clock division as in the event-driven simulation. The entire circuit is evaluated for a predetermined number of times for each clock. The cycle-based simulation is not used to verify the timing, but is used to perform high-speed verification with a focus on function confirmation.

[0005]

SUMMARY OF THE INVENTION For example, JP-A-11-9
The above-described means disclosed in Japanese Unexamined Patent Application Publication No. 6196 “Circuit conversion method and circuit design support device” and Japanese Unexamined Patent Application Publication No. 10-149385 “Logic circuit simulation device and its simulation method” are used for designing hardware such as LSI. Along with the increase in the scale, a process for extracting a specific circuit and an element for determination are all required for speeding up the simulation, and the process requires a great deal of design man-hours. Further, since a circuit different from a hardware model and a logic circuit different from the hardware model is generated and simulated, there is a problem that time required for debugging for verifying the validity is generated.

The cycle-based method often does not allow or ignore the delay written in the assignment reservation description of a signal other than the clock signal. The cycle-based simulation can be performed at a higher speed than the event-driven simulation. However, in a configuration in which the operation cycle in a device or an LSI differs from the operation cycle between devices or between LSIs, the operation cycle is slow. Simulation time depends on the As a result, for example, a simulation time is required to verify the internal logic of the connected device or the LSI, so that it is not possible to efficiently evaluate the competition of the LSI internal logic.

An object of the present invention is to provide an operation cycle control mechanism for improving efficiency and speeding apart from the original operation, for example, to reduce an interface operated by n clocks to 1 / 4n
A mechanism that operates with a clock is provided, and when performing logic verification or actual device evaluation using this high-speed function, high-speed transfer is performed by setting the mode flag with a specific instruction and switching the control of the definer signal In the actual operation environment, for example, when devices are connected by a cable of several meters to several tens of meters or more, a mode operable by the operation cycle switching mechanism described above. Set to
The purpose is to directly and directly input a signal using an external device such as a pulse generator and evaluate the logic circuit of the connected device at high speed and efficiently.

[0008]

A first interface circuit according to the present invention comprises: a mode flag for setting an operation cycle of an interface circuit to a high-speed mode or a normal mode without changing an interface between logic circuits; And a means for switching a refiner clock according to the state of the mode flag, and a means for controlling an input / output signal of the interface circuit by the refiner clock.

According to a first logic circuit verification method of the present invention, a first procedure for describing a logic circuit in a hardware description language, a mode flag for setting a high-speed operation cycle mode or a normal mode of the logic circuit, An operation cycle control comprising: a determination unit for determining a state of the mode flag; a unit for switching a refiner clock according to the state of the mode flag; and a unit for controlling an input / output signal of the interface circuit by the refiner clock. A second procedure of describing a mechanism in a hardware description language, a third step of inputting a logic model described in a hardware description language of the logic circuit and the operation cycle control mechanism by a simulator, and Set high-speed mode and run simulation on the simulator Ri has a fourth step of executing.

A second interface circuit according to the present invention is an interface circuit comprising an input section for inputting a command and data from a serial bus, and an output section for outputting a response to the command to the serial bus. The input unit and the output unit are respectively a mode flag for setting an operation cycle high-speed mode or a normal mode of the interface circuit, a determination unit for determining a state of the mode flag, and a definer based on the state of the mode flag. Means for switching a clock, means for controlling input / output signals of the interface circuit by the definer clock, an instruction decode circuit for decoding the instruction,
A counter for counting the number of transfers;
An operation cycle control comprising: an adder for adding a transfer number; a shift register for bit-shifting the data; a transfer count holding unit for holding a transfer count; and a comparison circuit for comparing the value of the counter with the transfer count holding unit. Has a mechanism.

A logic device according to the present invention includes a second interface circuit according to the present invention and an internal logic circuit for executing an instruction from the interface circuit.

In the information processing apparatus according to the present invention, the central processing unit, the input / output device, and the storage device, each having the second interface circuit according to the present invention, are mutually connected.

According to a second logic circuit verification method of the present invention, a mode flag for setting an operation cycle high-speed mode or a normal mode of an interface circuit, a determination means for determining a state of the mode flag, Setting a mode flag to a high-speed mode when evaluating an interface circuit having means for switching a refiner clock according to the state of the interface circuit and means for controlling an input / output signal of the interface circuit by the definer clock. The evaluation is performed according to a procedure and a second procedure of directly supplying a signal from the external device to the interface circuit.

[0014]

Next, embodiments of the present invention will be described in detail with reference to the drawings. First, the operation of the embodiment of the present invention will be described with reference to the drawings. Figure 1
FIG. 2 is a block diagram showing a configuration of a logic device 1 interconnected by using an interface circuit 10 having an operation cycle control mechanism 9 according to the embodiment of the present invention, and inputs to the simulator 2 of an HDL description of the logic device 1. Referring to FIG.
A device A3 including an operation cycle control mechanism 9, a device B4 including an LSIA 46, an LSIB 47, and an LSIC 48 each operating at a different clock and including an interface circuit 10 including the operation cycle control mechanism 9 like the device A3; Similar to the device A3, the connection device 5 includes a plurality of LSIDs 51 and an LSIE 52 each including an interface circuit 10 having an operation cycle control mechanism 9, and includes devices A3, B4,
The other connection device 5 performs data transfer between the devices connected to the device B4 in the same or different operation cycles. The specific mechanism of the operation cycle control mechanism 9 will be described with reference to FIGS.

The apparatus A3, apparatus B4, other connecting apparatus 5 and LSIA 46, ISIB 47, LSIC 48,
The LSID 51 and the LSIE 52 are supplied with a basic clock and a heterogeneous clock for all the devices, and further operate according to a definer signal that defines the timing of holding or storing in each device or in the LSI. The operation cycle of the interface between the devices is controlled and operated at the same or slower frequency than the operation cycle of the device or the device.

In order to perform logic verification in the logic circuit of each of the above devices, a hardware description language (eg, HDL, Ha) of the logic circuit of the devices A3, B4, and the other connection device 5
The logic verification model 1 is created from the description described in the rdware description language), and the operation verification is performed by the simulator 2 for verifying the operation of the logic verification model. Hardware description languages include, for example, HDL (Hard
ware description Language).

Next, the interface circuit 10 including the operation cycle control mechanism 9 will be described with reference to FIG. FIG. 2 shows an interface circuit 1 according to an embodiment of the present invention.
FIG. 3 is a block diagram showing a configuration of a 0. Apparatus A in FIG.
The interface circuit 10 for connecting the device 3 to the device B4 or the device B4 and the other connection device 5 includes the following elements.

A control line 102, a control line 104 including a command strobe, a command code, and a serial bus use request signal for controlling input / output between the devices, the control line 102, the control line 1
04, an address, a destination code, a serial bus 101 for transferring data, an input unit 12 for receiving an output of a connected device via a control line 102 and a signal line 103, and a command code received by the input unit 12. A signal transmitted from the input unit 12 via the signal line 106 and a signal line 109 output from the instruction decode circuit 14 via the signal line 108 and transmitted from the connected device. The transfer count holding unit 15 for holding the transfer count of the instruction, and the signal line 1 from the instruction decode circuit 14
The counter 16 counts the number of transfers according to each command received through the counter 10 and is reset at the end of the transfer.
Has an adder circuit 17 for counting up the value of. At the time of counting up, it is written to the counter 16 by the signal line 112.

The instruction code transmitted through the signal line 107 and the address (A), destination code (C) and data (D) transmitted through the signal line 108 are bit-shifted by the value of the counter 16. And a comparison circuit 18 for comparing the output of the transfer count holding unit 15 transmitted via the signal line 111 with the value transmitted via the signal line 113. The comparison circuit 18 compares the value of the transfer count holding unit 15 with the value of the counter 16 and outputs “1” when they match, and outputs “0” when they do not match. When the comparison circuit 18 outputs "1", the command transmitted by the connection destination device or the LSI is transmitted to the receiving device or the LSI by the instruction code, address,
The transmission destination code and data are regarded as reception completed, and the signal line 11
At the same time as transmitting the strobe signal of the command received via the command line 4, the command code, address, transmission destination code and data stored in the shift register 19 are transmitted to the internal logic circuit 11 via the signal line 115.

Further, the determination circuit 22 determines whether the output of the comparison circuit 18 is "1" and the information stored in the shift register 19, and the output on the left is set to the mode flag 21 via the signal line 116. . The value set in the mode flag 21 is transmitted to the definer switching circuit 20 via the signal line 117, and the definer switching circuit 20 switches the refiner signal transmitted via the signal line 119. The output of the definer switching circuit 20 is a signal line 118
Through the transfer cycle holding unit 15, the counter 16, the shift register 19, the mode flag 21, and the input unit 12 in the operation cycle control mechanism 9.

The output unit 13 includes an operation cycle control mechanism 9 for controlling a signal transmitted from the input unit 12, and includes a start signal transmitted via a signal line 120 and a start signal transmitted via a signal line 121. Instruction code, address,
The destination code and the data are received, and the refiner signal distributed via the signal line 119 is switched by the refiner switching circuit 20 in the operation cycle control mechanism 9 to control the output to the connection destination. The output of the output processing unit 13 transmits a signal including an instruction strobe, an instruction code, and a serial bus use request signal via the control line 104, and
5 are connected to the serial bus 101, and each instruction is processed between devices or between LSIs.

The internal logic circuit 11 includes a storage unit, a logical arithmetic function unit and the like, and performs each instruction processing.

FIG. 3 is a block diagram showing a configuration of the definer switching circuit 20 included in the interface circuit 10 according to the embodiment of the present invention. Definer switching circuit 20
Stores the refiner signal transmitted via the signal line 119 from the flip-flop 30 to the flip-flop 31 and further to the flip-flop 32, and outputs the above-mentioned outputs to each of the OR circuits 33, 34 and 34. The logical sum is calculated by 35. From each of the flip-flops 30 to the flip-flop 31, the output of the flip-flop 32 and the OR circuit 33, the OR circuit 34
The output of the OR circuit 35 is selected by the selector 36 according to the set value of the mode flag 21 transmitted via the signal line 117 by the selector 36, and the number of transfers in the operation cycle control mechanism 9 is held via the signal line 118. Part 15,
Counter 16, shift register 19, mode flag 2
1, and distributed to the input unit 12 and controlled.

Next, an example of an instruction transferred between devices will be described with reference to FIG. FIG. 4 is a diagram illustrating an example of an instruction transferred by the interface circuit 10 according to the embodiment of the present invention. Although a plurality of commands are transmitted and received between the device A3, the device B4, and the other connection device 5, a transfer cycle when executing an 8-byte write command will be described here. phase
Is variable depending on the data length of each instruction, and indicates the phase of each cycle occupying the interface between the devices. Here, since an 8-byte write instruction is taken as an example, data transfer is performed in a total of 80 phases. 16
144 bytes for byte instructions and 52 bytes for 64 byte write instructions
Requires 8 phases.

Strobe indicates that a serial bus use request is permitted, indicates a valid signal of an instruction, and indicates the start Phase of each instruction.
It becomes "1" in synchronization with e. Although not explicitly shown in the figure, an instruction code (here, an 8-byte instruction code) is transmitted from the connection source device in a phase in which the Strobe signal is “1”. Data is an 8-bit destination code C (0) to C (8) transmitted via the serial bus 101, and an 8-bit wide address A (0) to A (0).
(8) shows a phase in each transfer cycle in the case where data D (0) to D (64) having a width of 8 bytes are transferred bit-serial.

Next, with reference to FIGS. 5 and 6, an operation at the time of executing an 8-byte write instruction executed between devices or between LSIs will be described. FIG. 5 is a diagram showing a timing chart during the normal operation of the 8-byte write instruction transferred by the interface circuit 10 according to the embodiment of the present invention. Here, the LSIA 46 of the devices A3 and B4 in FIG. 3 will be described in the same manner as described above. The internal logic circuit 11 of the device A3 and the internal circuit of the LSIA 46 are CLK
1 Normal device A3 and LSIA4
It is assumed that the circuit operates during one-fourth cycle of CLK1 during period 6.

FIG. 5 shows a case of a normal operation in which the mode flag 21 of the operation cycle control mechanism 9 is set to all "0". Will be delivered to During normal operation, T00 = 1, T04 = 1,
As in T08 = 1, it becomes "1" in one cycle every 4T. 1T indicates one clock of CLK1. STB1
Is a valid signal for permitting a serial bus request and transmitting a command from a transmission source device. This signal is "1" for 4T according to the interface specifications. STB2 is a strobe signal received at the transmission destination.
1 ". At the same time, the instruction code is transmitted from the transmission source device. CNT is a value stored in the counter 16 of FIG. 1 and indicates the value of Phase of each instruction in FIG.
The addition circuit 17 counts up in accordance with the number of transmissions transmitted.

DATA1 is a destination code (C), address (A), and data (D) transmitted from the transmission source device via the serial bus 101. DATA2 is a device in which a receiving device sequentially receives data according to a transfer cycle. D63 is the last bit of the data of the 8-byte write instruction, and the receiving device receives all the data in T321. STB3 is the internal logic circuit 1
This is a strobe signal for outputting an 8-byte instruction to T1, and when the value of the counter 16 matches the value of the transfer count holding unit 15 in T32
1 becomes "1". At the same time, the destination code (C), address (A), and data (D) stored in the shift register 19 are transmitted to the internal logic circuit 11 and processed for each instruction. In other words, during normal operation, an 8-byte instruction requiring 321T is received and processed.

Next, a case where the data speed is increased by the operation cycle control mechanism 9 will be described. This case is used only when speeding up the operation verification. Since the high-speed mode is not executed between the actual devices, a reserve code or an instruction for switching the definer to an unused address is assigned as pre-processing on the interface specification. Here, address = FF (he
x). The initial operation is the same as the above-described operation, and is transferred in a cycle of 1 / 4T.
Set to a high-speed mode other than "0". In this case, L
In the internal logic circuit 11 in the SI, the above instruction (address = F
F (hex)) is invalidated. Since the setting has already been completed in the device, the device is switched by the definer switching circuit 20 in accordance with the value set in the mode flag 21, and the operation controlled by the output (DEF_OUT) is simulated.

FIG. 6 is a diagram showing a timing chart in the 8-byte write instruction high-speed mode operation transferred by the interface circuit 10 according to the embodiment of the present invention. The definer (DEF_OUT) becomes a level signal with "1". Therefore, the command transmitted from the issuing source in synchronization with CLK1 is processed. At T01, the information of Phase 1 is received. At T80, all information of the 8-byte instruction is received.
From 81, the processing of each instruction is performed in the internal logic circuit 11.

By setting the mode to the high-speed mode, what required 321T is reduced to 80T, so that the logic verification can be efficiently performed.
The internal logic circuit 11 in the SI can be verified in a shorter time than usual. The instruction for setting the high-speed mode is added to the existing test vector, and there is almost no burden on the logic designer. Although the high-speed mode is implemented by actual HW coding, the HW of the entire LSI is implemented.
In terms of volume, it is extremely small and does not pose a problem. Further, the conventional process of extracting a specific function and the process of converting a logic circuit are not required, and there is no debugging work for the process described on the left, so that high-speed and efficient logic verification can be realized.
In this embodiment, an example is given of the LSIA 46 without the device A3 and the device B4. However, the logic verification is carried out between the other devices by providing the above-described mechanism, thereby increasing the speed and efficiency of the logic verification of the entire device. Is realized.

FIG. 7 is a block diagram showing a configuration at the time of evaluation using the external device 60 of the logical device 1 having the operation cycle control mechanism 9 according to the embodiment of the present invention. Apparatus A of FIG.
When the device 3 and the device B4 are connected in an actual operating environment, for example, by a cable of several meters to several tens of meters or more, an external device 60 such as a pulse generator is used instead of the device A3 of FIG. The output is switched to the definer output operable by the operation cycle control mechanism 9 described above, and the operation of the LSI in the device B4 and the logic circuit of another device connected to the device B4 are verified.

In other words, even in an interface in which cables are connected by several to several tens of meters or more between devices and data transfer takes a long time, signals can be directly input from the external device device.
The operation of the logic circuit of the device itself can be verified without directly connecting to the device 3, and efficient evaluation can be performed. Therefore, quality can be improved at an early stage, and at the same time, short-term development becomes possible.

FIG. 8 is a block diagram showing a configuration of the information processing apparatus according to the embodiment of the present invention. Central processing unit 901,
The storage device 902 and the input / output device 903 are connected to each other by the serial bus 101 and mutually transfer data and instructions to execute processing.

[0035]

The effect of the present invention is as follows. By adding a mechanism for controlling the operation cycle with a relatively small amount of HW without changing the signal line of the interface between the devices or the LSI, the connection destination device or the LSI can be obtained. Accelerate internal logic verification and significantly reduce logic verification time.

Further, by providing the above-described mechanism between devices or LSIs operating at different operation clocks, the definer signal can be easily switched and the maximum data transfer can be realized. Becomes possible. In the actual operating environment, for example, when the devices are connected by a cable of several meters to several tens of meters or more, the operation cycle switching mechanism is set to the high-speed operation mode, and the external device (pulse generator) and the like are set. The logic circuit of the connection destination device can be evaluated at high speed and efficiently by directly inputting a signal.

As described above, high-speed and efficient verification of a logic circuit is realized by implementing the present invention, and verification of a logic circuit is accelerated.
Quality can be improved, and there is an effect that the device development TAT can be shortened. That is, in the device or LSI design, it is possible to perform the logic circuit verification by simulation and the logic verification circuit verification in an actual operating environment after development at high speed and efficiently.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a logic device 1 interconnected by using an interface circuit 10 having an operation cycle control mechanism 9 according to an embodiment of the present invention and an input to a simulator 2 of an HDL description of the logic device 1; .

FIG. 2 is a block diagram showing a configuration of an interface circuit 10 according to the embodiment of the present invention.

FIG. 3 is a block diagram illustrating a configuration of a definer switching circuit 20 included in the interface circuit 10 according to the embodiment of the present invention.

FIG. 4 is a diagram showing an example of an instruction transferred by the interface circuit 10 according to the embodiment of the present invention.

FIG. 5 is a diagram showing a timing chart in a normal operation of an 8-byte write instruction transferred by the interface circuit 10 according to the embodiment of the present invention.

FIG. 6 is a diagram showing a timing chart in an 8-byte write instruction high-speed mode operation transferred by the interface circuit 10 according to the embodiment of the present invention.

FIG. 7 is a block diagram showing a configuration at the time of evaluation using an external device of the logical device 1 having the operation cycle control mechanism 9 according to the embodiment of the present invention.

FIG. 8 is a block diagram illustrating a configuration of an information processing apparatus according to an embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Logic device 2 Simulator 3 Device A 4 Device B 5 Other connection device 9 Operation cycle control mechanism 10 Interface circuit 11 Internal logic circuit 12 Input unit 13 Output unit 14 Instruction decode circuit 15 Transfer count holding unit 16 Counter 17 Addition circuit 18 Comparison circuit Reference Signs List 19 shift register 20 definer switching circuit 21 mode flag 22 determination circuit 30 flip-flop 31 flip-flop 32 flip-flop 33 logical OR circuit 34 logical OR circuit 35 logical OR circuit 36 selector 46 LSIA 47 LSIB 48 LLIC 51 LSID 52 LSIIE 60 external device 101 Serial bus 102 control line 103 signal line 104 control line 105 signal line 106 signal line 107 signal line 108 signal line 109 signal line 110 signal line 111 signal line 112 Line 113 signal line 114 signal line 115 signal line 116 signal line 117 signal line 118 signal line 119 signal line 120 signal line 121 signal line 901 the central processing unit 902 memory 903 input and output device

Claims (6)

[Claims] A mode flag for setting an operation cycle of an interface circuit to a high-speed mode or a normal mode without changing an interface between logic circuits;
Determining means for determining the state of the mode flag;
An interface circuit, comprising: means for switching a definer clock according to a state of the mode flag; and means for controlling input / output signals of the interface circuit by the definer clock. 2. A first procedure for describing a logic circuit in a hardware description language, a mode flag for setting a high-speed operation cycle mode or a normal mode of the logic circuit, and determining a state of the mode flag. , An operation cycle control mechanism having means for switching a definer clock according to the state of the mode flag, and means for controlling an input / output signal of the interface circuit by the definer clock is described in a hardware description language. A second procedure, a third step of inputting a logic model described in a hardware description language of the logic circuit and the operation cycle control mechanism by a simulator, and setting the mode flag to a high-speed mode to execute a simulation by the simulator. Has a fourth step performed by A logic circuit verification method, characterized in that: 3. An interface circuit comprising an input unit for inputting an instruction and data from a serial bus, and an output unit for outputting a response to the instruction to the serial bus, wherein the input unit and the output unit are A mode flag for setting an operation cycle high-speed mode or a normal mode of the interface circuit, a determination unit for determining a state of the mode flag, a unit for switching a refiner clock according to a state of the mode flag, Means for controlling an input / output signal of the interface circuit with a definer clock, an instruction decode circuit for decoding the instruction, a counter for counting the number of transfers, and an adder for adding 1 to the value of the counter;
A shift register for bit-shifting the data, an operation cycle control mechanism including a transfer count holding unit for holding a transfer count, and a comparison circuit for comparing the value of the counter with the transfer count holding unit. Interface circuit. 4. A logic device comprising: the interface circuit according to claim 3; and an internal logic circuit for executing an instruction from the interface circuit. 5. An information processing apparatus comprising: a central processing unit, an input / output device, and a storage device, each having the interface circuit according to claim 3; 6. A mode flag for setting an operation cycle of the interface circuit to a high-speed mode or a normal mode, a determination unit for determining a state of the mode flag, and a unit for switching a refiner clock according to the state of the mode flag. A first procedure for setting the mode flag to a high-speed mode when evaluating an interface circuit having means for controlling input / output signals of the interface circuit by the definer clock; and A logic circuit verification method, wherein the evaluation is performed according to a second procedure for directly providing a signal from the logic circuit.